Linux kernel mirror (for testing)
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linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12
13/*
14 * This assumes you have a 1.8432 MHz clock for your UART.
15 *
16 * It'd be nice if someone built a serial card with a 24.576 MHz
17 * clock, since the 16550A is capable of handling a top speed of 1.5
18 * megabits/second; but this requires the faster clock.
19 */
20#define BASE_BAUD (1843200 / 16)
21
22/* Standard COM flags (except for COM4, because of the 8514 problem) */
23#ifdef CONFIG_SERIAL_DETECT_IRQ
24#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
25#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
26#else
27#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29#endif
30
31#ifdef CONFIG_MACH_JAZZ
32#include <asm/jazz.h>
33
34#ifndef CONFIG_OLIVETTI_M700
35 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
36 exactly which ones ... XXX */
37#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
38#else
39/* but the M700 isn't such a strange beast */
40#define JAZZ_BASE_BAUD BASE_BAUD
41#endif
42
43#define _JAZZ_SERIAL_INIT(int, base) \
44 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
45 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
46 .io_type = SERIAL_IO_MEM }
47#define JAZZ_SERIAL_PORT_DEFNS \
48 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
50#else
51#define JAZZ_SERIAL_PORT_DEFNS
52#endif
53
54/*
55 * Both Galileo boards have the same UART mappings.
56 */
57#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
58#include <asm/galileo-boards/ev96100.h>
59#include <asm/galileo-boards/ev96100int.h>
60#define EV96100_SERIAL_PORT_DEFNS \
61 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
62 .flags = STD_COM_FLAGS, \
63 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
64 .io_type = SERIAL_IO_MEM }, \
65 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
66 .flags = STD_COM_FLAGS, \
67 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
68 .io_type = SERIAL_IO_MEM },
69#else
70#define EV96100_SERIAL_PORT_DEFNS
71#endif
72
73#ifdef CONFIG_MIPS_ITE8172
74#include <asm/it8172/it8172.h>
75#include <asm/it8172/it8172_int.h>
76#include <asm/it8712.h>
77#define ITE_SERIAL_PORT_DEFNS \
78 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
79 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
80 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
81 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
82 /* Smart Card Reader 0 */ \
83 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
84 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
85 /* Smart Card Reader 1 */ \
86 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
87 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
88#else
89#define ITE_SERIAL_PORT_DEFNS
90#endif
91
92#ifdef CONFIG_MIPS_IVR
93#include <asm/it8172/it8172.h>
94#include <asm/it8172/it8172_int.h>
95#define IVR_SERIAL_PORT_DEFNS \
96 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
97 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
98 /* Smart Card Reader 1 */ \
99 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
100 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
101#else
102#define IVR_SERIAL_PORT_DEFNS
103#endif
104
105#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
106#define STD_SERIAL_PORT_DEFNS \
107 /* UART CLK PORT IRQ FLAGS */ \
108 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
109 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
110 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
111 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
112
113#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
114#define STD_SERIAL_PORT_DEFNS
115#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
116
117#ifdef CONFIG_MOMENCO_JAGUAR_ATX
118/* Ordinary NS16552 duart with a 20MHz crystal. */
119#define JAGUAR_ATX_UART_CLK 20000000
120#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
121
122#define JAGUAR_ATX_SERIAL1_IRQ 6
123#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
124
125#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
126 { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
127 .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
128 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
129 io_type: SERIAL_IO_MEM }
130#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
131 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
132#else
133#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
134#endif
135
136#ifdef CONFIG_MOMENCO_OCELOT_3
137#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
138#define OCELOT_3_SERIAL_IRQ 6
139#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
140
141#define _OCELOT_3_SERIAL_INIT(int, base) \
142 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
143 .flags = STD_COM_FLAGS, \
144 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
145 io_type: SERIAL_IO_MEM }
146
147#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
148 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
149#else
150#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
151#endif
152
153#ifdef CONFIG_MOMENCO_OCELOT
154/* Ordinary NS16552 duart with a 20MHz crystal. */
155#define OCELOT_BASE_BAUD ( 20000000 / 16 )
156
157#define OCELOT_SERIAL1_IRQ 4
158#define OCELOT_SERIAL1_BASE 0xe0001020
159
160#define _OCELOT_SERIAL_INIT(int, base) \
161 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
162 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
163 .io_type = SERIAL_IO_MEM }
164#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
165 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
166#else
167#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
168#endif
169
170#ifdef CONFIG_MOMENCO_OCELOT_G
171/* Ordinary NS16552 duart with a 20MHz crystal. */
172#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
173
174#define OCELOT_G_SERIAL1_IRQ 4
175#if 0
176#define OCELOT_G_SERIAL1_BASE 0xe0001020
177#else
178#define OCELOT_G_SERIAL1_BASE 0xfd000020
179#endif
180
181#define _OCELOT_G_SERIAL_INIT(int, base) \
182 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
183 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
184 .io_type = SERIAL_IO_MEM }
185#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
186 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
187#else
188#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
189#endif
190
191#ifdef CONFIG_MOMENCO_OCELOT_C
192/* Ordinary NS16552 duart with a 20MHz crystal. */
193#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
194
195#define OCELOT_C_SERIAL1_IRQ 80
196#define OCELOT_C_SERIAL1_BASE 0xfd000020
197
198#define OCELOT_C_SERIAL2_IRQ 81
199#define OCELOT_C_SERIAL2_BASE 0xfd000000
200
201#define _OCELOT_C_SERIAL_INIT(int, base) \
202 { .baud_base = OCELOT_C_BASE_BAUD, \
203 .irq = (int), \
204 .flags = STD_COM_FLAGS, \
205 .iomem_base = (u8 *) base, \
206 .iomem_reg_shift = 2, \
207 .io_type = SERIAL_IO_MEM \
208 }
209#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
210 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
211 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
212#else
213#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
214#endif
215
216#ifdef CONFIG_DDB5477
217#include <asm/ddb5xxx/ddb5477.h>
218#define DDB5477_SERIAL_PORT_DEFNS \
219 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
220 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
221 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
222 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
223 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
224 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
225#else
226#define DDB5477_SERIAL_PORT_DEFNS
227#endif
228
229#ifdef CONFIG_SGI_IP32
230/*
231 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
232 * They are initialized in ip32_setup
233 */
234#define IP32_SERIAL_PORT_DEFNS \
235 {},{},
236#else
237#define IP32_SERIAL_PORT_DEFNS
238#endif /* CONFIG_SGI_IP32 */
239
240#define SERIAL_PORT_DFNS \
241 DDB5477_SERIAL_PORT_DEFNS \
242 EV96100_SERIAL_PORT_DEFNS \
243 IP32_SERIAL_PORT_DEFNS \
244 ITE_SERIAL_PORT_DEFNS \
245 IVR_SERIAL_PORT_DEFNS \
246 JAZZ_SERIAL_PORT_DEFNS \
247 STD_SERIAL_PORT_DEFNS \
248 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
249 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
250 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
251 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
252
253#endif /* _ASM_SERIAL_H */