tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Declarations of procedures and variables shared between files
3 * in arch/ppc/mm/.
4 *
5 * Derived from arch/ppc/mm/init.c:
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 *
8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
9 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
10 * Copyright (C) 1996 Paul Mackerras
11 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
12 *
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
20 *
21 */
22#include <asm/tlbflush.h>
23#include <asm/mmu.h>
24
25extern void mapin_ram(void);
26extern int map_page(unsigned long va, phys_addr_t pa, int flags);
27extern void setbat(int index, unsigned long virt, unsigned long phys,
28 unsigned int size, int flags);
29extern void reserve_phys_mem(unsigned long start, unsigned long size);
30extern void settlbcam(int index, unsigned long virt, phys_addr_t phys,
31 unsigned int size, int flags, unsigned int pid);
32extern void invalidate_tlbcam_entry(int index);
33
34extern int __map_without_bats;
35extern unsigned long ioremap_base;
36extern unsigned long ioremap_bot;
37extern unsigned int rtas_data, rtas_size;
38
39extern unsigned long total_memory;
40extern unsigned long total_lowmem;
41extern int mem_init_done;
42
43extern PTE *Hash, *Hash_end;
44extern unsigned long Hash_size, Hash_mask;
45
46extern unsigned int num_tlbcam_entries;
47
48/* ...and now those things that may be slightly different between processor
49 * architectures. -- Dan
50 */
51#if defined(CONFIG_8xx)
52#define flush_HPTE(X, va, pg) _tlbie(va)
53#define MMU_init_hw() do { } while(0)
54#define mmu_mapin_ram() (0UL)
55
56#elif defined(CONFIG_4xx)
57#define flush_HPTE(X, va, pg) _tlbie(va)
58extern void MMU_init_hw(void);
59extern unsigned long mmu_mapin_ram(void);
60
61#elif defined(CONFIG_FSL_BOOKE)
62#define flush_HPTE(X, va, pg) _tlbie(va)
63extern void MMU_init_hw(void);
64extern unsigned long mmu_mapin_ram(void);
65extern void adjust_total_lowmem(void);
66
67#else
68/* anything except 4xx or 8xx */
69extern void MMU_init_hw(void);
70extern unsigned long mmu_mapin_ram(void);
71
72/* Be careful....this needs to be updated if we ever encounter 603 SMPs,
73 * which includes all new 82xx processors. We need tlbie/tlbsync here
74 * in that case (I think). -- Dan.
75 */
76static inline void flush_HPTE(unsigned context, unsigned long va,
77 unsigned long pdval)
78{
79 if ((Hash != 0) &&
80 cpu_has_feature(CPU_FTR_HPTE_TABLE))
81 flush_hash_pages(0, va, pdval, 1);
82 else
83 _tlbie(va);
84}
85#endif