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Linux kernel mirror (for testing)
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linux
1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/workqueue.h>
28#include <linux/sysdev.h>
29
30#define LS_SIZE (256 * 1024)
31#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flags indicating progress during context switch. */
102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
104
105struct spu_context;
106struct spu_runqueue;
107
108struct spu {
109 char *name;
110 unsigned long local_store_phys;
111 u8 *local_store;
112 unsigned long problem_phys;
113 struct spu_problem __iomem *problem;
114 struct spu_priv1 __iomem *priv1;
115 struct spu_priv2 __iomem *priv2;
116 struct list_head list;
117 struct list_head sched_list;
118 int number;
119 int nid;
120 unsigned int irqs[3];
121 u32 isrc;
122 u32 node;
123 u64 flags;
124 u64 dar;
125 u64 dsisr;
126 size_t ls_size;
127 unsigned int slb_replace;
128 struct mm_struct *mm;
129 struct spu_context *ctx;
130 struct spu_runqueue *rq;
131 unsigned long long timestamp;
132 pid_t pid;
133 int prio;
134 int class_0_pending;
135 spinlock_t register_lock;
136
137 void (* wbox_callback)(struct spu *spu);
138 void (* ibox_callback)(struct spu *spu);
139 void (* stop_callback)(struct spu *spu);
140 void (* mfc_callback)(struct spu *spu);
141
142 char irq_c0[8];
143 char irq_c1[8];
144 char irq_c2[8];
145
146 struct sys_device sysdev;
147};
148
149struct spu *spu_alloc(void);
150void spu_free(struct spu *spu);
151int spu_irq_class_0_bottom(struct spu *spu);
152int spu_irq_class_1_bottom(struct spu *spu);
153void spu_irq_setaffinity(struct spu *spu, int cpu);
154
155/* system callbacks from the SPU */
156struct spu_syscall_block {
157 u64 nr_ret;
158 u64 parm[6];
159};
160extern long spu_sys_callback(struct spu_syscall_block *s);
161
162/* syscalls implemented in spufs */
163extern struct spufs_calls {
164 asmlinkage long (*create_thread)(const char __user *name,
165 unsigned int flags, mode_t mode);
166 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
167 __u32 __user *ustatus);
168 struct module *owner;
169} spufs_calls;
170
171#ifdef CONFIG_SPU_FS_MODULE
172int register_spu_syscalls(struct spufs_calls *calls);
173void unregister_spu_syscalls(struct spufs_calls *calls);
174#else
175static inline int register_spu_syscalls(struct spufs_calls *calls)
176{
177 return 0;
178}
179static inline void unregister_spu_syscalls(struct spufs_calls *calls)
180{
181}
182#endif /* MODULE */
183
184
185/*
186 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
187 */
188
189union mfc_tag_size_class_cmd {
190 struct {
191 u16 mfc_size;
192 u16 mfc_tag;
193 u8 pad;
194 u8 mfc_rclassid;
195 u16 mfc_cmd;
196 } u;
197 struct {
198 u32 mfc_size_tag32;
199 u32 mfc_class_cmd32;
200 } by32;
201 u64 all64;
202};
203
204struct mfc_cq_sr {
205 u64 mfc_cq_data0_RW;
206 u64 mfc_cq_data1_RW;
207 u64 mfc_cq_data2_RW;
208 u64 mfc_cq_data3_RW;
209};
210
211struct spu_problem {
212#define MS_SYNC_PENDING 1L
213 u64 spc_mssync_RW; /* 0x0000 */
214 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
215
216 /* DMA Area */
217 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
218 u32 mfc_lsa_W; /* 0x3004 */
219 u64 mfc_ea_W; /* 0x3008 */
220 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
221 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
222 u32 dma_qstatus_R; /* 0x3104 */
223 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
224 u32 dma_querytype_RW; /* 0x3204 */
225 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
226 u32 dma_querymask_RW; /* 0x321c */
227 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
228 u32 dma_tagstatus_R; /* 0x322c */
229#define DMA_TAGSTATUS_INTR_ANY 1u
230#define DMA_TAGSTATUS_INTR_ALL 2u
231 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
232
233 /* SPU Control Area */
234 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
235 u32 pu_mb_R; /* 0x4004 */
236 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
237 u32 spu_mb_W; /* 0x400c */
238 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
239 u32 mb_stat_R; /* 0x4014 */
240 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
241 u32 spu_runcntl_RW; /* 0x401c */
242#define SPU_RUNCNTL_STOP 0L
243#define SPU_RUNCNTL_RUNNABLE 1L
244 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
245 u32 spu_status_R; /* 0x4024 */
246#define SPU_STOP_STATUS_SHIFT 16
247#define SPU_STATUS_STOPPED 0x0
248#define SPU_STATUS_RUNNING 0x1
249#define SPU_STATUS_STOPPED_BY_STOP 0x2
250#define SPU_STATUS_STOPPED_BY_HALT 0x4
251#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
252#define SPU_STATUS_SINGLE_STEP 0x10
253#define SPU_STATUS_INVALID_INSTR 0x20
254#define SPU_STATUS_INVALID_CH 0x40
255#define SPU_STATUS_ISOLATED_STATE 0x80
256#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
257#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
258 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
259 u32 spu_spe_R; /* 0x402c */
260 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
261 u32 spu_npc_RW; /* 0x4034 */
262 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
263
264 /* Signal Notification Area */
265 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
266 u32 signal_notify1; /* 0x1400c */
267 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
268 u32 signal_notify2; /* 0x1c00c */
269} __attribute__ ((aligned(0x20000)));
270
271/* SPU Privilege 2 State Area */
272struct spu_priv2 {
273 /* MFC Registers */
274 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
275
276 /* SLB Management Registers */
277 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
278 u64 slb_index_W; /* 0x1108 */
279#define SLB_INDEX_MASK 0x7L
280 u64 slb_esid_RW; /* 0x1110 */
281 u64 slb_vsid_RW; /* 0x1118 */
282#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
283#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
284#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
285#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
286#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
287#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
288#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
289#define SLB_VSID_4K_PAGE (0x0 << 8)
290#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
291#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
292#define SLB_VSID_CLASS_MASK (0x1ull << 7)
293#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
294 u64 slb_invalidate_entry_W; /* 0x1120 */
295 u64 slb_invalidate_all_W; /* 0x1128 */
296 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
297
298 /* Context Save / Restore Area */
299 struct mfc_cq_sr spuq[16]; /* 0x2000 */
300 struct mfc_cq_sr puq[8]; /* 0x2200 */
301 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
302
303 /* MFC Control */
304 u64 mfc_control_RW; /* 0x3000 */
305#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
306#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
307#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
308#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
309#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
310#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
311#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
312#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
313#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
314#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
315#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
316#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
317#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
318#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
319#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
320#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
321#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
322#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
323#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
324#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
325#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
326#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
327 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
328
329 /* Interrupt Mailbox */
330 u64 puint_mb_R; /* 0x4000 */
331 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
332
333 /* SPU Control */
334 u64 spu_privcntl_RW; /* 0x4040 */
335#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
336#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
337#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
338#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
339#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
340#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
341#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
342#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
343 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
344 u64 spu_lslr_RW; /* 0x4058 */
345 u64 spu_chnlcntptr_RW; /* 0x4060 */
346 u64 spu_chnlcnt_RW; /* 0x4068 */
347 u64 spu_chnldata_RW; /* 0x4070 */
348 u64 spu_cfg_RW; /* 0x4078 */
349 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
350
351 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
352 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
353 u64 spu_tag_status_query_RW; /* 0x5008 */
354#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
355#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
356 u64 spu_cmd_buf1_RW; /* 0x5010 */
357#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
358#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
359 u64 spu_cmd_buf2_RW; /* 0x5018 */
360#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
361#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
362#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
363 u64 spu_atomic_status_RW; /* 0x5020 */
364} __attribute__ ((aligned(0x20000)));
365
366/* SPU Privilege 1 State Area */
367struct spu_priv1 {
368 /* Control and Configuration Area */
369 u64 mfc_sr1_RW; /* 0x000 */
370#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
371#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
372#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
373#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
374#define MFC_STATE1_RELOCATE_MASK 0x10ull
375#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
376 u64 mfc_lpid_RW; /* 0x008 */
377 u64 spu_idr_RW; /* 0x010 */
378 u64 mfc_vr_RO; /* 0x018 */
379#define MFC_VERSION_BITS (0xffff << 16)
380#define MFC_REVISION_BITS (0xffff)
381#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
382#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
383 u64 spu_vr_RO; /* 0x020 */
384#define SPU_VERSION_BITS (0xffff << 16)
385#define SPU_REVISION_BITS (0xffff)
386#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
387#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
388 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
389
390 /* Interrupt Area */
391 u64 int_mask_RW[3]; /* 0x100 */
392#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
393#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
394#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
395#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
396#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
397#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
398#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
399#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
400#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
401#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
402#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
403#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
404 u8 pad_0x118_0x140[0x28]; /* 0x118 */
405 u64 int_stat_RW[3]; /* 0x140 */
406 u8 pad_0x158_0x180[0x28]; /* 0x158 */
407 u64 int_route_RW; /* 0x180 */
408
409 /* Interrupt Routing */
410 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
411
412 /* Atomic Unit Control Area */
413 u64 mfc_atomic_flush_RW; /* 0x200 */
414#define mfc_atomic_flush_enable 0x1L
415 u8 pad_0x208_0x280[0x78]; /* 0x208 */
416 u64 resource_allocation_groupID_RW; /* 0x280 */
417 u64 resource_allocation_enable_RW; /* 0x288 */
418 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
419
420 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
421
422 u64 smf_sbi_signal_sel; /* 0x3c8 */
423#define smf_sbi_mask_lsb 56
424#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
425#define smf_sbi_mask (0x301LL << smf_sbi_shift)
426#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
427#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
428#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
429#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
430 u64 smf_ato_signal_sel; /* 0x3d0 */
431#define smf_ato_mask_lsb 35
432#define smf_ato_shift (63 - smf_ato_mask_lsb)
433#define smf_ato_mask (0x3LL << smf_ato_shift)
434#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
435#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
436 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
437
438 /* TLB Management Registers */
439 u64 mfc_sdr_RW; /* 0x400 */
440 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
441 u64 tlb_index_hint_RO; /* 0x500 */
442 u64 tlb_index_W; /* 0x508 */
443 u64 tlb_vpn_RW; /* 0x510 */
444 u64 tlb_rpn_RW; /* 0x518 */
445 u8 pad_0x520_0x540[0x20]; /* 0x520 */
446 u64 tlb_invalidate_entry_W; /* 0x540 */
447 u64 tlb_invalidate_all_W; /* 0x548 */
448 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
449
450 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
451 u64 smm_hid; /* 0x580 */
452#define PAGE_SIZE_MASK 0xf000000000000000ull
453#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
454 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
455
456 /* MFC Status/Control Area */
457 u64 mfc_accr_RW; /* 0x600 */
458#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
459#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
460#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
461#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
462 u8 pad_0x608_0x610[0x8]; /* 0x608 */
463 u64 mfc_dsisr_RW; /* 0x610 */
464#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
465#define MFC_DSISR_ACCESS_DENIED (1 << 27)
466#define MFC_DSISR_ATOMIC (1 << 26)
467#define MFC_DSISR_ACCESS_PUT (1 << 25)
468#define MFC_DSISR_ADDR_MATCH (1 << 22)
469#define MFC_DSISR_LS (1 << 17)
470#define MFC_DSISR_L (1 << 16)
471#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
472 u8 pad_0x618_0x620[0x8]; /* 0x618 */
473 u64 mfc_dar_RW; /* 0x620 */
474 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
475
476 /* Replacement Management Table (RMT) Area */
477 u64 rmt_index_RW; /* 0x700 */
478 u8 pad_0x708_0x710[0x8]; /* 0x708 */
479 u64 rmt_data1_RW; /* 0x710 */
480 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
481
482 /* Control/Configuration Registers */
483 u64 mfc_dsir_R; /* 0x800 */
484#define MFC_DSIR_Q (1 << 31)
485#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
486 u64 mfc_lsacr_RW; /* 0x808 */
487#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
488#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
489 u64 mfc_lscrr_R; /* 0x810 */
490#define MFC_LSCRR_Q (1 << 31)
491#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
492#define MFC_LSCRR_QI_SHIFT 32
493#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
494 u8 pad_0x818_0x820[0x8]; /* 0x818 */
495 u64 mfc_tclass_id_RW; /* 0x820 */
496#define MFC_TCLASS_ID_ENABLE (1L << 0L)
497#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
498#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
499#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
500#define MFC_TCLASS_QUOTA_2_SHIFT 8L
501#define MFC_TCLASS_QUOTA_1_SHIFT 16L
502#define MFC_TCLASS_QUOTA_0_SHIFT 24L
503#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
504#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
505#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
506 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
507
508 /* Real Mode Support Registers */
509 u64 mfc_rm_boundary; /* 0x900 */
510 u8 pad_0x908_0x938[0x30]; /* 0x908 */
511 u64 smf_dma_signal_sel; /* 0x938 */
512#define mfc_dma1_mask_lsb 41
513#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
514#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
515#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
516#define mfc_dma2_mask_lsb 43
517#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
518#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
519#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
520 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
521 u64 smm_signal_sel; /* 0xa38 */
522#define smm_sig_mask_lsb 12
523#define smm_sig_shift (63 - smm_sig_mask_lsb)
524#define smm_sig_mask (0x3LL << smm_sig_shift)
525#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
526#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
527 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
528
529 /* DMA Command Error Area */
530 u64 mfc_cer_R; /* 0xc00 */
531#define MFC_CER_Q (1 << 31)
532#define MFC_CER_SPU_QUEUE MFC_CER_Q
533 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
534
535 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
536 /* DMA Command Error Area */
537 u64 spu_ecc_cntl_RW; /* 0x1000 */
538#define SPU_ECC_CNTL_E (1ull << 0ull)
539#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
540#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
541#define SPU_ECC_CNTL_S (1ull << 1ull)
542#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
543#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
544#define SPU_ECC_CNTL_B (1ull << 2ull)
545#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
546#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
547#define SPU_ECC_CNTL_I_SHIFT 3ull
548#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
549#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
550#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
551#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
552#define SPU_ECC_CNTL_D (1ull << 5ull)
553#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
554#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
555 u64 spu_ecc_stat_RW; /* 0x1008 */
556#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
557#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
558#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
559#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
560#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
561#define SPU_ECC_DATA_ERROR (1ull << 5ul)
562#define SPU_ECC_DMA_ERROR (1ull << 6ul)
563#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
564 u64 spu_ecc_addr_RW; /* 0x1010 */
565 u64 spu_err_mask_RW; /* 0x1018 */
566#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
567#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
568 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
569
570 /* SPU Debug-Trace Bus (DTB) Selection Registers */
571 u64 spu_trig0_sel; /* 0x1028 */
572 u64 spu_trig1_sel; /* 0x1030 */
573 u64 spu_trig2_sel; /* 0x1038 */
574 u64 spu_trig3_sel; /* 0x1040 */
575 u64 spu_trace_sel; /* 0x1048 */
576#define spu_trace_sel_mask 0x1f1fLL
577#define spu_trace_sel_bus0_bits 0x1000LL
578#define spu_trace_sel_bus2_bits 0x0010LL
579 u64 spu_event0_sel; /* 0x1050 */
580 u64 spu_event1_sel; /* 0x1058 */
581 u64 spu_event2_sel; /* 0x1060 */
582 u64 spu_event3_sel; /* 0x1068 */
583 u64 spu_trace_cntl; /* 0x1070 */
584} __attribute__ ((aligned(0x2000)));
585
586#endif /* __KERNEL__ */
587#endif