tjh.dev
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1/* vi: ts=8 sw=8
2 *
3 * TI 3410/5052 USB Serial Driver Header
4 *
5 * Copyright (C) 2004 Texas Instruments
6 *
7 * This driver is based on the Linux io_ti driver, which is
8 * Copyright (C) 2000-2002 Inside Out Networks
9 * Copyright (C) 2001-2002 Greg Kroah-Hartman
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * For questions or problems with this driver, contact Texas Instruments
17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or
18 * Peter Berger <pberger@brimson.com>.
19 */
20
21#ifndef _TI_3410_5052_H_
22#define _TI_3410_5052_H_
23
24/* Configuration ids */
25#define TI_BOOT_CONFIG 1
26#define TI_ACTIVE_CONFIG 2
27
28/* Vendor and product ids */
29#define TI_VENDOR_ID 0x0451
30#define TI_3410_PRODUCT_ID 0x3410
31#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */
32#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */
33#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */
34#define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */
35
36/* Commands */
37#define TI_GET_VERSION 0x01
38#define TI_GET_PORT_STATUS 0x02
39#define TI_GET_PORT_DEV_INFO 0x03
40#define TI_GET_CONFIG 0x04
41#define TI_SET_CONFIG 0x05
42#define TI_OPEN_PORT 0x06
43#define TI_CLOSE_PORT 0x07
44#define TI_START_PORT 0x08
45#define TI_STOP_PORT 0x09
46#define TI_TEST_PORT 0x0A
47#define TI_PURGE_PORT 0x0B
48#define TI_RESET_EXT_DEVICE 0x0C
49#define TI_WRITE_DATA 0x80
50#define TI_READ_DATA 0x81
51#define TI_REQ_TYPE_CLASS 0x82
52
53/* Module identifiers */
54#define TI_I2C_PORT 0x01
55#define TI_IEEE1284_PORT 0x02
56#define TI_UART1_PORT 0x03
57#define TI_UART2_PORT 0x04
58#define TI_RAM_PORT 0x05
59
60/* Modem status */
61#define TI_MSR_DELTA_CTS 0x01
62#define TI_MSR_DELTA_DSR 0x02
63#define TI_MSR_DELTA_RI 0x04
64#define TI_MSR_DELTA_CD 0x08
65#define TI_MSR_CTS 0x10
66#define TI_MSR_DSR 0x20
67#define TI_MSR_RI 0x40
68#define TI_MSR_CD 0x80
69#define TI_MSR_DELTA_MASK 0x0F
70#define TI_MSR_MASK 0xF0
71
72/* Line status */
73#define TI_LSR_OVERRUN_ERROR 0x01
74#define TI_LSR_PARITY_ERROR 0x02
75#define TI_LSR_FRAMING_ERROR 0x04
76#define TI_LSR_BREAK 0x08
77#define TI_LSR_ERROR 0x0F
78#define TI_LSR_RX_FULL 0x10
79#define TI_LSR_TX_EMPTY 0x20
80
81/* Line control */
82#define TI_LCR_BREAK 0x40
83
84/* Modem control */
85#define TI_MCR_LOOP 0x04
86#define TI_MCR_DTR 0x10
87#define TI_MCR_RTS 0x20
88
89/* Mask settings */
90#define TI_UART_ENABLE_RTS_IN 0x0001
91#define TI_UART_DISABLE_RTS 0x0002
92#define TI_UART_ENABLE_PARITY_CHECKING 0x0008
93#define TI_UART_ENABLE_DSR_OUT 0x0010
94#define TI_UART_ENABLE_CTS_OUT 0x0020
95#define TI_UART_ENABLE_X_OUT 0x0040
96#define TI_UART_ENABLE_XA_OUT 0x0080
97#define TI_UART_ENABLE_X_IN 0x0100
98#define TI_UART_ENABLE_DTR_IN 0x0800
99#define TI_UART_DISABLE_DTR 0x1000
100#define TI_UART_ENABLE_MS_INTS 0x2000
101#define TI_UART_ENABLE_AUTO_START_DMA 0x4000
102
103/* Parity */
104#define TI_UART_NO_PARITY 0x00
105#define TI_UART_ODD_PARITY 0x01
106#define TI_UART_EVEN_PARITY 0x02
107#define TI_UART_MARK_PARITY 0x03
108#define TI_UART_SPACE_PARITY 0x04
109
110/* Stop bits */
111#define TI_UART_1_STOP_BITS 0x00
112#define TI_UART_1_5_STOP_BITS 0x01
113#define TI_UART_2_STOP_BITS 0x02
114
115/* Bits per character */
116#define TI_UART_5_DATA_BITS 0x00
117#define TI_UART_6_DATA_BITS 0x01
118#define TI_UART_7_DATA_BITS 0x02
119#define TI_UART_8_DATA_BITS 0x03
120
121/* 232/485 modes */
122#define TI_UART_232 0x00
123#define TI_UART_485_RECEIVER_DISABLED 0x01
124#define TI_UART_485_RECEIVER_ENABLED 0x02
125
126/* Pipe transfer mode and timeout */
127#define TI_PIPE_MODE_CONTINOUS 0x01
128#define TI_PIPE_MODE_MASK 0x03
129#define TI_PIPE_TIMEOUT_MASK 0x7C
130#define TI_PIPE_TIMEOUT_ENABLE 0x80
131
132/* Config struct */
133struct ti_uart_config {
134 __u16 wBaudRate;
135 __u16 wFlags;
136 __u8 bDataBits;
137 __u8 bParity;
138 __u8 bStopBits;
139 char cXon;
140 char cXoff;
141 __u8 bUartMode;
142} __attribute__((packed));
143
144/* Get port status */
145struct ti_port_status {
146 __u8 bCmdCode;
147 __u8 bModuleId;
148 __u8 bErrorCode;
149 __u8 bMSR;
150 __u8 bLSR;
151} __attribute__((packed));
152
153/* Purge modes */
154#define TI_PURGE_OUTPUT 0x00
155#define TI_PURGE_INPUT 0x80
156
157/* Read/Write data */
158#define TI_RW_DATA_ADDR_SFR 0x10
159#define TI_RW_DATA_ADDR_IDATA 0x20
160#define TI_RW_DATA_ADDR_XDATA 0x30
161#define TI_RW_DATA_ADDR_CODE 0x40
162#define TI_RW_DATA_ADDR_GPIO 0x50
163#define TI_RW_DATA_ADDR_I2C 0x60
164#define TI_RW_DATA_ADDR_FLASH 0x70
165#define TI_RW_DATA_ADDR_DSP 0x80
166
167#define TI_RW_DATA_UNSPECIFIED 0x00
168#define TI_RW_DATA_BYTE 0x01
169#define TI_RW_DATA_WORD 0x02
170#define TI_RW_DATA_DOUBLE_WORD 0x04
171
172struct ti_write_data_bytes {
173 __u8 bAddrType;
174 __u8 bDataType;
175 __u8 bDataCounter;
176 __be16 wBaseAddrHi;
177 __be16 wBaseAddrLo;
178 __u8 bData[0];
179} __attribute__((packed));
180
181struct ti_read_data_request {
182 __u8 bAddrType;
183 __u8 bDataType;
184 __u8 bDataCounter;
185 __be16 wBaseAddrHi;
186 __be16 wBaseAddrLo;
187} __attribute__((packed));
188
189struct ti_read_data_bytes {
190 __u8 bCmdCode;
191 __u8 bModuleId;
192 __u8 bErrorCode;
193 __u8 bData[0];
194} __attribute__((packed));
195
196/* Interrupt struct */
197struct ti_interrupt {
198 __u8 bICode;
199 __u8 bIInfo;
200} __attribute__((packed));
201
202/* Interrupt codes */
203#define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
204#define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
205#define TI_CODE_HARDWARE_ERROR 0xFF
206#define TI_CODE_DATA_ERROR 0x03
207#define TI_CODE_MODEM_STATUS 0x04
208
209/* Download firmware max packet size */
210#define TI_DOWNLOAD_MAX_PACKET_SIZE 64
211
212/* Firmware image header */
213struct ti_firmware_header {
214 __le16 wLength;
215 __u8 bCheckSum;
216} __attribute__((packed));
217
218/* UART addresses */
219#define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */
220#define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */
221#define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */
222#define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */
223
224#endif /* _TI_3410_5052_H_ */