tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com>
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10
11#ifdef __KERNEL__
12#ifndef __ASM_IBM403_H__
13#define __ASM_IBM403_H__
14
15#include <linux/config.h>
16
17#if defined(CONFIG_403GCX)
18
19#define DCRN_BE_BASE 0x090
20#define DCRN_DMA0_BASE 0x0C0
21#define DCRN_DMA1_BASE 0x0C8
22#define DCRN_DMA2_BASE 0x0D0
23#define DCRN_DMA3_BASE 0x0D8
24#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
25#define DCRN_DMASR_BASE 0x0E0
26
27#define DCRN_EXIER_BASE 0x042
28#define DCRN_EXISR_BASE 0x040
29#define DCRN_IOCR_BASE 0x0A0
30
31
32/* ------------------------------------------------------------------------- */
33#endif
34
35
36
37#ifdef DCRN_BE_BASE
38#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
39#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/
40#endif
41/* DCRN_BESR */
42#define BESR_DSES 0x80000000 /* Data-Side Error Status */
43#define BESR_DMES 0x40000000 /* DMA Error Status */
44#define BESR_RWS 0x20000000 /* Read/Write Status */
45#define BESR_ETMASK 0x1C000000 /* Error Type */
46#define ET_PROT 0
47#define ET_PARITY 1
48#define ET_NCFG 2
49#define ET_BUSERR 4
50#define ET_BUSTO 6
51
52#ifdef DCRN_CHCR_BASE
53#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
54#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
55#endif
56#define CHR1_CETE 0x00800000 /* CPU external timer enable */
57#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
58
59#ifdef DCRN_CHPSR_BASE
60#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
61#endif
62
63#ifdef DCRN_CIC_BASE
64#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
65#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
66#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
67#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
68#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
69#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
70#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
71#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
72#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
73#endif
74
75#ifdef DCRN_CPMFR_BASE
76#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
77#endif
78
79#ifndef CPM_AUD
80#define CPM_AUD 0x00000000
81#endif
82#ifndef CPM_BRG
83#define CPM_BRG 0x00000000
84#endif
85#ifndef CPM_CBS
86#define CPM_CBS 0x00000000
87#endif
88#ifndef CPM_CPU
89#define CPM_CPU 0x00000000
90#endif
91#ifndef CPM_DCP
92#define CPM_DCP 0x00000000
93#endif
94#ifndef CPM_DCRX
95#define CPM_DCRX 0x00000000
96#endif
97#ifndef CPM_DENC
98#define CPM_DENC 0x00000000
99#endif
100#ifndef CPM_DMA
101#define CPM_DMA 0x00000000
102#endif
103#ifndef CPM_DSCR
104#define CPM_DSCR 0x00000000
105#endif
106#ifndef CPM_EBC
107#define CPM_EBC 0x00000000
108#endif
109#ifndef CPM_EBIU
110#define CPM_EBIU 0x00000000
111#endif
112#ifndef CPM_EMAC_MM
113#define CPM_EMAC_MM 0x00000000
114#endif
115#ifndef CPM_EMAC_RM
116#define CPM_EMAC_RM 0x00000000
117#endif
118#ifndef CPM_EMAC_TM
119#define CPM_EMAC_TM 0x00000000
120#endif
121#ifndef CPM_GPIO0
122#define CPM_GPIO0 0x00000000
123#endif
124#ifndef CPM_GPT
125#define CPM_GPT 0x00000000
126#endif
127#ifndef CPM_I1284
128#define CPM_I1284 0x00000000
129#endif
130#ifndef CPM_IIC0
131#define CPM_IIC0 0x00000000
132#endif
133#ifndef CPM_IIC1
134#define CPM_IIC1 0x00000000
135#endif
136#ifndef CPM_MSI
137#define CPM_MSI 0x00000000
138#endif
139#ifndef CPM_PCI
140#define CPM_PCI 0x00000000
141#endif
142#ifndef CPM_PLB
143#define CPM_PLB 0x00000000
144#endif
145#ifndef CPM_SC0
146#define CPM_SC0 0x00000000
147#endif
148#ifndef CPM_SC1
149#define CPM_SC1 0x00000000
150#endif
151#ifndef CPM_SDRAM0
152#define CPM_SDRAM0 0x00000000
153#endif
154#ifndef CPM_SDRAM1
155#define CPM_SDRAM1 0x00000000
156#endif
157#ifndef CPM_TMRCLK
158#define CPM_TMRCLK 0x00000000
159#endif
160#ifndef CPM_UART0
161#define CPM_UART0 0x00000000
162#endif
163#ifndef CPM_UART1
164#define CPM_UART1 0x00000000
165#endif
166#ifndef CPM_UART2
167#define CPM_UART2 0x00000000
168#endif
169#ifndef CPM_UIC
170#define CPM_UIC 0x00000000
171#endif
172#ifndef CPM_VID2
173#define CPM_VID2 0x00000000
174#endif
175#ifndef CPM_XPT27
176#define CPM_XPT27 0x00000000
177#endif
178#ifndef CPM_XPT54
179#define CPM_XPT54 0x00000000
180#endif
181
182#ifdef DCRN_CPMSR_BASE
183#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
184#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
185#endif
186
187#ifdef DCRN_DCP0_BASE
188#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */
189#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */
190#endif
191
192#ifdef DCRN_DCRX_BASE
193#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
194#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
195#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
196#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
197#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
198#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
199#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
200#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
201#endif
202
203#ifdef DCRN_DMA0_BASE
204#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */
205#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
206#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */
207#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */
208#ifdef DCRNCAP_DMA_CC
209#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */
210#endif
211
212#ifdef DCRNCAP_DMA_SG
213#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */
214#endif
215#endif
216
217#ifdef DCRN_DMA1_BASE
218#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */
219#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */
220#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */
221#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */
222
223#ifdef DCRNCAP_DMA_CC
224#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */
225#endif
226#ifdef DCRNCAP_DMA_SG
227#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */
228#endif
229#endif
230
231#ifdef DCRN_DMA2_BASE
232#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
233#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
234#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
235#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
236#ifdef DCRNCAP_DMA_CC
237#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
238#endif
239#ifdef DCRNCAP_DMA_SG
240#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
241#endif
242#endif
243
244#ifdef DCRN_DMA3_BASE
245#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
246#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
247#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
248#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
249#ifdef DCRNCAP_DMA_CC
250#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
251#endif
252#ifdef DCRNCAP_DMA_SG
253#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
254#endif
255#endif
256
257#ifdef DCRN_DMASR_BASE
258#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
259#ifdef DCRNCAP_DMA_SG
260#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
261/* don't know if these two registers always exist if scatter/gather exists */
262#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
263#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
264#endif
265#endif
266
267#ifdef DCRN_EBC_BASE
268#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */
269#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */
270#endif
271
272#ifdef DCRN_EXIER_BASE
273#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
274#endif
275
276#ifdef DCRN_EBIMC_BASE
277#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
278#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
279#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
280#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
281#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
282#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
283#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
284#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
285#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */
286#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */
287#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */
288#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */
289#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */
290#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */
291#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */
292#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */
293#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */
294#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */
295#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */
296#endif
297
298#ifdef DCRN_EXISR_BASE
299#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
300#endif
301#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
302#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
303#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
304#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
305#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
306#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
307#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
308#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
309#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
310#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
311#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
312#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
313#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
314#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
315
316#ifdef DCRN_IOCR_BASE
317#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */
318#endif
319#define IOCR_E0TE 0x80000000
320#define IOCR_E0LP 0x40000000
321#define IOCR_E1TE 0x20000000
322#define IOCR_E1LP 0x10000000
323#define IOCR_E2TE 0x08000000
324#define IOCR_E2LP 0x04000000
325#define IOCR_E3TE 0x02000000
326#define IOCR_E3LP 0x01000000
327#define IOCR_E4TE 0x00800000
328#define IOCR_E4LP 0x00400000
329#define IOCR_EDT 0x00080000
330#define IOCR_SOR 0x00040000
331#define IOCR_EDO 0x00008000
332#define IOCR_2XC 0x00004000
333#define IOCR_ATC 0x00002000
334#define IOCR_SPD 0x00001000
335#define IOCR_BEM 0x00000800
336#define IOCR_PTD 0x00000400
337#define IOCR_ARE 0x00000080
338#define IOCR_DRC 0x00000020
339#define IOCR_RDM(x) (((x) & 0x3) << 3)
340#define IOCR_TCS 0x00000004
341#define IOCR_SCS 0x00000002
342#define IOCR_SPC 0x00000001
343
344#ifdef DCRN_MAL_BASE
345#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */
346#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */
347#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */
348#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
349#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
350#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
351#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
352#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */
353#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */
354#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */
355#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */
356#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */
357#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */
358#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */
359#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */
360#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */
361#endif
362/* DCRN_MALCR */
363#define MALCR_MMSR 0x80000000/* MAL Software reset */
364#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
365#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
366#define MALCR_PLBP_3 0x00C00000 /* highest */
367#define MALCR_GA 0x00200000 /* Guarded Active Bit */
368#define MALCR_OA 0x00100000 /* Ordered Active Bit */
369#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
370#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
371#define MALCR_PLBLT_2 0x00020000
372#define MALCR_PLBLT_3 0x00010000
373#define MALCR_PLBLT_4 0x00008000
374#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */
375#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
376#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
377#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
378#define MALCR_LEA 0x00000002 /* Locked Error Active */
379#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
380/* DCRN_MALESR */
381#define MALESR_EVB 0x80000000 /* Error Valid Bit */
382#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
383#define MALESR_DE 0x00100000 /* Descriptor Error */
384#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
385#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
386#define MALESR_OSE 0x00020000 /* OPB Slave Error */
387#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
388#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
389#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
390#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
391#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
392#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
393/* DCRN_MALIER */
394#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
395#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
396#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
397#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
398#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
399/* DCRN_MALTXEOBISR */
400#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
401#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
402
403#ifdef DCRN_OCM0_BASE
404#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
405#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
406#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
407#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
408#endif
409
410#ifdef DCRN_PLB0_BASE
411#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0)
412#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2)
413/* doesn't exist on stb03xxx? */
414#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3)
415#endif
416
417#ifdef DCRN_PLB1_BASE
418#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0)
419#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1)
420/* doesn't exist on stb03xxx? */
421#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2)
422#endif
423
424#ifdef DCRN_PLLMR_BASE
425#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
426#endif
427
428#ifdef DCRN_POB0_BASE
429#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
430#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2)
431#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
432#endif
433
434#ifdef DCRN_SCCR_BASE
435#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0)
436#endif
437
438#ifdef DCRN_SDRAM0_BASE
439#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */
440#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */
441#endif
442
443#ifdef DCRN_UIC0_BASE
444#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0)
445#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2)
446#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3)
447#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4)
448#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5)
449#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6)
450#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7)
451#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8)
452#endif
453
454#ifdef DCRN_UIC1_BASE
455#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0)
456#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1)
457#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2)
458#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3)
459#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4)
460#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5)
461#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6)
462#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7)
463#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8)
464#endif
465
466#ifdef DCRN_SDRAM0_BASE
467#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
468#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
469#endif
470
471#ifdef DCRN_OCM0_BASE
472#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
473#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
474#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
475#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
476#endif
477
478#endif /* __ASM_IBM403_H__ */
479#endif /* __KERNEL__ */