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1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/config.h>
21#include <linux/threads.h>
22#include <asm/percpu.h>
23#include <linux/cpumask.h>
24
25/* flag for disabling the tsc */
26extern int tsc_disable;
27
28struct desc_struct {
29 unsigned long a,b;
30};
31
32#define desc_empty(desc) \
33 (!((desc)->a | (desc)->b))
34
35#define desc_equal(desc1, desc2) \
36 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37/*
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
40 */
41#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
42
43/*
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
47 */
48
49struct cpuinfo_x86 {
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
52 __u8 x86_model;
53 __u8 x86_mask;
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
56 char hard_math;
57 char rfu;
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
63 call */
64 int x86_cache_alignment; /* In bytes */
65 char fdiv_bug;
66 char f00f_bug;
67 char coma_bug;
68 char pad0;
69 int x86_power;
70 unsigned long loops_per_jiffy;
71#ifdef CONFIG_SMP
72 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
73#endif
74 unsigned char x86_max_cores; /* cpuid returned max cores value */
75 unsigned char booted_cores; /* number of cores as seen by OS */
76 unsigned char apicid;
77} __attribute__((__aligned__(SMP_CACHE_BYTES)));
78
79#define X86_VENDOR_INTEL 0
80#define X86_VENDOR_CYRIX 1
81#define X86_VENDOR_AMD 2
82#define X86_VENDOR_UMC 3
83#define X86_VENDOR_NEXGEN 4
84#define X86_VENDOR_CENTAUR 5
85#define X86_VENDOR_RISE 6
86#define X86_VENDOR_TRANSMETA 7
87#define X86_VENDOR_NSC 8
88#define X86_VENDOR_NUM 9
89#define X86_VENDOR_UNKNOWN 0xff
90
91/*
92 * capabilities of CPUs
93 */
94
95extern struct cpuinfo_x86 boot_cpu_data;
96extern struct cpuinfo_x86 new_cpu_data;
97extern struct tss_struct doublefault_tss;
98DECLARE_PER_CPU(struct tss_struct, init_tss);
99
100#ifdef CONFIG_SMP
101extern struct cpuinfo_x86 cpu_data[];
102#define current_cpu_data cpu_data[smp_processor_id()]
103#else
104#define cpu_data (&boot_cpu_data)
105#define current_cpu_data boot_cpu_data
106#endif
107
108extern int phys_proc_id[NR_CPUS];
109extern int cpu_core_id[NR_CPUS];
110extern int cpu_llc_id[NR_CPUS];
111extern char ignore_fpu_irq;
112
113extern void identify_cpu(struct cpuinfo_x86 *);
114extern void print_cpu_info(struct cpuinfo_x86 *);
115extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
116
117#ifdef CONFIG_X86_HT
118extern void detect_ht(struct cpuinfo_x86 *c);
119#else
120static inline void detect_ht(struct cpuinfo_x86 *c) {}
121#endif
122
123/*
124 * EFLAGS bits
125 */
126#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
127#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
128#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
129#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
130#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
131#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
132#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
133#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
134#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
135#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
136#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
137#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
138#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
139#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
140#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
141#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
142#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
143
144/*
145 * Generic CPUID function
146 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
147 * resulting in stale register contents being returned.
148 */
149static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
150{
151 __asm__("cpuid"
152 : "=a" (*eax),
153 "=b" (*ebx),
154 "=c" (*ecx),
155 "=d" (*edx)
156 : "0" (op), "c"(0));
157}
158
159/* Some CPUID calls want 'count' to be placed in ecx */
160static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
161 int *edx)
162{
163 __asm__("cpuid"
164 : "=a" (*eax),
165 "=b" (*ebx),
166 "=c" (*ecx),
167 "=d" (*edx)
168 : "0" (op), "c" (count));
169}
170
171/*
172 * CPUID functions returning a single datum
173 */
174static inline unsigned int cpuid_eax(unsigned int op)
175{
176 unsigned int eax;
177
178 __asm__("cpuid"
179 : "=a" (eax)
180 : "0" (op)
181 : "bx", "cx", "dx");
182 return eax;
183}
184static inline unsigned int cpuid_ebx(unsigned int op)
185{
186 unsigned int eax, ebx;
187
188 __asm__("cpuid"
189 : "=a" (eax), "=b" (ebx)
190 : "0" (op)
191 : "cx", "dx" );
192 return ebx;
193}
194static inline unsigned int cpuid_ecx(unsigned int op)
195{
196 unsigned int eax, ecx;
197
198 __asm__("cpuid"
199 : "=a" (eax), "=c" (ecx)
200 : "0" (op)
201 : "bx", "dx" );
202 return ecx;
203}
204static inline unsigned int cpuid_edx(unsigned int op)
205{
206 unsigned int eax, edx;
207
208 __asm__("cpuid"
209 : "=a" (eax), "=d" (edx)
210 : "0" (op)
211 : "bx", "cx");
212 return edx;
213}
214
215#define load_cr3(pgdir) write_cr3(__pa(pgdir))
216
217/*
218 * Intel CPU features in CR4
219 */
220#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
221#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
222#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
223#define X86_CR4_DE 0x0008 /* enable debugging extensions */
224#define X86_CR4_PSE 0x0010 /* enable page size extensions */
225#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
226#define X86_CR4_MCE 0x0040 /* Machine check enable */
227#define X86_CR4_PGE 0x0080 /* enable global pages */
228#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
229#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
230#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
231
232/*
233 * Save the cr4 feature set we're using (ie
234 * Pentium 4MB enable and PPro Global page
235 * enable), so that any CPU's that boot up
236 * after us can get the correct flags.
237 */
238extern unsigned long mmu_cr4_features;
239
240static inline void set_in_cr4 (unsigned long mask)
241{
242 unsigned cr4;
243 mmu_cr4_features |= mask;
244 cr4 = read_cr4();
245 cr4 |= mask;
246 write_cr4(cr4);
247}
248
249static inline void clear_in_cr4 (unsigned long mask)
250{
251 unsigned cr4;
252 mmu_cr4_features &= ~mask;
253 cr4 = read_cr4();
254 cr4 &= ~mask;
255 write_cr4(cr4);
256}
257
258/*
259 * NSC/Cyrix CPU configuration register indexes
260 */
261
262#define CX86_PCR0 0x20
263#define CX86_GCR 0xb8
264#define CX86_CCR0 0xc0
265#define CX86_CCR1 0xc1
266#define CX86_CCR2 0xc2
267#define CX86_CCR3 0xc3
268#define CX86_CCR4 0xe8
269#define CX86_CCR5 0xe9
270#define CX86_CCR6 0xea
271#define CX86_CCR7 0xeb
272#define CX86_PCR1 0xf0
273#define CX86_DIR0 0xfe
274#define CX86_DIR1 0xff
275#define CX86_ARR_BASE 0xc4
276#define CX86_RCR_BASE 0xdc
277
278/*
279 * NSC/Cyrix CPU indexed register access macros
280 */
281
282#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
283
284#define setCx86(reg, data) do { \
285 outb((reg), 0x22); \
286 outb((data), 0x23); \
287} while (0)
288
289/* Stop speculative execution */
290static inline void sync_core(void)
291{
292 int tmp;
293 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
294}
295
296static inline void __monitor(const void *eax, unsigned long ecx,
297 unsigned long edx)
298{
299 /* "monitor %eax,%ecx,%edx;" */
300 asm volatile(
301 ".byte 0x0f,0x01,0xc8;"
302 : :"a" (eax), "c" (ecx), "d"(edx));
303}
304
305static inline void __mwait(unsigned long eax, unsigned long ecx)
306{
307 /* "mwait %eax,%ecx;" */
308 asm volatile(
309 ".byte 0x0f,0x01,0xc9;"
310 : :"a" (eax), "c" (ecx));
311}
312
313/* from system description table in BIOS. Mostly for MCA use, but
314others may find it useful. */
315extern unsigned int machine_id;
316extern unsigned int machine_submodel_id;
317extern unsigned int BIOS_revision;
318extern unsigned int mca_pentium_flag;
319
320/* Boot loader type from the setup header */
321extern int bootloader_type;
322
323/*
324 * User space process size: 3GB (default).
325 */
326#define TASK_SIZE (PAGE_OFFSET)
327
328/* This decides where the kernel will search for a free chunk of vm
329 * space during mmap's.
330 */
331#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
332
333#define HAVE_ARCH_PICK_MMAP_LAYOUT
334
335/*
336 * Size of io_bitmap.
337 */
338#define IO_BITMAP_BITS 65536
339#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
340#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
341#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
342#define INVALID_IO_BITMAP_OFFSET 0x8000
343#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
344
345struct i387_fsave_struct {
346 long cwd;
347 long swd;
348 long twd;
349 long fip;
350 long fcs;
351 long foo;
352 long fos;
353 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
354 long status; /* software status information */
355};
356
357struct i387_fxsave_struct {
358 unsigned short cwd;
359 unsigned short swd;
360 unsigned short twd;
361 unsigned short fop;
362 long fip;
363 long fcs;
364 long foo;
365 long fos;
366 long mxcsr;
367 long mxcsr_mask;
368 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
369 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
370 long padding[56];
371} __attribute__ ((aligned (16)));
372
373struct i387_soft_struct {
374 long cwd;
375 long swd;
376 long twd;
377 long fip;
378 long fcs;
379 long foo;
380 long fos;
381 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
382 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
383 struct info *info;
384 unsigned long entry_eip;
385};
386
387union i387_union {
388 struct i387_fsave_struct fsave;
389 struct i387_fxsave_struct fxsave;
390 struct i387_soft_struct soft;
391};
392
393typedef struct {
394 unsigned long seg;
395} mm_segment_t;
396
397struct thread_struct;
398
399struct tss_struct {
400 unsigned short back_link,__blh;
401 unsigned long esp0;
402 unsigned short ss0,__ss0h;
403 unsigned long esp1;
404 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
405 unsigned long esp2;
406 unsigned short ss2,__ss2h;
407 unsigned long __cr3;
408 unsigned long eip;
409 unsigned long eflags;
410 unsigned long eax,ecx,edx,ebx;
411 unsigned long esp;
412 unsigned long ebp;
413 unsigned long esi;
414 unsigned long edi;
415 unsigned short es, __esh;
416 unsigned short cs, __csh;
417 unsigned short ss, __ssh;
418 unsigned short ds, __dsh;
419 unsigned short fs, __fsh;
420 unsigned short gs, __gsh;
421 unsigned short ldt, __ldth;
422 unsigned short trace, io_bitmap_base;
423 /*
424 * The extra 1 is there because the CPU will access an
425 * additional byte beyond the end of the IO permission
426 * bitmap. The extra byte must be all 1 bits, and must
427 * be within the limit.
428 */
429 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
430 /*
431 * Cache the current maximum and the last task that used the bitmap:
432 */
433 unsigned long io_bitmap_max;
434 struct thread_struct *io_bitmap_owner;
435 /*
436 * pads the TSS to be cacheline-aligned (size is 0x100)
437 */
438 unsigned long __cacheline_filler[35];
439 /*
440 * .. and then another 0x100 bytes for emergency kernel stack
441 */
442 unsigned long stack[64];
443} __attribute__((packed));
444
445#define ARCH_MIN_TASKALIGN 16
446
447struct thread_struct {
448/* cached TLS descriptors. */
449 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
450 unsigned long esp0;
451 unsigned long sysenter_cs;
452 unsigned long eip;
453 unsigned long esp;
454 unsigned long fs;
455 unsigned long gs;
456/* Hardware debugging registers */
457 unsigned long debugreg[8]; /* %%db0-7 debug registers */
458/* fault info */
459 unsigned long cr2, trap_no, error_code;
460/* floating point info */
461 union i387_union i387;
462/* virtual 86 mode info */
463 struct vm86_struct __user * vm86_info;
464 unsigned long screen_bitmap;
465 unsigned long v86flags, v86mask, saved_esp0;
466 unsigned int saved_fs, saved_gs;
467/* IO permissions */
468 unsigned long *io_bitmap_ptr;
469 unsigned long iopl;
470/* max allowed port in the bitmap, in bytes: */
471 unsigned long io_bitmap_max;
472};
473
474#define INIT_THREAD { \
475 .vm86_info = NULL, \
476 .sysenter_cs = __KERNEL_CS, \
477 .io_bitmap_ptr = NULL, \
478}
479
480/*
481 * Note that the .io_bitmap member must be extra-big. This is because
482 * the CPU will access an additional byte beyond the end of the IO
483 * permission bitmap. The extra byte must be all 1 bits, and must
484 * be within the limit.
485 */
486#define INIT_TSS { \
487 .esp0 = sizeof(init_stack) + (long)&init_stack, \
488 .ss0 = __KERNEL_DS, \
489 .ss1 = __KERNEL_CS, \
490 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
491 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
492}
493
494static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
495{
496 tss->esp0 = thread->esp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
499 tss->ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
501 }
502}
503
504#define start_thread(regs, new_eip, new_esp) do { \
505 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
506 set_fs(USER_DS); \
507 regs->xds = __USER_DS; \
508 regs->xes = __USER_DS; \
509 regs->xss = __USER_DS; \
510 regs->xcs = __USER_CS; \
511 regs->eip = new_eip; \
512 regs->esp = new_esp; \
513} while (0)
514
515/*
516 * These special macros can be used to get or set a debugging register
517 */
518#define get_debugreg(var, register) \
519 __asm__("movl %%db" #register ", %0" \
520 :"=r" (var))
521#define set_debugreg(value, register) \
522 __asm__("movl %0,%%db" #register \
523 : /* no output */ \
524 :"r" (value))
525
526/*
527 * Set IOPL bits in EFLAGS from given mask
528 */
529static inline void set_iopl_mask(unsigned mask)
530{
531 unsigned int reg;
532 __asm__ __volatile__ ("pushfl;"
533 "popl %0;"
534 "andl %1, %0;"
535 "orl %2, %0;"
536 "pushl %0;"
537 "popfl"
538 : "=&r" (reg)
539 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
540}
541
542/* Forward declaration, a strange C thing */
543struct task_struct;
544struct mm_struct;
545
546/* Free all resources held by a thread. */
547extern void release_thread(struct task_struct *);
548
549/* Prepare to copy thread state - unlazy all lazy status */
550extern void prepare_to_copy(struct task_struct *tsk);
551
552/*
553 * create a kernel thread without removing it from tasklists
554 */
555extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
556
557extern unsigned long thread_saved_pc(struct task_struct *tsk);
558void show_trace(struct task_struct *task, unsigned long *stack);
559
560unsigned long get_wchan(struct task_struct *p);
561
562#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
563#define KSTK_TOP(info) \
564({ \
565 unsigned long *__ptr = (unsigned long *)(info); \
566 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
567})
568
569/*
570 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
571 * This is necessary to guarantee that the entire "struct pt_regs"
572 * is accessable even if the CPU haven't stored the SS/ESP registers
573 * on the stack (interrupt gate does not save these registers
574 * when switching to the same priv ring).
575 * Therefore beware: accessing the xss/esp fields of the
576 * "struct pt_regs" is possible, but they may contain the
577 * completely wrong values.
578 */
579#define task_pt_regs(task) \
580({ \
581 struct pt_regs *__regs__; \
582 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
583 __regs__ - 1; \
584})
585
586#define KSTK_EIP(task) (task_pt_regs(task)->eip)
587#define KSTK_ESP(task) (task_pt_regs(task)->esp)
588
589
590struct microcode_header {
591 unsigned int hdrver;
592 unsigned int rev;
593 unsigned int date;
594 unsigned int sig;
595 unsigned int cksum;
596 unsigned int ldrver;
597 unsigned int pf;
598 unsigned int datasize;
599 unsigned int totalsize;
600 unsigned int reserved[3];
601};
602
603struct microcode {
604 struct microcode_header hdr;
605 unsigned int bits[0];
606};
607
608typedef struct microcode microcode_t;
609typedef struct microcode_header microcode_header_t;
610
611/* microcode format is extended from prescott processors */
612struct extended_signature {
613 unsigned int sig;
614 unsigned int pf;
615 unsigned int cksum;
616};
617
618struct extended_sigtable {
619 unsigned int count;
620 unsigned int cksum;
621 unsigned int reserved[3];
622 struct extended_signature sigs[0];
623};
624
625/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
626static inline void rep_nop(void)
627{
628 __asm__ __volatile__("rep;nop": : :"memory");
629}
630
631#define cpu_relax() rep_nop()
632
633/* generic versions from gas */
634#define GENERIC_NOP1 ".byte 0x90\n"
635#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
636#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
637#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
638#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
639#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
640#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
641#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
642
643/* Opteron nops */
644#define K8_NOP1 GENERIC_NOP1
645#define K8_NOP2 ".byte 0x66,0x90\n"
646#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
647#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
648#define K8_NOP5 K8_NOP3 K8_NOP2
649#define K8_NOP6 K8_NOP3 K8_NOP3
650#define K8_NOP7 K8_NOP4 K8_NOP3
651#define K8_NOP8 K8_NOP4 K8_NOP4
652
653/* K7 nops */
654/* uses eax dependencies (arbitary choice) */
655#define K7_NOP1 GENERIC_NOP1
656#define K7_NOP2 ".byte 0x8b,0xc0\n"
657#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
658#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
659#define K7_NOP5 K7_NOP4 ASM_NOP1
660#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
661#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
662#define K7_NOP8 K7_NOP7 ASM_NOP1
663
664#ifdef CONFIG_MK8
665#define ASM_NOP1 K8_NOP1
666#define ASM_NOP2 K8_NOP2
667#define ASM_NOP3 K8_NOP3
668#define ASM_NOP4 K8_NOP4
669#define ASM_NOP5 K8_NOP5
670#define ASM_NOP6 K8_NOP6
671#define ASM_NOP7 K8_NOP7
672#define ASM_NOP8 K8_NOP8
673#elif defined(CONFIG_MK7)
674#define ASM_NOP1 K7_NOP1
675#define ASM_NOP2 K7_NOP2
676#define ASM_NOP3 K7_NOP3
677#define ASM_NOP4 K7_NOP4
678#define ASM_NOP5 K7_NOP5
679#define ASM_NOP6 K7_NOP6
680#define ASM_NOP7 K7_NOP7
681#define ASM_NOP8 K7_NOP8
682#else
683#define ASM_NOP1 GENERIC_NOP1
684#define ASM_NOP2 GENERIC_NOP2
685#define ASM_NOP3 GENERIC_NOP3
686#define ASM_NOP4 GENERIC_NOP4
687#define ASM_NOP5 GENERIC_NOP5
688#define ASM_NOP6 GENERIC_NOP6
689#define ASM_NOP7 GENERIC_NOP7
690#define ASM_NOP8 GENERIC_NOP8
691#endif
692
693#define ASM_NOP_MAX 8
694
695/* Prefetch instructions for Pentium III and AMD Athlon */
696/* It's not worth to care about 3dnow! prefetches for the K6
697 because they are microcoded there and very slow.
698 However we don't do prefetches for pre XP Athlons currently
699 That should be fixed. */
700#define ARCH_HAS_PREFETCH
701static inline void prefetch(const void *x)
702{
703 alternative_input(ASM_NOP4,
704 "prefetchnta (%1)",
705 X86_FEATURE_XMM,
706 "r" (x));
707}
708
709#define ARCH_HAS_PREFETCH
710#define ARCH_HAS_PREFETCHW
711#define ARCH_HAS_SPINLOCK_PREFETCH
712
713/* 3dnow! prefetch to get an exclusive cache line. Useful for
714 spinlocks to avoid one state transition in the cache coherency protocol. */
715static inline void prefetchw(const void *x)
716{
717 alternative_input(ASM_NOP4,
718 "prefetchw (%1)",
719 X86_FEATURE_3DNOW,
720 "r" (x));
721}
722#define spin_lock_prefetch(x) prefetchw(x)
723
724extern void select_idle_routine(const struct cpuinfo_x86 *c);
725
726#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
727
728extern unsigned long boot_option_idle_override;
729extern void enable_sep_cpu(void);
730extern int sysenter_setup(void);
731
732#ifdef CONFIG_MTRR
733extern void mtrr_ap_init(void);
734extern void mtrr_bp_init(void);
735#else
736#define mtrr_ap_init() do {} while (0)
737#define mtrr_bp_init() do {} while (0)
738#endif
739
740#ifdef CONFIG_X86_MCE
741extern void mcheck_init(struct cpuinfo_x86 *c);
742#else
743#define mcheck_init(c) do {} while(0)
744#endif
745
746#endif /* __ASM_I386_PROCESSOR_H */