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kernel / drivers / video / nvidia / nv_hw.c
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1 /***************************************************************************\ 2|* *| 3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| 4|* *| 5|* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6|* international laws. Users and possessors of this source code are *| 7|* hereby granted a nonexclusive, royalty-free copyright license to *| 8|* use this code in individual and commercial software. *| 9|* *| 10|* Any use of this source code must include, in the user documenta- *| 11|* tion and internal comments to the code, notices to the end user *| 12|* as follows: *| 13|* *| 14|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| 15|* *| 16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27|* *| 28|* U.S. Government End Users. This source code is a "commercial *| 29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30|* consisting of "commercial computer software" and "commercial *| 31|* computer software documentation," as such terms are used in *| 32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33|* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35|* all U.S. Government End Users acquire the source code with only *| 36|* those rights set forth herein. *| 37|* *| 38 \***************************************************************************/ 39 40/* 41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ 42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing 43 * where the source code is provided "as is" without warranty of any kind. 44 * The only usage restriction is for the copyright notices to be retained 45 * whenever code is used. 46 * 47 * Antonino Daplas <adaplas@pol.net> 2005-03-11 48 */ 49 50/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */ 51 52#include <linux/pci.h> 53#include "nv_type.h" 54#include "nv_local.h" 55#include "nv_proto.h" 56 57void NVLockUnlock(struct nvidia_par *par, int Lock) 58{ 59 u8 cr11; 60 61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); 62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); 63 64 VGA_WR08(par->PCIO, 0x3D4, 0x11); 65 cr11 = VGA_RD08(par->PCIO, 0x3D5); 66 if (Lock) 67 cr11 |= 0x80; 68 else 69 cr11 &= ~0x80; 70 VGA_WR08(par->PCIO, 0x3D5, cr11); 71} 72 73int NVShowHideCursor(struct nvidia_par *par, int ShowHide) 74{ 75 int cur = par->CurrentState->cursor1; 76 77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | 78 (ShowHide & 0x01); 79 VGA_WR08(par->PCIO, 0x3D4, 0x31); 80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1); 81 82 if (par->Architecture == NV_ARCH_40) 83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300)); 84 85 return (cur & 0x01); 86} 87 88/****************************************************************************\ 89* * 90* The video arbitration routines calculate some "magic" numbers. Fixes * 91* the snow seen when accessing the framebuffer without it. * 92* It just works (I hope). * 93* * 94\****************************************************************************/ 95 96typedef struct { 97 int graphics_lwm; 98 int video_lwm; 99 int graphics_burst_size; 100 int video_burst_size; 101 int valid; 102} nv4_fifo_info; 103 104typedef struct { 105 int pclk_khz; 106 int mclk_khz; 107 int nvclk_khz; 108 char mem_page_miss; 109 char mem_latency; 110 int memory_width; 111 char enable_video; 112 char gr_during_vid; 113 char pix_bpp; 114 char mem_aligned; 115 char enable_mp; 116} nv4_sim_state; 117 118typedef struct { 119 int graphics_lwm; 120 int video_lwm; 121 int graphics_burst_size; 122 int video_burst_size; 123 int valid; 124} nv10_fifo_info; 125 126typedef struct { 127 int pclk_khz; 128 int mclk_khz; 129 int nvclk_khz; 130 char mem_page_miss; 131 char mem_latency; 132 int memory_type; 133 int memory_width; 134 char enable_video; 135 char gr_during_vid; 136 char pix_bpp; 137 char mem_aligned; 138 char enable_mp; 139} nv10_sim_state; 140 141static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk, 142 unsigned int *NVClk) 143{ 144 unsigned int pll, N, M, MB, NB, P; 145 146 if (par->Architecture >= NV_ARCH_40) { 147 pll = NV_RD32(par->PMC, 0x4020); 148 P = (pll >> 16) & 0x03; 149 pll = NV_RD32(par->PMC, 0x4024); 150 M = pll & 0xFF; 151 N = (pll >> 8) & 0xFF; 152 MB = (pll >> 16) & 0xFF; 153 NB = (pll >> 24) & 0xFF; 154 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 155 156 pll = NV_RD32(par->PMC, 0x4000); 157 P = (pll >> 16) & 0x03; 158 pll = NV_RD32(par->PMC, 0x4004); 159 M = pll & 0xFF; 160 N = (pll >> 8) & 0xFF; 161 MB = (pll >> 16) & 0xFF; 162 NB = (pll >> 24) & 0xFF; 163 164 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 165 } else if (par->twoStagePLL) { 166 pll = NV_RD32(par->PRAMDAC0, 0x0504); 167 M = pll & 0xFF; 168 N = (pll >> 8) & 0xFF; 169 P = (pll >> 16) & 0x0F; 170 pll = NV_RD32(par->PRAMDAC0, 0x0574); 171 if (pll & 0x80000000) { 172 MB = pll & 0xFF; 173 NB = (pll >> 8) & 0xFF; 174 } else { 175 MB = 1; 176 NB = 1; 177 } 178 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 179 180 pll = NV_RD32(par->PRAMDAC0, 0x0500); 181 M = pll & 0xFF; 182 N = (pll >> 8) & 0xFF; 183 P = (pll >> 16) & 0x0F; 184 pll = NV_RD32(par->PRAMDAC0, 0x0570); 185 if (pll & 0x80000000) { 186 MB = pll & 0xFF; 187 NB = (pll >> 8) & 0xFF; 188 } else { 189 MB = 1; 190 NB = 1; 191 } 192 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 193 } else 194 if (((par->Chipset & 0x0ff0) == 0x0300) || 195 ((par->Chipset & 0x0ff0) == 0x0330)) { 196 pll = NV_RD32(par->PRAMDAC0, 0x0504); 197 M = pll & 0x0F; 198 N = (pll >> 8) & 0xFF; 199 P = (pll >> 16) & 0x07; 200 if (pll & 0x00000080) { 201 MB = (pll >> 4) & 0x07; 202 NB = (pll >> 19) & 0x1f; 203 } else { 204 MB = 1; 205 NB = 1; 206 } 207 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 208 209 pll = NV_RD32(par->PRAMDAC0, 0x0500); 210 M = pll & 0x0F; 211 N = (pll >> 8) & 0xFF; 212 P = (pll >> 16) & 0x07; 213 if (pll & 0x00000080) { 214 MB = (pll >> 4) & 0x07; 215 NB = (pll >> 19) & 0x1f; 216 } else { 217 MB = 1; 218 NB = 1; 219 } 220 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; 221 } else { 222 pll = NV_RD32(par->PRAMDAC0, 0x0504); 223 M = pll & 0xFF; 224 N = (pll >> 8) & 0xFF; 225 P = (pll >> 16) & 0x0F; 226 *MClk = (N * par->CrystalFreqKHz / M) >> P; 227 228 pll = NV_RD32(par->PRAMDAC0, 0x0500); 229 M = pll & 0xFF; 230 N = (pll >> 8) & 0xFF; 231 P = (pll >> 16) & 0x0F; 232 *NVClk = (N * par->CrystalFreqKHz / M) >> P; 233 } 234} 235 236static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb) 237{ 238 int data, pagemiss, cas, width, video_enable, bpp; 239 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 240 int found, mclk_extra, mclk_loop, cbs, m1, p1; 241 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 242 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; 243 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm; 244 245 fifo->valid = 1; 246 pclk_freq = arb->pclk_khz; 247 mclk_freq = arb->mclk_khz; 248 nvclk_freq = arb->nvclk_khz; 249 pagemiss = arb->mem_page_miss; 250 cas = arb->mem_latency; 251 width = arb->memory_width >> 6; 252 video_enable = arb->enable_video; 253 bpp = arb->pix_bpp; 254 mp_enable = arb->enable_mp; 255 clwm = 0; 256 vlwm = 0; 257 cbs = 128; 258 pclks = 2; 259 nvclks = 2; 260 nvclks += 2; 261 nvclks += 1; 262 mclks = 5; 263 mclks += 3; 264 mclks += 1; 265 mclks += cas; 266 mclks += 1; 267 mclks += 1; 268 mclks += 1; 269 mclks += 1; 270 mclk_extra = 3; 271 nvclks += 2; 272 nvclks += 1; 273 nvclks += 1; 274 nvclks += 1; 275 if (mp_enable) 276 mclks += 4; 277 nvclks += 0; 278 pclks += 0; 279 found = 0; 280 vbs = 0; 281 while (found != 1) { 282 fifo->valid = 1; 283 found = 1; 284 mclk_loop = mclks + mclk_extra; 285 us_m = mclk_loop * 1000 * 1000 / mclk_freq; 286 us_n = nvclks * 1000 * 1000 / nvclk_freq; 287 us_p = nvclks * 1000 * 1000 / pclk_freq; 288 if (video_enable) { 289 video_drain_rate = pclk_freq * 2; 290 crtc_drain_rate = pclk_freq * bpp / 8; 291 vpagemiss = 2; 292 vpagemiss += 1; 293 crtpagemiss = 2; 294 vpm_us = 295 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq; 296 if (nvclk_freq * 2 > mclk_freq * width) 297 video_fill_us = 298 cbs * 1000 * 1000 / 16 / nvclk_freq; 299 else 300 video_fill_us = 301 cbs * 1000 * 1000 / (8 * width) / 302 mclk_freq; 303 us_video = vpm_us + us_m + us_n + us_p + video_fill_us; 304 vlwm = us_video * video_drain_rate / (1000 * 1000); 305 vlwm++; 306 vbs = 128; 307 if (vlwm > 128) 308 vbs = 64; 309 if (vlwm > (256 - 64)) 310 vbs = 32; 311 if (nvclk_freq * 2 > mclk_freq * width) 312 video_fill_us = 313 vbs * 1000 * 1000 / 16 / nvclk_freq; 314 else 315 video_fill_us = 316 vbs * 1000 * 1000 / (8 * width) / 317 mclk_freq; 318 cpm_us = 319 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; 320 us_crt = 321 us_video + video_fill_us + cpm_us + us_m + us_n + 322 us_p; 323 clwm = us_crt * crtc_drain_rate / (1000 * 1000); 324 clwm++; 325 } else { 326 crtc_drain_rate = pclk_freq * bpp / 8; 327 crtpagemiss = 2; 328 crtpagemiss += 1; 329 cpm_us = 330 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; 331 us_crt = cpm_us + us_m + us_n + us_p; 332 clwm = us_crt * crtc_drain_rate / (1000 * 1000); 333 clwm++; 334 } 335 m1 = clwm + cbs - 512; 336 p1 = m1 * pclk_freq / mclk_freq; 337 p1 = p1 * bpp / 8; 338 if ((p1 < m1) && (m1 > 0)) { 339 fifo->valid = 0; 340 found = 0; 341 if (mclk_extra == 0) 342 found = 1; 343 mclk_extra--; 344 } else if (video_enable) { 345 if ((clwm > 511) || (vlwm > 255)) { 346 fifo->valid = 0; 347 found = 0; 348 if (mclk_extra == 0) 349 found = 1; 350 mclk_extra--; 351 } 352 } else { 353 if (clwm > 519) { 354 fifo->valid = 0; 355 found = 0; 356 if (mclk_extra == 0) 357 found = 1; 358 mclk_extra--; 359 } 360 } 361 if (clwm < 384) 362 clwm = 384; 363 if (vlwm < 128) 364 vlwm = 128; 365 data = (int)(clwm); 366 fifo->graphics_lwm = data; 367 fifo->graphics_burst_size = 128; 368 data = (int)((vlwm + 15)); 369 fifo->video_lwm = data; 370 fifo->video_burst_size = vbs; 371 } 372} 373 374static void nv4UpdateArbitrationSettings(unsigned VClk, 375 unsigned pixelDepth, 376 unsigned *burst, 377 unsigned *lwm, struct nvidia_par *par) 378{ 379 nv4_fifo_info fifo_data; 380 nv4_sim_state sim_data; 381 unsigned int MClk, NVClk, cfg1; 382 383 nvGetClocks(par, &MClk, &NVClk); 384 385 cfg1 = NV_RD32(par->PFB, 0x00000204); 386 sim_data.pix_bpp = (char)pixelDepth; 387 sim_data.enable_video = 0; 388 sim_data.enable_mp = 0; 389 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? 390 128 : 64; 391 sim_data.mem_latency = (char)cfg1 & 0x0F; 392 sim_data.mem_aligned = 1; 393 sim_data.mem_page_miss = 394 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); 395 sim_data.gr_during_vid = 0; 396 sim_data.pclk_khz = VClk; 397 sim_data.mclk_khz = MClk; 398 sim_data.nvclk_khz = NVClk; 399 nv4CalcArbitration(&fifo_data, &sim_data); 400 if (fifo_data.valid) { 401 int b = fifo_data.graphics_burst_size >> 4; 402 *burst = 0; 403 while (b >>= 1) 404 (*burst)++; 405 *lwm = fifo_data.graphics_lwm >> 3; 406 } 407} 408 409static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb) 410{ 411 int data, pagemiss, width, video_enable, bpp; 412 int nvclks, mclks, pclks, vpagemiss, crtpagemiss; 413 int nvclk_fill; 414 int found, mclk_extra, mclk_loop, cbs, m1; 415 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 416 int us_m, us_m_min, us_n, us_p, crtc_drain_rate; 417 int vus_m; 418 int vpm_us, us_video, cpm_us, us_crt, clwm; 419 int clwm_rnd_down; 420 int m2us, us_pipe_min, p1clk, p2; 421 int min_mclk_extra; 422 int us_min_mclk_extra; 423 424 fifo->valid = 1; 425 pclk_freq = arb->pclk_khz; /* freq in KHz */ 426 mclk_freq = arb->mclk_khz; 427 nvclk_freq = arb->nvclk_khz; 428 pagemiss = arb->mem_page_miss; 429 width = arb->memory_width / 64; 430 video_enable = arb->enable_video; 431 bpp = arb->pix_bpp; 432 mp_enable = arb->enable_mp; 433 clwm = 0; 434 435 cbs = 512; 436 437 pclks = 4; /* lwm detect. */ 438 439 nvclks = 3; /* lwm -> sync. */ 440 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ 441 /* 2 edge sync. may be very close to edge so just put one. */ 442 mclks = 1; 443 mclks += 1; /* arb_hp_req */ 444 mclks += 5; /* ap_hp_req tiling pipeline */ 445 446 mclks += 2; /* tc_req latency fifo */ 447 mclks += 2; /* fb_cas_n_ memory request to fbio block */ 448 mclks += 7; /* sm_d_rdv data returned from fbio block */ 449 450 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ 451 if (arb->memory_type == 0) 452 if (arb->memory_width == 64) /* 64 bit bus */ 453 mclks += 4; 454 else 455 mclks += 2; 456 else if (arb->memory_width == 64) /* 64 bit bus */ 457 mclks += 2; 458 else 459 mclks += 1; 460 461 if ((!video_enable) && (arb->memory_width == 128)) { 462 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ 463 min_mclk_extra = 17; 464 } else { 465 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ 466 /* mclk_extra = 4; *//* Margin of error */ 467 min_mclk_extra = 18; 468 } 469 470 /* 2 edge sync. may be very close to edge so just put one. */ 471 nvclks += 1; 472 nvclks += 1; /* fbi_d_rdv_n */ 473 nvclks += 1; /* Fbi_d_rdata */ 474 nvclks += 1; /* crtfifo load */ 475 476 if (mp_enable) 477 mclks += 4; /* Mp can get in with a burst of 8. */ 478 /* Extra clocks determined by heuristics */ 479 480 nvclks += 0; 481 pclks += 0; 482 found = 0; 483 while (found != 1) { 484 fifo->valid = 1; 485 found = 1; 486 mclk_loop = mclks + mclk_extra; 487 /* Mclk latency in us */ 488 us_m = mclk_loop * 1000 * 1000 / mclk_freq; 489 /* Minimum Mclk latency in us */ 490 us_m_min = mclks * 1000 * 1000 / mclk_freq; 491 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq; 492 /* nvclk latency in us */ 493 us_n = nvclks * 1000 * 1000 / nvclk_freq; 494 /* nvclk latency in us */ 495 us_p = pclks * 1000 * 1000 / pclk_freq; 496 us_pipe_min = us_m_min + us_n + us_p; 497 498 /* Mclk latency in us */ 499 vus_m = mclk_loop * 1000 * 1000 / mclk_freq; 500 501 if (video_enable) { 502 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */ 503 504 vpagemiss = 1; /* self generating page miss */ 505 vpagemiss += 1; /* One higher priority before */ 506 507 crtpagemiss = 2; /* self generating page miss */ 508 if (mp_enable) 509 crtpagemiss += 1; /* if MA0 conflict */ 510 511 vpm_us = 512 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq; 513 514 /* Video has separate read return path */ 515 us_video = vpm_us + vus_m; 516 517 cpm_us = 518 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; 519 /* Wait for video */ 520 us_crt = us_video 521 + cpm_us /* CRT Page miss */ 522 + us_m + us_n + us_p /* other latency */ 523 ; 524 525 clwm = us_crt * crtc_drain_rate / (1000 * 1000); 526 /* fixed point <= float_point - 1. Fixes that */ 527 clwm++; 528 } else { 529 /* bpp * pclk/8 */ 530 crtc_drain_rate = pclk_freq * bpp / 8; 531 532 crtpagemiss = 1; /* self generating page miss */ 533 crtpagemiss += 1; /* MA0 page miss */ 534 if (mp_enable) 535 crtpagemiss += 1; /* if MA0 conflict */ 536 cpm_us = 537 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; 538 us_crt = cpm_us + us_m + us_n + us_p; 539 clwm = us_crt * crtc_drain_rate / (1000 * 1000); 540 /* fixed point <= float_point - 1. Fixes that */ 541 clwm++; 542 543 /* Finally, a heuristic check when width == 64 bits */ 544 if (width == 1) { 545 nvclk_fill = nvclk_freq * 8; 546 if (crtc_drain_rate * 100 >= nvclk_fill * 102) 547 /*Large number to fail */ 548 clwm = 0xfff; 549 550 else if (crtc_drain_rate * 100 >= 551 nvclk_fill * 98) { 552 clwm = 1024; 553 cbs = 512; 554 } 555 } 556 } 557 558 /* 559 Overfill check: 560 */ 561 562 clwm_rnd_down = ((int)clwm / 8) * 8; 563 if (clwm_rnd_down < clwm) 564 clwm += 8; 565 566 m1 = clwm + cbs - 1024; /* Amount of overfill */ 567 m2us = us_pipe_min + us_min_mclk_extra; 568 569 /* pclk cycles to drain */ 570 p1clk = m2us * pclk_freq / (1000 * 1000); 571 p2 = p1clk * bpp / 8; /* bytes drained. */ 572 573 if ((p2 < m1) && (m1 > 0)) { 574 fifo->valid = 0; 575 found = 0; 576 if (min_mclk_extra == 0) { 577 if (cbs <= 32) { 578 /* Can't adjust anymore! */ 579 found = 1; 580 } else { 581 /* reduce the burst size */ 582 cbs = cbs / 2; 583 } 584 } else { 585 min_mclk_extra--; 586 } 587 } else { 588 if (clwm > 1023) { /* Have some margin */ 589 fifo->valid = 0; 590 found = 0; 591 if (min_mclk_extra == 0) 592 /* Can't adjust anymore! */ 593 found = 1; 594 else 595 min_mclk_extra--; 596 } 597 } 598 599 if (clwm < (1024 - cbs + 8)) 600 clwm = 1024 - cbs + 8; 601 data = (int)(clwm); 602 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", 603 clwm, data ); */ 604 fifo->graphics_lwm = data; 605 fifo->graphics_burst_size = cbs; 606 607 fifo->video_lwm = 1024; 608 fifo->video_burst_size = 512; 609 } 610} 611 612static void nv10UpdateArbitrationSettings(unsigned VClk, 613 unsigned pixelDepth, 614 unsigned *burst, 615 unsigned *lwm, 616 struct nvidia_par *par) 617{ 618 nv10_fifo_info fifo_data; 619 nv10_sim_state sim_data; 620 unsigned int MClk, NVClk, cfg1; 621 622 nvGetClocks(par, &MClk, &NVClk); 623 624 cfg1 = NV_RD32(par->PFB, 0x0204); 625 sim_data.pix_bpp = (char)pixelDepth; 626 sim_data.enable_video = 1; 627 sim_data.enable_mp = 0; 628 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; 629 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? 630 128 : 64; 631 sim_data.mem_latency = (char)cfg1 & 0x0F; 632 sim_data.mem_aligned = 1; 633 sim_data.mem_page_miss = 634 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); 635 sim_data.gr_during_vid = 0; 636 sim_data.pclk_khz = VClk; 637 sim_data.mclk_khz = MClk; 638 sim_data.nvclk_khz = NVClk; 639 nv10CalcArbitration(&fifo_data, &sim_data); 640 if (fifo_data.valid) { 641 int b = fifo_data.graphics_burst_size >> 4; 642 *burst = 0; 643 while (b >>= 1) 644 (*burst)++; 645 *lwm = fifo_data.graphics_lwm >> 3; 646 } 647} 648 649static void nv30UpdateArbitrationSettings ( 650 struct nvidia_par *par, 651 unsigned int *burst, 652 unsigned int *lwm 653) 654{ 655 unsigned int MClk, NVClk; 656 unsigned int fifo_size, burst_size, graphics_lwm; 657 658 fifo_size = 2048; 659 burst_size = 512; 660 graphics_lwm = fifo_size - burst_size; 661 662 nvGetClocks(par, &MClk, &NVClk); 663 664 *burst = 0; 665 burst_size >>= 5; 666 while(burst_size >>= 1) (*burst)++; 667 *lwm = graphics_lwm >> 3; 668} 669 670static void nForceUpdateArbitrationSettings(unsigned VClk, 671 unsigned pixelDepth, 672 unsigned *burst, 673 unsigned *lwm, 674 struct nvidia_par *par) 675{ 676 nv10_fifo_info fifo_data; 677 nv10_sim_state sim_data; 678 unsigned int M, N, P, pll, MClk, NVClk, memctrl; 679 struct pci_dev *dev; 680 681 if ((par->Chipset & 0x0FF0) == 0x01A0) { 682 unsigned int uMClkPostDiv; 683 dev = pci_find_slot(0, 3); 684 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 685 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 686 687 if (!uMClkPostDiv) 688 uMClkPostDiv = 4; 689 MClk = 400000 / uMClkPostDiv; 690 } else { 691 dev = pci_find_slot(0, 5); 692 pci_read_config_dword(dev, 0x4c, &MClk); 693 MClk /= 1000; 694 } 695 696 pll = NV_RD32(par->PRAMDAC0, 0x0500); 697 M = (pll >> 0) & 0xFF; 698 N = (pll >> 8) & 0xFF; 699 P = (pll >> 16) & 0x0F; 700 NVClk = (N * par->CrystalFreqKHz / M) >> P; 701 sim_data.pix_bpp = (char)pixelDepth; 702 sim_data.enable_video = 0; 703 sim_data.enable_mp = 0; 704 pci_find_slot(0, 1); 705 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 706 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 707 sim_data.memory_width = 64; 708 709 dev = pci_find_slot(0, 3); 710 pci_read_config_dword(dev, 0, &memctrl); 711 memctrl >>= 16; 712 713 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { 714 int dimm[3]; 715 716 pci_find_slot(0, 2); 717 pci_read_config_dword(dev, 0x40, &dimm[0]); 718 dimm[0] = (dimm[0] >> 8) & 0x4f; 719 pci_read_config_dword(dev, 0x44, &dimm[1]); 720 dimm[1] = (dimm[1] >> 8) & 0x4f; 721 pci_read_config_dword(dev, 0x48, &dimm[2]); 722 dimm[2] = (dimm[2] >> 8) & 0x4f; 723 724 if ((dimm[0] + dimm[1]) != dimm[2]) { 725 printk("nvidiafb: your nForce DIMMs are not arranged " 726 "in optimal banks!\n"); 727 } 728 } 729 730 sim_data.mem_latency = 3; 731 sim_data.mem_aligned = 1; 732 sim_data.mem_page_miss = 10; 733 sim_data.gr_during_vid = 0; 734 sim_data.pclk_khz = VClk; 735 sim_data.mclk_khz = MClk; 736 sim_data.nvclk_khz = NVClk; 737 nv10CalcArbitration(&fifo_data, &sim_data); 738 if (fifo_data.valid) { 739 int b = fifo_data.graphics_burst_size >> 4; 740 *burst = 0; 741 while (b >>= 1) 742 (*burst)++; 743 *lwm = fifo_data.graphics_lwm >> 3; 744 } 745} 746 747/****************************************************************************\ 748* * 749* RIVA Mode State Routines * 750* * 751\****************************************************************************/ 752 753/* 754 * Calculate the Video Clock parameters for the PLL. 755 */ 756static void CalcVClock(int clockIn, 757 int *clockOut, u32 * pllOut, struct nvidia_par *par) 758{ 759 unsigned lowM, highM; 760 unsigned DeltaNew, DeltaOld; 761 unsigned VClk, Freq; 762 unsigned M, N, P; 763 764 DeltaOld = 0xFFFFFFFF; 765 766 VClk = (unsigned)clockIn; 767 768 if (par->CrystalFreqKHz == 13500) { 769 lowM = 7; 770 highM = 13; 771 } else { 772 lowM = 8; 773 highM = 14; 774 } 775 776 for (P = 0; P <= 4; P++) { 777 Freq = VClk << P; 778 if ((Freq >= 128000) && (Freq <= 350000)) { 779 for (M = lowM; M <= highM; M++) { 780 N = ((VClk << P) * M) / par->CrystalFreqKHz; 781 if (N <= 255) { 782 Freq = 783 ((par->CrystalFreqKHz * N) / 784 M) >> P; 785 if (Freq > VClk) 786 DeltaNew = Freq - VClk; 787 else 788 DeltaNew = VClk - Freq; 789 if (DeltaNew < DeltaOld) { 790 *pllOut = 791 (P << 16) | (N << 8) | M; 792 *clockOut = Freq; 793 DeltaOld = DeltaNew; 794 } 795 } 796 } 797 } 798 } 799} 800 801static void CalcVClock2Stage(int clockIn, 802 int *clockOut, 803 u32 * pllOut, 804 u32 * pllBOut, struct nvidia_par *par) 805{ 806 unsigned DeltaNew, DeltaOld; 807 unsigned VClk, Freq; 808 unsigned M, N, P; 809 810 DeltaOld = 0xFFFFFFFF; 811 812 *pllBOut = 0x80000401; /* fixed at x4 for now */ 813 814 VClk = (unsigned)clockIn; 815 816 for (P = 0; P <= 6; P++) { 817 Freq = VClk << P; 818 if ((Freq >= 400000) && (Freq <= 1000000)) { 819 for (M = 1; M <= 13; M++) { 820 N = ((VClk << P) * M) / 821 (par->CrystalFreqKHz << 2); 822 if ((N >= 5) && (N <= 255)) { 823 Freq = 824 (((par->CrystalFreqKHz << 2) * N) / 825 M) >> P; 826 if (Freq > VClk) 827 DeltaNew = Freq - VClk; 828 else 829 DeltaNew = VClk - Freq; 830 if (DeltaNew < DeltaOld) { 831 *pllOut = 832 (P << 16) | (N << 8) | M; 833 *clockOut = Freq; 834 DeltaOld = DeltaNew; 835 } 836 } 837 } 838 } 839 } 840} 841 842/* 843 * Calculate extended mode parameters (SVGA) and save in a 844 * mode state structure. 845 */ 846void NVCalcStateExt(struct nvidia_par *par, 847 RIVA_HW_STATE * state, 848 int bpp, 849 int width, 850 int hDisplaySize, int height, int dotClock, int flags) 851{ 852 int pixelDepth, VClk = 0; 853 /* 854 * Save mode parameters. 855 */ 856 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ 857 state->width = width; 858 state->height = height; 859 /* 860 * Extended RIVA registers. 861 */ 862 pixelDepth = (bpp + 1) / 8; 863 if (par->twoStagePLL) 864 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, 865 par); 866 else 867 CalcVClock(dotClock, &VClk, &state->pll, par); 868 869 switch (par->Architecture) { 870 case NV_ARCH_04: 871 nv4UpdateArbitrationSettings(VClk, 872 pixelDepth * 8, 873 &(state->arbitration0), 874 &(state->arbitration1), par); 875 state->cursor0 = 0x00; 876 state->cursor1 = 0xbC; 877 if (flags & FB_VMODE_DOUBLE) 878 state->cursor1 |= 2; 879 state->cursor2 = 0x00000000; 880 state->pllsel = 0x10000700; 881 state->config = 0x00001114; 882 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 883 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 884 break; 885 case NV_ARCH_10: 886 case NV_ARCH_20: 887 case NV_ARCH_30: 888 default: 889 if (((par->Chipset & 0xffff) == 0x01A0) || 890 ((par->Chipset & 0xffff) == 0x01f0)) { 891 nForceUpdateArbitrationSettings(VClk, 892 pixelDepth * 8, 893 &(state->arbitration0), 894 &(state->arbitration1), 895 par); 896 } else if (par->Architecture < NV_ARCH_30) { 897 nv10UpdateArbitrationSettings(VClk, 898 pixelDepth * 8, 899 &(state->arbitration0), 900 &(state->arbitration1), 901 par); 902 } else { 903 nv30UpdateArbitrationSettings(par, 904 &(state->arbitration0), 905 &(state->arbitration1)); 906 } 907 908 state->cursor0 = 0x80 | (par->CursorStart >> 17); 909 state->cursor1 = (par->CursorStart >> 11) << 2; 910 state->cursor2 = par->CursorStart >> 24; 911 if (flags & FB_VMODE_DOUBLE) 912 state->cursor1 |= 2; 913 state->pllsel = 0x10000700; 914 state->config = NV_RD32(par->PFB, 0x00000200); 915 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 916 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 917 break; 918 } 919 920 if (bpp != 8) /* DirectColor */ 921 state->general |= 0x00000030; 922 923 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3; 924 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth; 925} 926 927void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) 928{ 929 int i; 930 931 NV_WR32(par->PMC, 0x0140, 0x00000000); 932 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); 933 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); 934 935 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008); 936 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003); 937 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000); 938 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF); 939 940 if (par->Architecture == NV_ARCH_04) { 941 NV_WR32(par->PFB, 0x0200, state->config); 942 } else if ((par->Architecture < NV_ARCH_40) || 943 (par->Chipset & 0xfff0) == 0x0040) { 944 for (i = 0; i < 8; i++) { 945 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); 946 NV_WR32(par->PFB, 0x0244 + (i * 0x10), 947 par->FbMapSize - 1); 948 } 949 } else { 950 int regions = 12; 951 952 if (((par->Chipset & 0xfff0) == 0x0090) || 953 ((par->Chipset & 0xfff0) == 0x01D0) || 954 ((par->Chipset & 0xfff0) == 0x0290)) 955 regions = 15; 956 for(i = 0; i < regions; i++) { 957 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0); 958 NV_WR32(par->PFB, 0x0604 + (i * 0x10), 959 par->FbMapSize - 1); 960 } 961 } 962 963 if (par->Architecture >= NV_ARCH_40) { 964 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010); 965 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202); 966 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011); 967 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204); 968 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012); 969 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206); 970 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013); 971 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208); 972 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014); 973 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A); 974 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015); 975 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C); 976 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016); 977 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E); 978 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017); 979 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210); 980 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000); 981 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1); 982 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002); 983 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062); 984 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000); 985 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200); 986 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200); 987 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000); 988 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000); 989 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043); 990 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000); 991 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000); 992 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000); 993 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000); 994 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000); 995 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044); 996 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000); 997 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000); 998 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000); 999 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000); 1000 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000); 1001 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019); 1002 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000); 1003 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000); 1004 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000); 1005 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000); 1006 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000); 1007 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C); 1008 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000); 1009 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000); 1010 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000); 1011 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000); 1012 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000); 1013 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F); 1014 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000); 1015 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200); 1016 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200); 1017 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000); 1018 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000); 1019 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A); 1020 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000); 1021 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000); 1022 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000); 1023 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000); 1024 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000); 1025 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077); 1026 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000); 1027 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200); 1028 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200); 1029 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000); 1030 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000); 1031 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002); 1032 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF); 1033 NV_WR32(par->PRAMIN, 0x084E * 4, 1034 par->FbUsableSize | 0x00000002); 1035 1036#ifdef __BIG_ENDIAN 1037 NV_WR32(par->PRAMIN, 0x080A * 4, 1038 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000); 1039 NV_WR32(par->PRAMIN, 0x0812 * 4, 1040 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000); 1041 NV_WR32(par->PRAMIN, 0x081A * 4, 1042 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000); 1043 NV_WR32(par->PRAMIN, 0x0822 * 4, 1044 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000); 1045 NV_WR32(par->PRAMIN, 0x082A * 4, 1046 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000); 1047 NV_WR32(par->PRAMIN, 0x0832 * 4, 1048 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000); 1049 NV_WR32(par->PRAMIN, 0x083A * 4, 1050 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000); 1051 NV_WR32(par->PRAMIN, 0x0842 * 4, 1052 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000); 1053 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000); 1054 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000); 1055#endif 1056 } else { 1057 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010); 1058 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201); 1059 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011); 1060 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202); 1061 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012); 1062 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203); 1063 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013); 1064 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204); 1065 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014); 1066 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205); 1067 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015); 1068 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206); 1069 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016); 1070 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207); 1071 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017); 1072 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208); 1073 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000); 1074 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1); 1075 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002); 1076 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002); 1077 if (par->Architecture >= NV_ARCH_10) 1078 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062); 1079 else 1080 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042); 1081 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000); 1082 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200); 1083 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000); 1084 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043); 1085 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000); 1086 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000); 1087 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000); 1088 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044); 1089 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002); 1090 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000); 1091 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000); 1092 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019); 1093 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000); 1094 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000); 1095 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000); 1096 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C); 1097 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000); 1098 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000); 1099 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000); 1100 if (par->WaitVSyncPossible) 1101 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F); 1102 else 1103 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F); 1104 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000); 1105 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200); 1106 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000); 1107 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A); 1108 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002); 1109 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000); 1110 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000); 1111 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077); 1112 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000); 1113 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200); 1114 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000); 1115 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002); 1116 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF); 1117 NV_WR32(par->PRAMIN, 0x0826 * 4, 1118 par->FbUsableSize | 0x00000002); 1119 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002); 1120#ifdef __BIG_ENDIAN 1121 NV_WR32(par->PRAMIN, 0x0804 * 4, 1122 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000); 1123 NV_WR32(par->PRAMIN, 0x0808 * 4, 1124 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000); 1125 NV_WR32(par->PRAMIN, 0x080C * 4, 1126 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000); 1127 NV_WR32(par->PRAMIN, 0x0810 * 4, 1128 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000); 1129 NV_WR32(par->PRAMIN, 0x0814 * 4, 1130 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000); 1131 NV_WR32(par->PRAMIN, 0x0818 * 4, 1132 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000); 1133 NV_WR32(par->PRAMIN, 0x081C * 4, 1134 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000); 1135 NV_WR32(par->PRAMIN, 0x0820 * 4, 1136 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000); 1137 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001); 1138 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001); 1139#endif 1140 } 1141 if (par->Architecture < NV_ARCH_10) { 1142 if ((par->Chipset & 0x0fff) == 0x0020) { 1143 NV_WR32(par->PRAMIN, 0x0824 * 4, 1144 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000); 1145 NV_WR32(par->PRAMIN, 0x0826 * 4, 1146 NV_RD32(par->PRAMIN, 1147 0x0826 * 4) + par->FbAddress); 1148 } 1149 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF); 1150 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000); 1151 NV_WR32(par->PGRAPH, 0x0084, 0x72111101); 1152 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071); 1153 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31); 1154 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31); 1155 NV_WR32(par->PGRAPH, 0x0140, 0x00000000); 1156 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF); 1157 NV_WR32(par->PGRAPH, 0x0170, 0x10010100); 1158 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF); 1159 NV_WR32(par->PGRAPH, 0x0720, 0x00000001); 1160 NV_WR32(par->PGRAPH, 0x0810, 0x00000000); 1161 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); 1162 } else { 1163 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF); 1164 NV_WR32(par->PGRAPH, 0x0080, 0x00000000); 1165 1166 NV_WR32(par->PGRAPH, 0x0140, 0x00000000); 1167 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF); 1168 NV_WR32(par->PGRAPH, 0x0144, 0x10010100); 1169 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF); 1170 NV_WR32(par->PGRAPH, 0x0720, 0x00000001); 1171 NV_WR32(par->PGRAPH, 0x0710, 1172 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00); 1173 NV_WR32(par->PGRAPH, 0x0710, 1174 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100); 1175 1176 if (par->Architecture == NV_ARCH_10) { 1177 NV_WR32(par->PGRAPH, 0x0084, 0x00118700); 1178 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810); 1179 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030); 1180 1181 for (i = 0; i < 32; i++) 1182 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0, 1183 NV_RD32(&par->PFB[(0x0240 / 4) + i], 1184 0)); 1185 1186 NV_WR32(par->PGRAPH, 0x640, 0); 1187 NV_WR32(par->PGRAPH, 0x644, 0); 1188 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1); 1189 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1); 1190 1191 NV_WR32(par->PGRAPH, 0x0810, 0x00000000); 1192 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); 1193 } else { 1194 if (par->Architecture >= NV_ARCH_40) { 1195 u32 tmp; 1196 1197 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0); 1198 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051); 1199 NV_WR32(par->PGRAPH, 0x0090, 0x00008000); 1200 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f); 1201 1202 tmp = NV_RD32(par->REGS, 0x1540) & 0xff; 1203 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++); 1204 NV_WR32(par->PGRAPH, 0x5000, i); 1205 1206 if ((par->Chipset & 0xfff0) == 0x0040) { 1207 NV_WR32(par->PGRAPH, 0x09b0, 1208 0x83280fff); 1209 NV_WR32(par->PGRAPH, 0x09b4, 1210 0x000000a0); 1211 } else { 1212 NV_WR32(par->PGRAPH, 0x0820, 1213 0x83280eff); 1214 NV_WR32(par->PGRAPH, 0x0824, 1215 0x000000a0); 1216 } 1217 1218 switch (par->Chipset & 0xfff0) { 1219 case 0x0040: 1220 case 0x0210: 1221 NV_WR32(par->PGRAPH, 0x09b8, 1222 0x0078e366); 1223 NV_WR32(par->PGRAPH, 0x09bc, 1224 0x0000014c); 1225 NV_WR32(par->PFB, 0x033C, 1226 NV_RD32(par->PFB, 0x33C) & 1227 0xffff7fff); 1228 break; 1229 case 0x00C0: 1230 case 0x0120: 1231 NV_WR32(par->PGRAPH, 0x0828, 1232 0x007596ff); 1233 NV_WR32(par->PGRAPH, 0x082C, 1234 0x00000108); 1235 break; 1236 case 0x0160: 1237 case 0x01D0: 1238 NV_WR32(par->PMC, 0x1700, 1239 NV_RD32(par->PFB, 0x020C)); 1240 NV_WR32(par->PMC, 0x1704, 0); 1241 NV_WR32(par->PMC, 0x1708, 0); 1242 NV_WR32(par->PMC, 0x170C, 1243 NV_RD32(par->PFB, 0x020C)); 1244 NV_WR32(par->PGRAPH, 0x0860, 0); 1245 NV_WR32(par->PGRAPH, 0x0864, 0); 1246 NV_WR32(par->PRAMDAC, 0x0608, 1247 NV_RD32(par->PRAMDAC, 1248 0x0608) | 0x00100000); 1249 break; 1250 case 0x0140: 1251 NV_WR32(par->PGRAPH, 0x0828, 1252 0x0072cb77); 1253 NV_WR32(par->PGRAPH, 0x082C, 1254 0x00000108); 1255 break; 1256 case 0x0220: 1257 case 0x0230: 1258 NV_WR32(par->PGRAPH, 0x0860, 0); 1259 NV_WR32(par->PGRAPH, 0x0864, 0); 1260 NV_WR32(par->PRAMDAC, 0x0608, 1261 NV_RD32(par->PRAMDAC, 0x0608) | 1262 0x00100000); 1263 break; 1264 case 0x0090: 1265 case 0x0290: 1266 NV_WR32(par->PRAMDAC, 0x0608, 1267 NV_RD32(par->PRAMDAC, 0x0608) | 1268 0x00100000); 1269 NV_WR32(par->PGRAPH, 0x0828, 1270 0x07830610); 1271 NV_WR32(par->PGRAPH, 0x082C, 1272 0x0000016A); 1273 break; 1274 default: 1275 break; 1276 }; 1277 1278 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800); 1279 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000); 1280 NV_WR32(par->PGRAPH, 0x032C, 0x01000000); 1281 NV_WR32(par->PGRAPH, 0x0220, 0x00001200); 1282 } else if (par->Architecture == NV_ARCH_30) { 1283 NV_WR32(par->PGRAPH, 0x0084, 0x40108700); 1284 NV_WR32(par->PGRAPH, 0x0890, 0x00140000); 1285 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431); 1286 NV_WR32(par->PGRAPH, 0x0090, 0x00008000); 1287 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36); 1288 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888); 1289 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f); 1290 } else { 1291 NV_WR32(par->PGRAPH, 0x0084, 0x00118700); 1292 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431); 1293 NV_WR32(par->PGRAPH, 0x0090, 0x00000000); 1294 NV_WR32(par->PGRAPH, 0x009C, 0x00000040); 1295 1296 if ((par->Chipset & 0x0ff0) >= 0x0250) { 1297 NV_WR32(par->PGRAPH, 0x0890, 1298 0x00080000); 1299 NV_WR32(par->PGRAPH, 0x0610, 1300 0x304B1FB6); 1301 NV_WR32(par->PGRAPH, 0x0B80, 1302 0x18B82880); 1303 NV_WR32(par->PGRAPH, 0x0B84, 1304 0x44000000); 1305 NV_WR32(par->PGRAPH, 0x0098, 1306 0x40000080); 1307 NV_WR32(par->PGRAPH, 0x0B88, 1308 0x000000ff); 1309 } else { 1310 NV_WR32(par->PGRAPH, 0x0880, 1311 0x00080000); 1312 NV_WR32(par->PGRAPH, 0x0094, 1313 0x00000005); 1314 NV_WR32(par->PGRAPH, 0x0B80, 1315 0x45CAA208); 1316 NV_WR32(par->PGRAPH, 0x0B84, 1317 0x24000000); 1318 NV_WR32(par->PGRAPH, 0x0098, 1319 0x00000040); 1320 NV_WR32(par->PGRAPH, 0x0750, 1321 0x00E00038); 1322 NV_WR32(par->PGRAPH, 0x0754, 1323 0x00000030); 1324 NV_WR32(par->PGRAPH, 0x0750, 1325 0x00E10038); 1326 NV_WR32(par->PGRAPH, 0x0754, 1327 0x00000030); 1328 } 1329 } 1330 1331 if ((par->Architecture < NV_ARCH_40) || 1332 ((par->Chipset & 0xfff0) == 0x0040)) { 1333 for (i = 0; i < 32; i++) { 1334 NV_WR32(par->PGRAPH, 0x0900 + i*4, 1335 NV_RD32(par->PFB, 0x0240 +i*4)); 1336 NV_WR32(par->PGRAPH, 0x6900 + i*4, 1337 NV_RD32(par->PFB, 0x0240 +i*4)); 1338 } 1339 } else { 1340 if (((par->Chipset & 0xfff0) == 0x0090) || 1341 ((par->Chipset & 0xfff0) == 0x01D0) || 1342 ((par->Chipset & 0xfff0) == 0x0290)) { 1343 for (i = 0; i < 60; i++) { 1344 NV_WR32(par->PGRAPH, 1345 0x0D00 + i*4, 1346 NV_RD32(par->PFB, 1347 0x0600 + i*4)); 1348 NV_WR32(par->PGRAPH, 1349 0x6900 + i*4, 1350 NV_RD32(par->PFB, 1351 0x0600 + i*4)); 1352 } 1353 } else { 1354 for (i = 0; i < 48; i++) { 1355 NV_WR32(par->PGRAPH, 1356 0x0900 + i*4, 1357 NV_RD32(par->PFB, 1358 0x0600 + i*4)); 1359 if(((par->Chipset & 0xfff0) 1360 != 0x0160) && 1361 ((par->Chipset & 0xfff0) 1362 != 0x0220)) 1363 NV_WR32(par->PGRAPH, 1364 0x6900 + i*4, 1365 NV_RD32(par->PFB, 1366 0x0600 + i*4)); 1367 } 1368 } 1369 } 1370 1371 if (par->Architecture >= NV_ARCH_40) { 1372 if ((par->Chipset & 0xfff0) == 0x0040) { 1373 NV_WR32(par->PGRAPH, 0x09A4, 1374 NV_RD32(par->PFB, 0x0200)); 1375 NV_WR32(par->PGRAPH, 0x09A8, 1376 NV_RD32(par->PFB, 0x0204)); 1377 NV_WR32(par->PGRAPH, 0x69A4, 1378 NV_RD32(par->PFB, 0x0200)); 1379 NV_WR32(par->PGRAPH, 0x69A8, 1380 NV_RD32(par->PFB, 0x0204)); 1381 1382 NV_WR32(par->PGRAPH, 0x0820, 0); 1383 NV_WR32(par->PGRAPH, 0x0824, 0); 1384 NV_WR32(par->PGRAPH, 0x0864, 1385 par->FbMapSize - 1); 1386 NV_WR32(par->PGRAPH, 0x0868, 1387 par->FbMapSize - 1); 1388 } else { 1389 if ((par->Chipset & 0xfff0) == 0x0090 || 1390 (par->Chipset & 0xfff0) == 0x01D0 || 1391 (par->Chipset & 0xfff0) == 0x0290) { 1392 NV_WR32(par->PGRAPH, 0x0DF0, 1393 NV_RD32(par->PFB, 0x0200)); 1394 NV_WR32(par->PGRAPH, 0x0DF4, 1395 NV_RD32(par->PFB, 0x0204)); 1396 } else { 1397 NV_WR32(par->PGRAPH, 0x09F0, 1398 NV_RD32(par->PFB, 0x0200)); 1399 NV_WR32(par->PGRAPH, 0x09F4, 1400 NV_RD32(par->PFB, 0x0204)); 1401 } 1402 NV_WR32(par->PGRAPH, 0x69F0, 1403 NV_RD32(par->PFB, 0x0200)); 1404 NV_WR32(par->PGRAPH, 0x69F4, 1405 NV_RD32(par->PFB, 0x0204)); 1406 1407 NV_WR32(par->PGRAPH, 0x0840, 0); 1408 NV_WR32(par->PGRAPH, 0x0844, 0); 1409 NV_WR32(par->PGRAPH, 0x08a0, 1410 par->FbMapSize - 1); 1411 NV_WR32(par->PGRAPH, 0x08a4, 1412 par->FbMapSize - 1); 1413 } 1414 } else { 1415 NV_WR32(par->PGRAPH, 0x09A4, 1416 NV_RD32(par->PFB, 0x0200)); 1417 NV_WR32(par->PGRAPH, 0x09A8, 1418 NV_RD32(par->PFB, 0x0204)); 1419 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000); 1420 NV_WR32(par->PGRAPH, 0x0754, 1421 NV_RD32(par->PFB, 0x0200)); 1422 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004); 1423 NV_WR32(par->PGRAPH, 0x0754, 1424 NV_RD32(par->PFB, 0x0204)); 1425 1426 NV_WR32(par->PGRAPH, 0x0820, 0); 1427 NV_WR32(par->PGRAPH, 0x0824, 0); 1428 NV_WR32(par->PGRAPH, 0x0864, 1429 par->FbMapSize - 1); 1430 NV_WR32(par->PGRAPH, 0x0868, 1431 par->FbMapSize - 1); 1432 } 1433 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000); 1434 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF); 1435 } 1436 } 1437 NV_WR32(par->PGRAPH, 0x053C, 0); 1438 NV_WR32(par->PGRAPH, 0x0540, 0); 1439 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF); 1440 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF); 1441 1442 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000); 1443 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001); 1444 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000); 1445 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000); 1446 if (par->Architecture >= NV_ARCH_40) 1447 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000); 1448 else 1449 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100); 1450 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000); 1451 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000); 1452 if (par->Architecture >= NV_ARCH_40) 1453 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213); 1454 else 1455 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209); 1456 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000); 1457 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000); 1458 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100); 1459 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110); 1460 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112); 1461 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF); 1462 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF); 1463 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000); 1464 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF); 1465 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001); 1466 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000); 1467 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000); 1468#ifdef __BIG_ENDIAN 1469 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078); 1470#else 1471 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078); 1472#endif 1473 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001); 1474 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001); 1475 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001); 1476 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001); 1477 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001); 1478 if (par->Architecture >= NV_ARCH_10) { 1479 if (par->twoHeads) { 1480 NV_WR32(par->PCRTC0, 0x0860, state->head); 1481 NV_WR32(par->PCRTC0, 0x2860, state->head2); 1482 } 1483 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) | 1484 (1 << 25)); 1485 1486 NV_WR32(par->PMC, 0x8704, 1); 1487 NV_WR32(par->PMC, 0x8140, 0); 1488 NV_WR32(par->PMC, 0x8920, 0); 1489 NV_WR32(par->PMC, 0x8924, 0); 1490 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1); 1491 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1); 1492 NV_WR32(par->PMC, 0x1588, 0); 1493 1494 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig); 1495 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3); 1496 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1); 1497 1498 if (par->FlatPanel) { 1499 if ((par->Chipset & 0x0ff0) == 0x0110) { 1500 NV_WR32(par->PRAMDAC, 0x0528, state->dither); 1501 } else if (par->twoHeads) { 1502 NV_WR32(par->PRAMDAC, 0x083C, state->dither); 1503 } 1504 1505 VGA_WR08(par->PCIO, 0x03D4, 0x53); 1506 VGA_WR08(par->PCIO, 0x03D5, state->timingH); 1507 VGA_WR08(par->PCIO, 0x03D4, 0x54); 1508 VGA_WR08(par->PCIO, 0x03D5, state->timingV); 1509 VGA_WR08(par->PCIO, 0x03D4, 0x21); 1510 VGA_WR08(par->PCIO, 0x03D5, 0xfa); 1511 } 1512 1513 VGA_WR08(par->PCIO, 0x03D4, 0x41); 1514 VGA_WR08(par->PCIO, 0x03D5, state->extra); 1515 } 1516 1517 VGA_WR08(par->PCIO, 0x03D4, 0x19); 1518 VGA_WR08(par->PCIO, 0x03D5, state->repaint0); 1519 VGA_WR08(par->PCIO, 0x03D4, 0x1A); 1520 VGA_WR08(par->PCIO, 0x03D5, state->repaint1); 1521 VGA_WR08(par->PCIO, 0x03D4, 0x25); 1522 VGA_WR08(par->PCIO, 0x03D5, state->screen); 1523 VGA_WR08(par->PCIO, 0x03D4, 0x28); 1524 VGA_WR08(par->PCIO, 0x03D5, state->pixel); 1525 VGA_WR08(par->PCIO, 0x03D4, 0x2D); 1526 VGA_WR08(par->PCIO, 0x03D5, state->horiz); 1527 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 1528 VGA_WR08(par->PCIO, 0x03D5, state->fifo); 1529 VGA_WR08(par->PCIO, 0x03D4, 0x1B); 1530 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0); 1531 VGA_WR08(par->PCIO, 0x03D4, 0x20); 1532 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1); 1533 1534 if(par->Architecture >= NV_ARCH_30) { 1535 VGA_WR08(par->PCIO, 0x03D4, 0x47); 1536 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8); 1537 } 1538 1539 VGA_WR08(par->PCIO, 0x03D4, 0x30); 1540 VGA_WR08(par->PCIO, 0x03D5, state->cursor0); 1541 VGA_WR08(par->PCIO, 0x03D4, 0x31); 1542 VGA_WR08(par->PCIO, 0x03D5, state->cursor1); 1543 VGA_WR08(par->PCIO, 0x03D4, 0x2F); 1544 VGA_WR08(par->PCIO, 0x03D5, state->cursor2); 1545 VGA_WR08(par->PCIO, 0x03D4, 0x39); 1546 VGA_WR08(par->PCIO, 0x03D5, state->interlace); 1547 1548 if (!par->FlatPanel) { 1549 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel); 1550 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll); 1551 if (par->twoHeads) 1552 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2); 1553 if (par->twoStagePLL) { 1554 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB); 1555 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B); 1556 } 1557 } else { 1558 NV_WR32(par->PRAMDAC, 0x0848, state->scale); 1559 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync + 1560 par->PanelTweak); 1561 } 1562 1563 NV_WR32(par->PRAMDAC, 0x0600, state->general); 1564 1565 NV_WR32(par->PCRTC, 0x0140, 0); 1566 NV_WR32(par->PCRTC, 0x0100, 1); 1567 1568 par->CurrentState = state; 1569} 1570 1571void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) { 1572 VGA_WR08(par->PCIO, 0x03D4, 0x19); 1573 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5); 1574 VGA_WR08(par->PCIO, 0x03D4, 0x1A); 1575 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5); 1576 VGA_WR08(par->PCIO, 0x03D4, 0x25); 1577 state->screen = VGA_RD08(par->PCIO, 0x03D5); 1578 VGA_WR08(par->PCIO, 0x03D4, 0x28); 1579 state->pixel = VGA_RD08(par->PCIO, 0x03D5); 1580 VGA_WR08(par->PCIO, 0x03D4, 0x2D); 1581 state->horiz = VGA_RD08(par->PCIO, 0x03D5); 1582 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 1583 state->fifo = VGA_RD08(par->PCIO, 0x03D5); 1584 VGA_WR08(par->PCIO, 0x03D4, 0x1B); 1585 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5); 1586 VGA_WR08(par->PCIO, 0x03D4, 0x20); 1587 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5); 1588 1589 if(par->Architecture >= NV_ARCH_30) { 1590 VGA_WR08(par->PCIO, 0x03D4, 0x47); 1591 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8; 1592 } 1593 1594 VGA_WR08(par->PCIO, 0x03D4, 0x30); 1595 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5); 1596 VGA_WR08(par->PCIO, 0x03D4, 0x31); 1597 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5); 1598 VGA_WR08(par->PCIO, 0x03D4, 0x2F); 1599 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5); 1600 VGA_WR08(par->PCIO, 0x03D4, 0x39); 1601 state->interlace = VGA_RD08(par->PCIO, 0x03D5); 1602 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508); 1603 if (par->twoHeads) 1604 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); 1605 if (par->twoStagePLL) { 1606 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578); 1607 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); 1608 } 1609 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C); 1610 state->general = NV_RD32(par->PRAMDAC, 0x0600); 1611 state->scale = NV_RD32(par->PRAMDAC, 0x0848); 1612 state->config = NV_RD32(par->PFB, 0x0200); 1613 1614 if (par->Architecture >= NV_ARCH_10) { 1615 if (par->twoHeads) { 1616 state->head = NV_RD32(par->PCRTC0, 0x0860); 1617 state->head2 = NV_RD32(par->PCRTC0, 0x2860); 1618 VGA_WR08(par->PCIO, 0x03D4, 0x44); 1619 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5); 1620 } 1621 VGA_WR08(par->PCIO, 0x03D4, 0x41); 1622 state->extra = VGA_RD08(par->PCIO, 0x03D5); 1623 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810); 1624 1625 if ((par->Chipset & 0x0ff0) == 0x0110) { 1626 state->dither = NV_RD32(par->PRAMDAC, 0x0528); 1627 } else if (par->twoHeads) { 1628 state->dither = NV_RD32(par->PRAMDAC, 0x083C); 1629 } 1630 1631 if (par->FlatPanel) { 1632 VGA_WR08(par->PCIO, 0x03D4, 0x53); 1633 state->timingH = VGA_RD08(par->PCIO, 0x03D5); 1634 VGA_WR08(par->PCIO, 0x03D4, 0x54); 1635 state->timingV = VGA_RD08(par->PCIO, 0x03D5); 1636 } 1637 } 1638} 1639 1640void NVSetStartAddress(struct nvidia_par *par, u32 start) 1641{ 1642 NV_WR32(par->PCRTC, 0x800, start); 1643}