tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/config.h>
31#include <linux/module.h>
32#include <linux/tty.h>
33#include <linux/ioport.h>
34#include <linux/init.h>
35#include <linux/serial.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/device.h>
39#include <linux/bootmem.h>
40#include <linux/dma-mapping.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include <linux/serial_core.h>
46#include <linux/kernel.h>
47
48#include "cpm_uart.h"
49
50/**************************************************************/
51
52void cpm_line_cr_cmd(int line, int cmd)
53{
54 ushort val;
55 volatile cpm8xx_t *cp = cpmp;
56
57 switch (line) {
58 case UART_SMC1:
59 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
60 break;
61 case UART_SMC2:
62 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
63 break;
64 case UART_SCC1:
65 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
66 break;
67 case UART_SCC2:
68 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
69 break;
70 case UART_SCC3:
71 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
72 break;
73 case UART_SCC4:
74 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
75 break;
76 default:
77 return;
78
79 }
80 cp->cp_cpcr = val;
81 while (cp->cp_cpcr & CPM_CR_FLG) ;
82}
83
84void smc1_lineif(struct uart_cpm_port *pinfo)
85{
86 pinfo->brg = 1;
87}
88
89void smc2_lineif(struct uart_cpm_port *pinfo)
90{
91 pinfo->brg = 2;
92}
93
94void scc1_lineif(struct uart_cpm_port *pinfo)
95{
96 /* XXX SCC1: insert port configuration here */
97 pinfo->brg = 1;
98}
99
100void scc2_lineif(struct uart_cpm_port *pinfo)
101{
102 /* XXX SCC2: insert port configuration here */
103 pinfo->brg = 2;
104}
105
106void scc3_lineif(struct uart_cpm_port *pinfo)
107{
108 /* XXX SCC3: insert port configuration here */
109 pinfo->brg = 3;
110}
111
112void scc4_lineif(struct uart_cpm_port *pinfo)
113{
114 /* XXX SCC4: insert port configuration here */
115 pinfo->brg = 4;
116}
117
118/*
119 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
120 * receive buffer descriptors from dual port ram, and a character
121 * buffer area from host mem. If we are allocating for the console we need
122 * to do it from bootmem
123 */
124int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
125{
126 int dpmemsz, memsz;
127 u8 *dp_mem;
128 uint dp_offset;
129 u8 *mem_addr;
130 dma_addr_t dma_addr = 0;
131
132 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
133
134 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
135 dp_offset = cpm_dpalloc(dpmemsz, 8);
136 if (IS_DPERR(dp_offset)) {
137 printk(KERN_ERR
138 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
139 return -ENOMEM;
140 }
141 dp_mem = cpm_dpram_addr(dp_offset);
142
143 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
144 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
145 if (is_con) {
146 /* was hostalloc but changed cause it blows away the */
147 /* large tlb mapping when pinning the kernel area */
148 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
149 dma_addr = (u32)mem_addr;
150 } else
151 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
152 GFP_KERNEL);
153
154 if (mem_addr == NULL) {
155 cpm_dpfree(dp_offset);
156 printk(KERN_ERR
157 "cpm_uart_cpm1.c: could not allocate coherent memory\n");
158 return -ENOMEM;
159 }
160
161 pinfo->dp_addr = dp_offset;
162 pinfo->mem_addr = mem_addr; /* virtual address*/
163 pinfo->dma_addr = dma_addr; /* physical address*/
164 pinfo->mem_size = memsz;
165
166 pinfo->rx_buf = mem_addr;
167 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
168 * pinfo->rx_fifosize);
169
170 pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
171 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
172
173 return 0;
174}
175
176void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
177{
178 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
179 pinfo->rx_fifosize) +
180 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
181 pinfo->tx_fifosize), pinfo->mem_addr,
182 pinfo->dma_addr);
183
184 cpm_dpfree(pinfo->dp_addr);
185}
186
187/* Setup any dynamic params in the uart desc */
188int cpm_uart_init_portdesc(void)
189{
190 pr_debug("CPM uart[-]:init portdesc\n");
191
192 cpm_uart_nr = 0;
193#ifdef CONFIG_SERIAL_CPM_SMC1
194 cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
195/*
196 * Is SMC1 being relocated?
197 */
198# ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
199 cpm_uart_ports[UART_SMC1].smcup =
200 (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
201# else
202 cpm_uart_ports[UART_SMC1].smcup =
203 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
204# endif
205 cpm_uart_ports[UART_SMC1].port.mapbase =
206 (unsigned long)&cpmp->cp_smc[0];
207 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
208 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
209 cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
210 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
211#endif
212
213#ifdef CONFIG_SERIAL_CPM_SMC2
214 cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
215 cpm_uart_ports[UART_SMC2].smcup =
216 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
217 cpm_uart_ports[UART_SMC2].port.mapbase =
218 (unsigned long)&cpmp->cp_smc[1];
219 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
220 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
221 cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
222 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
223#endif
224
225#ifdef CONFIG_SERIAL_CPM_SCC1
226 cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
227 cpm_uart_ports[UART_SCC1].sccup =
228 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
229 cpm_uart_ports[UART_SCC1].port.mapbase =
230 (unsigned long)&cpmp->cp_scc[0];
231 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
232 ~(UART_SCCM_TX | UART_SCCM_RX);
233 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
234 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
235 cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
236 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
237#endif
238
239#ifdef CONFIG_SERIAL_CPM_SCC2
240 cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
241 cpm_uart_ports[UART_SCC2].sccup =
242 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
243 cpm_uart_ports[UART_SCC2].port.mapbase =
244 (unsigned long)&cpmp->cp_scc[1];
245 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
246 ~(UART_SCCM_TX | UART_SCCM_RX);
247 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
248 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
249 cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
250 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
251#endif
252
253#ifdef CONFIG_SERIAL_CPM_SCC3
254 cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
255 cpm_uart_ports[UART_SCC3].sccup =
256 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
257 cpm_uart_ports[UART_SCC3].port.mapbase =
258 (unsigned long)&cpmp->cp_scc[2];
259 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
260 ~(UART_SCCM_TX | UART_SCCM_RX);
261 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
262 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
263 cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
264 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
265#endif
266
267#ifdef CONFIG_SERIAL_CPM_SCC4
268 cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
269 cpm_uart_ports[UART_SCC4].sccup =
270 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
271 cpm_uart_ports[UART_SCC4].port.mapbase =
272 (unsigned long)&cpmp->cp_scc[3];
273 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
274 ~(UART_SCCM_TX | UART_SCCM_RX);
275 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
276 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
277 cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
278 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
279#endif
280 return 0;
281}