tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Ethernet driver definitions for the MIPS GT96100 Advanced
24 * Communication Controller.
25 *
26 */
27#ifndef _GT96100ETH_H
28#define _GT96100ETH_H
29
30#include <linux/config.h>
31#include <asm/galileo-boards/gt96100.h>
32
33#define dbg(lvl, format, arg...) \
34 if (lvl <= GT96100_DEBUG) \
35 printk(KERN_DEBUG "%s: " format, dev->name , ## arg)
36#define err(format, arg...) \
37 printk(KERN_ERR "%s: " format, dev->name , ## arg)
38#define info(format, arg...) \
39 printk(KERN_INFO "%s: " format, dev->name , ## arg)
40#define warn(format, arg...) \
41 printk(KERN_WARNING "%s: " format, dev->name , ## arg)
42
43/* Keep the ring sizes a power of two for efficiency. */
44#define TX_RING_SIZE 16
45#define RX_RING_SIZE 32
46#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
47
48#define RX_HASH_TABLE_SIZE 16384
49#define HASH_HOP_NUMBER 12
50
51#define NUM_INTERFACES 2
52
53#define GT96100ETH_TX_TIMEOUT HZ/4
54
55#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
56#define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE)
57
58#ifdef CONFIG_MIPS_EV96100
59#define GT96100_ETHER0_IRQ 3
60#define GT96100_ETHER1_IRQ 4
61#else
62#define GT96100_ETHER0_IRQ -1
63#define GT96100_ETHER1_IRQ -1
64#endif
65
66#define REV_GT96100 1
67#define REV_GT96100A_1 2
68#define REV_GT96100A 3
69
70#define GT96100ETH_READ(gp, offset) \
71 GT96100_READ((gp->port_offset + offset))
72
73#define GT96100ETH_WRITE(gp, offset, data) \
74 GT96100_WRITE((gp->port_offset + offset), data)
75
76#define GT96100ETH_SETBIT(gp, offset, bits) {\
77 u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \
78 GT96100ETH_WRITE(gp, offset, val); }
79
80#define GT96100ETH_CLRBIT(gp, offset, bits) {\
81 u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \
82 GT96100ETH_WRITE(gp, offset, val); }
83
84
85/* Bit definitions of the SMI Reg */
86enum {
87 smirDataMask = 0xffff,
88 smirPhyAdMask = 0x1f<<16,
89 smirPhyAdBit = 16,
90 smirRegAdMask = 0x1f<<21,
91 smirRegAdBit = 21,
92 smirOpCode = 1<<26,
93 smirReadValid = 1<<27,
94 smirBusy = 1<<28
95};
96
97/* Bit definitions of the Port Config Reg */
98enum pcr_bits {
99 pcrPM = 1,
100 pcrRBM = 2,
101 pcrPBF = 4,
102 pcrEN = 1<<7,
103 pcrLPBKMask = 0x3<<8,
104 pcrLPBKBit = 8,
105 pcrFC = 1<<10,
106 pcrHS = 1<<12,
107 pcrHM = 1<<13,
108 pcrHDM = 1<<14,
109 pcrHD = 1<<15,
110 pcrISLMask = 0x7<<28,
111 pcrISLBit = 28,
112 pcrACCS = 1<<31
113};
114
115/* Bit definitions of the Port Config Extend Reg */
116enum pcxr_bits {
117 pcxrIGMP = 1,
118 pcxrSPAN = 2,
119 pcxrPAR = 4,
120 pcxrPRIOtxMask = 0x7<<3,
121 pcxrPRIOtxBit = 3,
122 pcxrPRIOrxMask = 0x3<<6,
123 pcxrPRIOrxBit = 6,
124 pcxrPRIOrxOverride = 1<<8,
125 pcxrDPLXen = 1<<9,
126 pcxrFCTLen = 1<<10,
127 pcxrFLP = 1<<11,
128 pcxrFCTL = 1<<12,
129 pcxrMFLMask = 0x3<<14,
130 pcxrMFLBit = 14,
131 pcxrMIBclrMode = 1<<16,
132 pcxrSpeed = 1<<18,
133 pcxrSpeeden = 1<<19,
134 pcxrRMIIen = 1<<20,
135 pcxrDSCPen = 1<<21
136};
137
138/* Bit definitions of the Port Command Reg */
139enum pcmr_bits {
140 pcmrFJ = 1<<15
141};
142
143
144/* Bit definitions of the Port Status Reg */
145enum psr_bits {
146 psrSpeed = 1,
147 psrDuplex = 2,
148 psrFctl = 4,
149 psrLink = 8,
150 psrPause = 1<<4,
151 psrTxLow = 1<<5,
152 psrTxHigh = 1<<6,
153 psrTxInProg = 1<<7
154};
155
156/* Bit definitions of the SDMA Config Reg */
157enum sdcr_bits {
158 sdcrRCMask = 0xf<<2,
159 sdcrRCBit = 2,
160 sdcrBLMR = 1<<6,
161 sdcrBLMT = 1<<7,
162 sdcrPOVR = 1<<8,
163 sdcrRIFB = 1<<9,
164 sdcrBSZMask = 0x3<<12,
165 sdcrBSZBit = 12
166};
167
168/* Bit definitions of the SDMA Command Reg */
169enum sdcmr_bits {
170 sdcmrERD = 1<<7,
171 sdcmrAR = 1<<15,
172 sdcmrSTDH = 1<<16,
173 sdcmrSTDL = 1<<17,
174 sdcmrTXDH = 1<<23,
175 sdcmrTXDL = 1<<24,
176 sdcmrAT = 1<<31
177};
178
179/* Bit definitions of the Interrupt Cause Reg */
180enum icr_bits {
181 icrRxBuffer = 1,
182 icrTxBufferHigh = 1<<2,
183 icrTxBufferLow = 1<<3,
184 icrTxEndHigh = 1<<6,
185 icrTxEndLow = 1<<7,
186 icrRxError = 1<<8,
187 icrTxErrorHigh = 1<<10,
188 icrTxErrorLow = 1<<11,
189 icrRxOVR = 1<<12,
190 icrTxUdr = 1<<13,
191 icrRxBufferQ0 = 1<<16,
192 icrRxBufferQ1 = 1<<17,
193 icrRxBufferQ2 = 1<<18,
194 icrRxBufferQ3 = 1<<19,
195 icrRxErrorQ0 = 1<<20,
196 icrRxErrorQ1 = 1<<21,
197 icrRxErrorQ2 = 1<<22,
198 icrRxErrorQ3 = 1<<23,
199 icrMIIPhySTC = 1<<28,
200 icrSMIdone = 1<<29,
201 icrEtherIntSum = 1<<31
202};
203
204
205/* The Rx and Tx descriptor lists. */
206typedef struct {
207#ifdef DESC_BE
208 u16 byte_cnt;
209 u16 reserved;
210#else
211 u16 reserved;
212 u16 byte_cnt;
213#endif
214 u32 cmdstat;
215 u32 next;
216 u32 buff_ptr;
217} __attribute__ ((packed)) gt96100_td_t;
218
219typedef struct {
220#ifdef DESC_BE
221 u16 buff_sz;
222 u16 byte_cnt;
223#else
224 u16 byte_cnt;
225 u16 buff_sz;
226#endif
227 u32 cmdstat;
228 u32 next;
229 u32 buff_ptr;
230} __attribute__ ((packed)) gt96100_rd_t;
231
232
233/* Values for the Tx command-status descriptor entry. */
234enum td_cmdstat {
235 txOwn = 1<<31,
236 txAutoMode = 1<<30,
237 txEI = 1<<23,
238 txGenCRC = 1<<22,
239 txPad = 1<<18,
240 txFirst = 1<<17,
241 txLast = 1<<16,
242 txErrorSummary = 1<<15,
243 txReTxCntMask = 0x0f<<10,
244 txReTxCntBit = 10,
245 txCollision = 1<<9,
246 txReTxLimit = 1<<8,
247 txUnderrun = 1<<6,
248 txLateCollision = 1<<5
249};
250
251
252/* Values for the Rx command-status descriptor entry. */
253enum rd_cmdstat {
254 rxOwn = 1<<31,
255 rxAutoMode = 1<<30,
256 rxEI = 1<<23,
257 rxFirst = 1<<17,
258 rxLast = 1<<16,
259 rxErrorSummary = 1<<15,
260 rxIGMP = 1<<14,
261 rxHashExpired = 1<<13,
262 rxMissedFrame = 1<<12,
263 rxFrameType = 1<<11,
264 rxShortFrame = 1<<8,
265 rxMaxFrameLen = 1<<7,
266 rxOverrun = 1<<6,
267 rxCollision = 1<<4,
268 rxCRCError = 1
269};
270
271/* Bit fields of a Hash Table Entry */
272enum hash_table_entry {
273 hteValid = 1,
274 hteSkip = 2,
275 hteRD = 4
276};
277
278// The MIB counters
279typedef struct {
280 u32 byteReceived;
281 u32 byteSent;
282 u32 framesReceived;
283 u32 framesSent;
284 u32 totalByteReceived;
285 u32 totalFramesReceived;
286 u32 broadcastFramesReceived;
287 u32 multicastFramesReceived;
288 u32 cRCError;
289 u32 oversizeFrames;
290 u32 fragments;
291 u32 jabber;
292 u32 collision;
293 u32 lateCollision;
294 u32 frames64;
295 u32 frames65_127;
296 u32 frames128_255;
297 u32 frames256_511;
298 u32 frames512_1023;
299 u32 frames1024_MaxSize;
300 u32 macRxError;
301 u32 droppedFrames;
302 u32 outMulticastFrames;
303 u32 outBroadcastFrames;
304 u32 undersizeFrames;
305} mib_counters_t;
306
307
308struct gt96100_private {
309 gt96100_rd_t* rx_ring;
310 gt96100_td_t* tx_ring;
311 // The Rx and Tx rings must be 16-byte aligned
312 dma_addr_t rx_ring_dma;
313 dma_addr_t tx_ring_dma;
314 char* hash_table;
315 // The Hash Table must be 8-byte aligned
316 dma_addr_t hash_table_dma;
317 int hash_mode;
318
319 // The Rx buffers must be 8-byte aligned
320 char* rx_buff;
321 dma_addr_t rx_buff_dma;
322 // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
323 // of payload must be 8-byte aligned
324 struct sk_buff* tx_skbuff[TX_RING_SIZE];
325 int rx_next_out; /* The next free ring entry to receive */
326 int tx_next_in; /* The next free ring entry to send */
327 int tx_next_out; /* The last ring entry the ISR processed */
328 int tx_count; /* current # of pkts waiting to be sent in Tx ring */
329 int intr_work_done; /* number of Rx and Tx pkts processed in the isr */
330 int tx_full; /* Tx ring is full */
331
332 mib_counters_t mib;
333 struct net_device_stats stats;
334
335 int io_size;
336 int port_num; // 0 or 1
337 int chip_rev;
338 u32 port_offset;
339
340 int phy_addr; // PHY address
341 u32 last_psr; // last value of the port status register
342
343 int options; /* User-settable misc. driver options. */
344 int drv_flags;
345 struct timer_list timer;
346 spinlock_t lock; /* Serialise access to device */
347};
348
349#endif