tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33/* General customization:
34 */
35
36#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
37
38#define DRIVER_NAME "i915"
39#define DRIVER_DESC "Intel Graphics"
40#define DRIVER_DATE "20060119"
41
42/* Interface history:
43 *
44 * 1.1: Original.
45 * 1.2: Add Power Management
46 * 1.3: Add vblank support
47 * 1.4: Fix cmdbuffer path, add heap destroy
48 */
49#define DRIVER_MAJOR 1
50#define DRIVER_MINOR 4
51#define DRIVER_PATCHLEVEL 0
52
53typedef struct _drm_i915_ring_buffer {
54 int tail_mask;
55 unsigned long Start;
56 unsigned long End;
57 unsigned long Size;
58 u8 *virtual_start;
59 int head;
60 int tail;
61 int space;
62 drm_local_map_t map;
63} drm_i915_ring_buffer_t;
64
65struct mem_block {
66 struct mem_block *next;
67 struct mem_block *prev;
68 int start;
69 int size;
70 DRMFILE filp; /* 0: free, -1: heap, other: real files */
71};
72
73typedef struct drm_i915_private {
74 drm_local_map_t *sarea;
75 drm_local_map_t *mmio_map;
76
77 drm_i915_sarea_t *sarea_priv;
78 drm_i915_ring_buffer_t ring;
79
80 drm_dma_handle_t *status_page_dmah;
81 void *hw_status_page;
82 dma_addr_t dma_status_page;
83 unsigned long counter;
84
85 int back_offset;
86 int front_offset;
87 int current_page;
88 int page_flipping;
89 int use_mi_batchbuffer_start;
90
91 wait_queue_head_t irq_queue;
92 atomic_t irq_received;
93 atomic_t irq_emitted;
94
95 int tex_lru_log_granularity;
96 int allow_batchbuffer;
97 struct mem_block *agp_heap;
98 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
99} drm_i915_private_t;
100
101extern drm_ioctl_desc_t i915_ioctls[];
102extern int i915_max_ioctl;
103
104 /* i915_dma.c */
105extern void i915_kernel_lost_context(drm_device_t * dev);
106extern int i915_driver_load(struct drm_device *, unsigned long flags);
107extern void i915_driver_lastclose(drm_device_t * dev);
108extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
109extern int i915_driver_device_is_agp(drm_device_t * dev);
110extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
111 unsigned long arg);
112
113/* i915_irq.c */
114extern int i915_irq_emit(DRM_IOCTL_ARGS);
115extern int i915_irq_wait(DRM_IOCTL_ARGS);
116
117extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
118extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
119extern void i915_driver_irq_preinstall(drm_device_t * dev);
120extern void i915_driver_irq_postinstall(drm_device_t * dev);
121extern void i915_driver_irq_uninstall(drm_device_t * dev);
122
123/* i915_mem.c */
124extern int i915_mem_alloc(DRM_IOCTL_ARGS);
125extern int i915_mem_free(DRM_IOCTL_ARGS);
126extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
127extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
128extern void i915_mem_takedown(struct mem_block **heap);
129extern void i915_mem_release(drm_device_t * dev,
130 DRMFILE filp, struct mem_block *heap);
131
132#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
133#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
134#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
135#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
136
137#define I915_VERBOSE 0
138
139#define RING_LOCALS unsigned int outring, ringmask, outcount; \
140 volatile char *virt;
141
142#define BEGIN_LP_RING(n) do { \
143 if (I915_VERBOSE) \
144 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
145 n, __FUNCTION__); \
146 if (dev_priv->ring.space < n*4) \
147 i915_wait_ring(dev, n*4, __FUNCTION__); \
148 outcount = 0; \
149 outring = dev_priv->ring.tail; \
150 ringmask = dev_priv->ring.tail_mask; \
151 virt = dev_priv->ring.virtual_start; \
152} while (0)
153
154#define OUT_RING(n) do { \
155 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
156 *(volatile unsigned int *)(virt + outring) = n; \
157 outcount++; \
158 outring += 4; \
159 outring &= ringmask; \
160} while (0)
161
162#define ADVANCE_LP_RING() do { \
163 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
164 dev_priv->ring.tail = outring; \
165 dev_priv->ring.space -= outcount * 4; \
166 I915_WRITE(LP_RING + RING_TAIL, outring); \
167} while(0)
168
169extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
170
171#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
172#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
173#define CMD_REPORT_HEAD (7<<23)
174#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
175#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
176
177#define INST_PARSER_CLIENT 0x00000000
178#define INST_OP_FLUSH 0x02000000
179#define INST_FLUSH_MAP_CACHE 0x00000001
180
181#define BB1_START_ADDR_MASK (~0x7)
182#define BB1_PROTECTED (1<<0)
183#define BB1_UNPROTECTED (0<<0)
184#define BB2_END_ADDR_MASK (~0x7)
185
186#define I915REG_HWSTAM 0x02098
187#define I915REG_INT_IDENTITY_R 0x020a4
188#define I915REG_INT_MASK_R 0x020a8
189#define I915REG_INT_ENABLE_R 0x020a0
190
191#define SRX_INDEX 0x3c4
192#define SRX_DATA 0x3c5
193#define SR01 1
194#define SR01_SCREEN_OFF (1<<5)
195
196#define PPCR 0x61204
197#define PPCR_ON (1<<0)
198
199#define DVOB 0x61140
200#define DVOB_ON (1<<31)
201#define DVOC 0x61160
202#define DVOC_ON (1<<31)
203#define LVDS 0x61180
204#define LVDS_ON (1<<31)
205
206#define ADPA 0x61100
207#define ADPA_DPMS_MASK (~(3<<10))
208#define ADPA_DPMS_ON (0<<10)
209#define ADPA_DPMS_SUSPEND (1<<10)
210#define ADPA_DPMS_STANDBY (2<<10)
211#define ADPA_DPMS_OFF (3<<10)
212
213#define NOPID 0x2094
214#define LP_RING 0x2030
215#define HP_RING 0x2040
216#define RING_TAIL 0x00
217#define TAIL_ADDR 0x001FFFF8
218#define RING_HEAD 0x04
219#define HEAD_WRAP_COUNT 0xFFE00000
220#define HEAD_WRAP_ONE 0x00200000
221#define HEAD_ADDR 0x001FFFFC
222#define RING_START 0x08
223#define START_ADDR 0x0xFFFFF000
224#define RING_LEN 0x0C
225#define RING_NR_PAGES 0x001FF000
226#define RING_REPORT_MASK 0x00000006
227#define RING_REPORT_64K 0x00000002
228#define RING_REPORT_128K 0x00000004
229#define RING_NO_REPORT 0x00000000
230#define RING_VALID_MASK 0x00000001
231#define RING_VALID 0x00000001
232#define RING_INVALID 0x00000000
233
234#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
235#define SC_UPDATE_SCISSOR (0x1<<1)
236#define SC_ENABLE_MASK (0x1<<0)
237#define SC_ENABLE (0x1<<0)
238
239#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
240#define SCI_YMIN_MASK (0xffff<<16)
241#define SCI_XMIN_MASK (0xffff<<0)
242#define SCI_YMAX_MASK (0xffff<<16)
243#define SCI_XMAX_MASK (0xffff<<0)
244
245#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
246#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
247#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
248#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
249#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
250#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
251#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
252
253#define MI_BATCH_BUFFER ((0x30<<23)|1)
254#define MI_BATCH_BUFFER_START (0x31<<23)
255#define MI_BATCH_BUFFER_END (0xA<<23)
256#define MI_BATCH_NON_SECURE (1)
257
258#define MI_WAIT_FOR_EVENT ((0x3<<23))
259#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
260#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
261
262#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
263
264#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
265#define ASYNC_FLIP (1<<22)
266
267#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
268
269#define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5])
270
271#endif