tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <linux/config.h>
9#include <asm/asm-compat.h>
10
11#ifndef __ASSEMBLY__
12#error __FILE__ should only be used in assembler files
13#else
14
15#define SZL (BITS_PER_LONG/8)
16
17/*
18 * Stuff for accurate CPU time accounting.
19 * These macros handle transitions between user and system state
20 * in exception entry and exit and accumulate time to the
21 * user_time and system_time fields in the paca.
22 */
23
24#ifndef CONFIG_VIRT_CPU_ACCOUNTING
25#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
26#define ACCOUNT_CPU_USER_EXIT(ra, rb)
27#else
28#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
29 beq 2f; /* if from kernel mode */ \
30BEGIN_FTR_SECTION; \
31 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
32END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
33BEGIN_FTR_SECTION; \
34 mftb ra; /* or get TB if no PURR */ \
35END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
36 ld rb,PACA_STARTPURR(r13); \
37 std ra,PACA_STARTPURR(r13); \
38 subf rb,rb,ra; /* subtract start value */ \
39 ld ra,PACA_USER_TIME(r13); \
40 add ra,ra,rb; /* add on to user time */ \
41 std ra,PACA_USER_TIME(r13); \
422:
43
44#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
45BEGIN_FTR_SECTION; \
46 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
47END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
48BEGIN_FTR_SECTION; \
49 mftb ra; /* or get TB if no PURR */ \
50END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
51 ld rb,PACA_STARTPURR(r13); \
52 std ra,PACA_STARTPURR(r13); \
53 subf rb,rb,ra; /* subtract start value */ \
54 ld ra,PACA_SYSTEM_TIME(r13); \
55 add ra,ra,rb; /* add on to user time */ \
56 std ra,PACA_SYSTEM_TIME(r13);
57#endif
58
59/*
60 * Macros for storing registers into and loading registers from
61 * exception frames.
62 */
63#ifdef __powerpc64__
64#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
65#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
66#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
67#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
68#else
69#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
70#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
71#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
72 SAVE_10GPRS(22, base)
73#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
74 REST_10GPRS(22, base)
75#endif
76
77
78#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
79#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
80#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
81#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
82#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
83#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
84#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
85#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
86
87#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
88#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
89#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
90#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
91#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
92#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
93#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
94#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
95#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
96#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
97#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
98#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
99
100#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
101#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
102#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
103#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
104#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
105#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
106#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
107#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
108#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
109#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
110#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
111#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
112
113#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
114#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
115#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
116#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
117#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
118#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
119#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
120#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
121#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
122#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
123#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
124#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
125
126/* Macros to adjust thread priority for hardware multithreading */
127#define HMT_VERY_LOW or 31,31,31 # very low priority
128#define HMT_LOW or 1,1,1
129#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
130#define HMT_MEDIUM or 2,2,2
131#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
132#define HMT_HIGH or 3,3,3
133
134/* handle instructions that older assemblers may not know */
135#define RFCI .long 0x4c000066 /* rfci instruction */
136#define RFDI .long 0x4c00004e /* rfdi instruction */
137#define RFMCI .long 0x4c00004c /* rfmci instruction */
138
139#ifdef __KERNEL__
140#ifdef CONFIG_PPC64
141
142#define XGLUE(a,b) a##b
143#define GLUE(a,b) XGLUE(a,b)
144
145#define _GLOBAL(name) \
146 .section ".text"; \
147 .align 2 ; \
148 .globl name; \
149 .globl GLUE(.,name); \
150 .section ".opd","aw"; \
151name: \
152 .quad GLUE(.,name); \
153 .quad .TOC.@tocbase; \
154 .quad 0; \
155 .previous; \
156 .type GLUE(.,name),@function; \
157GLUE(.,name):
158
159#define _KPROBE(name) \
160 .section ".kprobes.text","a"; \
161 .align 2 ; \
162 .globl name; \
163 .globl GLUE(.,name); \
164 .section ".opd","aw"; \
165name: \
166 .quad GLUE(.,name); \
167 .quad .TOC.@tocbase; \
168 .quad 0; \
169 .previous; \
170 .type GLUE(.,name),@function; \
171GLUE(.,name):
172
173#define _STATIC(name) \
174 .section ".text"; \
175 .align 2 ; \
176 .section ".opd","aw"; \
177name: \
178 .quad GLUE(.,name); \
179 .quad .TOC.@tocbase; \
180 .quad 0; \
181 .previous; \
182 .type GLUE(.,name),@function; \
183GLUE(.,name):
184
185#else /* 32-bit */
186
187#define _GLOBAL(n) \
188 .text; \
189 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
190 .globl n; \
191n:
192
193#define _KPROBE(n) \
194 .section ".kprobes.text","a"; \
195 .globl n; \
196n:
197
198#endif
199
200/*
201 * LOAD_REG_IMMEDIATE(rn, expr)
202 * Loads the value of the constant expression 'expr' into register 'rn'
203 * using immediate instructions only. Use this when it's important not
204 * to reference other data (i.e. on ppc64 when the TOC pointer is not
205 * valid).
206 *
207 * LOAD_REG_ADDR(rn, name)
208 * Loads the address of label 'name' into register 'rn'. Use this when
209 * you don't particularly need immediate instructions only, but you need
210 * the whole address in one register (e.g. it's a structure address and
211 * you want to access various offsets within it). On ppc32 this is
212 * identical to LOAD_REG_IMMEDIATE.
213 *
214 * LOAD_REG_ADDRBASE(rn, name)
215 * ADDROFF(name)
216 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
217 * register 'rn'. ADDROFF(name) returns the remainder of the address as
218 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
219 * in size, so is suitable for use directly as an offset in load and store
220 * instructions. Use this when loading/storing a single word or less as:
221 * LOAD_REG_ADDRBASE(rX, name)
222 * ld rY,ADDROFF(name)(rX)
223 */
224#ifdef __powerpc64__
225#define LOAD_REG_IMMEDIATE(reg,expr) \
226 lis (reg),(expr)@highest; \
227 ori (reg),(reg),(expr)@higher; \
228 rldicr (reg),(reg),32,31; \
229 oris (reg),(reg),(expr)@h; \
230 ori (reg),(reg),(expr)@l;
231
232#define LOAD_REG_ADDR(reg,name) \
233 ld (reg),name@got(r2)
234
235#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
236#define ADDROFF(name) 0
237
238/* offsets for stack frame layout */
239#define LRSAVE 16
240
241#else /* 32-bit */
242
243#define LOAD_REG_IMMEDIATE(reg,expr) \
244 lis (reg),(expr)@ha; \
245 addi (reg),(reg),(expr)@l;
246
247#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
248
249#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
250#define ADDROFF(name) name@l
251
252/* offsets for stack frame layout */
253#define LRSAVE 4
254
255#endif
256
257/* various errata or part fixups */
258#ifdef CONFIG_PPC601_SYNC_FIX
259#define SYNC \
260BEGIN_FTR_SECTION \
261 sync; \
262 isync; \
263END_FTR_SECTION_IFSET(CPU_FTR_601)
264#define SYNC_601 \
265BEGIN_FTR_SECTION \
266 sync; \
267END_FTR_SECTION_IFSET(CPU_FTR_601)
268#define ISYNC_601 \
269BEGIN_FTR_SECTION \
270 isync; \
271END_FTR_SECTION_IFSET(CPU_FTR_601)
272#else
273#define SYNC
274#define SYNC_601
275#define ISYNC_601
276#endif
277
278
279#ifndef CONFIG_SMP
280#define TLBSYNC
281#else /* CONFIG_SMP */
282/* tlbsync is not implemented on 601 */
283#define TLBSYNC \
284BEGIN_FTR_SECTION \
285 tlbsync; \
286 sync; \
287END_FTR_SECTION_IFCLR(CPU_FTR_601)
288#endif
289
290
291/*
292 * This instruction is not implemented on the PPC 603 or 601; however, on
293 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
294 * All of these instructions exist in the 8xx, they have magical powers,
295 * and they must be used.
296 */
297
298#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
299#define tlbia \
300 li r4,1024; \
301 mtctr r4; \
302 lis r4,KERNELBASE@h; \
3030: tlbie r4; \
304 addi r4,r4,0x1000; \
305 bdnz 0b
306#endif
307
308
309#ifdef CONFIG_IBM440EP_ERR42
310#define PPC440EP_ERR42 isync
311#else
312#define PPC440EP_ERR42
313#endif
314
315
316#if defined(CONFIG_BOOKE)
317#define toreal(rd)
318#define fromreal(rd)
319
320#define tophys(rd,rs) \
321 addis rd,rs,0
322
323#define tovirt(rd,rs) \
324 addis rd,rs,0
325
326#elif defined(CONFIG_PPC64)
327#define toreal(rd) /* we can access c000... in real mode */
328#define fromreal(rd)
329
330#define tophys(rd,rs) \
331 clrldi rd,rs,2
332
333#define tovirt(rd,rs) \
334 rotldi rd,rs,16; \
335 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
336 rotldi rd,rd,48
337#else
338/*
339 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
340 * physical base address of RAM at compile time.
341 */
342#define toreal(rd) tophys(rd,rd)
343#define fromreal(rd) tovirt(rd,rd)
344
345#define tophys(rd,rs) \
3460: addis rd,rs,-KERNELBASE@h; \
347 .section ".vtop_fixup","aw"; \
348 .align 1; \
349 .long 0b; \
350 .previous
351
352#define tovirt(rd,rs) \
3530: addis rd,rs,KERNELBASE@h; \
354 .section ".ptov_fixup","aw"; \
355 .align 1; \
356 .long 0b; \
357 .previous
358#endif
359
360#ifdef CONFIG_PPC64
361#define RFI rfid
362#define MTMSRD(r) mtmsrd r
363
364#else
365#define FIX_SRR1(ra, rb)
366#ifndef CONFIG_40x
367#define RFI rfi
368#else
369#define RFI rfi; b . /* Prevent prefetch past rfi */
370#endif
371#define MTMSRD(r) mtmsr r
372#define CLR_TOP32(r)
373#endif
374
375#endif /* __KERNEL__ */
376
377/* The boring bits... */
378
379/* Condition Register Bit Fields */
380
381#define cr0 0
382#define cr1 1
383#define cr2 2
384#define cr3 3
385#define cr4 4
386#define cr5 5
387#define cr6 6
388#define cr7 7
389
390
391/* General Purpose Registers (GPRs) */
392
393#define r0 0
394#define r1 1
395#define r2 2
396#define r3 3
397#define r4 4
398#define r5 5
399#define r6 6
400#define r7 7
401#define r8 8
402#define r9 9
403#define r10 10
404#define r11 11
405#define r12 12
406#define r13 13
407#define r14 14
408#define r15 15
409#define r16 16
410#define r17 17
411#define r18 18
412#define r19 19
413#define r20 20
414#define r21 21
415#define r22 22
416#define r23 23
417#define r24 24
418#define r25 25
419#define r26 26
420#define r27 27
421#define r28 28
422#define r29 29
423#define r30 30
424#define r31 31
425
426
427/* Floating Point Registers (FPRs) */
428
429#define fr0 0
430#define fr1 1
431#define fr2 2
432#define fr3 3
433#define fr4 4
434#define fr5 5
435#define fr6 6
436#define fr7 7
437#define fr8 8
438#define fr9 9
439#define fr10 10
440#define fr11 11
441#define fr12 12
442#define fr13 13
443#define fr14 14
444#define fr15 15
445#define fr16 16
446#define fr17 17
447#define fr18 18
448#define fr19 19
449#define fr20 20
450#define fr21 21
451#define fr22 22
452#define fr23 23
453#define fr24 24
454#define fr25 25
455#define fr26 26
456#define fr27 27
457#define fr28 28
458#define fr29 29
459#define fr30 30
460#define fr31 31
461
462/* AltiVec Registers (VPRs) */
463
464#define vr0 0
465#define vr1 1
466#define vr2 2
467#define vr3 3
468#define vr4 4
469#define vr5 5
470#define vr6 6
471#define vr7 7
472#define vr8 8
473#define vr9 9
474#define vr10 10
475#define vr11 11
476#define vr12 12
477#define vr13 13
478#define vr14 14
479#define vr15 15
480#define vr16 16
481#define vr17 17
482#define vr18 18
483#define vr19 19
484#define vr20 20
485#define vr21 21
486#define vr22 22
487#define vr23 23
488#define vr24 24
489#define vr25 25
490#define vr26 26
491#define vr27 27
492#define vr28 28
493#define vr29 29
494#define vr30 30
495#define vr31 31
496
497/* SPE Registers (EVPRs) */
498
499#define evr0 0
500#define evr1 1
501#define evr2 2
502#define evr3 3
503#define evr4 4
504#define evr5 5
505#define evr6 6
506#define evr7 7
507#define evr8 8
508#define evr9 9
509#define evr10 10
510#define evr11 11
511#define evr12 12
512#define evr13 13
513#define evr14 14
514#define evr15 15
515#define evr16 16
516#define evr17 17
517#define evr18 18
518#define evr19 19
519#define evr20 20
520#define evr21 21
521#define evr22 22
522#define evr23 23
523#define evr24 24
524#define evr25 25
525#define evr26 26
526#define evr27 27
527#define evr28 28
528#define evr29 29
529#define evr30 30
530#define evr31 31
531
532/* some stab codes */
533#define N_FUN 36
534#define N_RSYM 64
535#define N_SLINE 68
536#define N_SO 100
537
538#endif /* __ASSEMBLY__ */
539
540#endif /* _ASM_POWERPC_PPC_ASM_H */