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Linux kernel mirror (for testing)
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1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/config.h>
28#include <linux/kref.h>
29#include <linux/workqueue.h>
30
31#define LS_SIZE (256 * 1024)
32#define LS_ADDR_MASK (LS_SIZE - 1)
33
34#define MFC_PUT_CMD 0x20
35#define MFC_PUTS_CMD 0x28
36#define MFC_PUTR_CMD 0x30
37#define MFC_PUTF_CMD 0x22
38#define MFC_PUTB_CMD 0x21
39#define MFC_PUTFS_CMD 0x2A
40#define MFC_PUTBS_CMD 0x29
41#define MFC_PUTRF_CMD 0x32
42#define MFC_PUTRB_CMD 0x31
43#define MFC_PUTL_CMD 0x24
44#define MFC_PUTRL_CMD 0x34
45#define MFC_PUTLF_CMD 0x26
46#define MFC_PUTLB_CMD 0x25
47#define MFC_PUTRLF_CMD 0x36
48#define MFC_PUTRLB_CMD 0x35
49
50#define MFC_GET_CMD 0x40
51#define MFC_GETS_CMD 0x48
52#define MFC_GETF_CMD 0x42
53#define MFC_GETB_CMD 0x41
54#define MFC_GETFS_CMD 0x4A
55#define MFC_GETBS_CMD 0x49
56#define MFC_GETL_CMD 0x44
57#define MFC_GETLF_CMD 0x46
58#define MFC_GETLB_CMD 0x45
59
60#define MFC_SDCRT_CMD 0x80
61#define MFC_SDCRTST_CMD 0x81
62#define MFC_SDCRZ_CMD 0x89
63#define MFC_SDCRS_CMD 0x8D
64#define MFC_SDCRF_CMD 0x8F
65
66#define MFC_GETLLAR_CMD 0xD0
67#define MFC_PUTLLC_CMD 0xB4
68#define MFC_PUTLLUC_CMD 0xB0
69#define MFC_PUTQLLUC_CMD 0xB8
70#define MFC_SNDSIG_CMD 0xA0
71#define MFC_SNDSIGB_CMD 0xA1
72#define MFC_SNDSIGF_CMD 0xA2
73#define MFC_BARRIER_CMD 0xC0
74#define MFC_EIEIO_CMD 0xC8
75#define MFC_SYNC_CMD 0xCC
76
77#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
78#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
79#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
80#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
81#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
82#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
83#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
84#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
85
86#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
87
88/* Events for Channels 0-2 */
89#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
90#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
91#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
92#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
93#define MFC_DECREMENTER_EVENT 0x00000020
94#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
95#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
96#define MFC_SIGNAL_2_EVENT 0x00000100
97#define MFC_SIGNAL_1_EVENT 0x00000200
98#define MFC_LLR_LOST_EVENT 0x00000400
99#define MFC_PRIV_ATTN_EVENT 0x00000800
100#define MFC_MULTI_SRC_EVENT 0x00001000
101
102/* Flags indicating progress during context switch. */
103#define SPU_CONTEXT_SWITCH_PENDING 0UL
104#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
105
106struct spu_context;
107struct spu_runqueue;
108
109struct spu {
110 char *name;
111 unsigned long local_store_phys;
112 u8 *local_store;
113 unsigned long problem_phys;
114 struct spu_problem __iomem *problem;
115 struct spu_priv1 __iomem *priv1;
116 struct spu_priv2 __iomem *priv2;
117 struct list_head list;
118 struct list_head sched_list;
119 int number;
120 u32 isrc;
121 u32 node;
122 u64 flags;
123 u64 dar;
124 u64 dsisr;
125 struct kref kref;
126 size_t ls_size;
127 unsigned int slb_replace;
128 struct mm_struct *mm;
129 struct spu_context *ctx;
130 struct spu_runqueue *rq;
131 unsigned long long timestamp;
132 pid_t pid;
133 int prio;
134 int class_0_pending;
135 spinlock_t register_lock;
136
137 u32 stop_code;
138 void (* wbox_callback)(struct spu *spu);
139 void (* ibox_callback)(struct spu *spu);
140 void (* stop_callback)(struct spu *spu);
141 void (* mfc_callback)(struct spu *spu);
142
143 char irq_c0[8];
144 char irq_c1[8];
145 char irq_c2[8];
146};
147
148struct spu *spu_alloc(void);
149void spu_free(struct spu *spu);
150int spu_irq_class_0_bottom(struct spu *spu);
151int spu_irq_class_1_bottom(struct spu *spu);
152void spu_irq_setaffinity(struct spu *spu, int cpu);
153
154/* system callbacks from the SPU */
155struct spu_syscall_block {
156 u64 nr_ret;
157 u64 parm[6];
158};
159extern long spu_sys_callback(struct spu_syscall_block *s);
160
161/* syscalls implemented in spufs */
162extern struct spufs_calls {
163 asmlinkage long (*create_thread)(const char __user *name,
164 unsigned int flags, mode_t mode);
165 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
166 __u32 __user *ustatus);
167 struct module *owner;
168} spufs_calls;
169
170#ifdef CONFIG_SPU_FS_MODULE
171int register_spu_syscalls(struct spufs_calls *calls);
172void unregister_spu_syscalls(struct spufs_calls *calls);
173#else
174static inline int register_spu_syscalls(struct spufs_calls *calls)
175{
176 return 0;
177}
178static inline void unregister_spu_syscalls(struct spufs_calls *calls)
179{
180}
181#endif /* MODULE */
182
183
184/* access to priv1 registers */
185void spu_int_mask_and(struct spu *spu, int class, u64 mask);
186void spu_int_mask_or(struct spu *spu, int class, u64 mask);
187void spu_int_mask_set(struct spu *spu, int class, u64 mask);
188u64 spu_int_mask_get(struct spu *spu, int class);
189void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
190u64 spu_int_stat_get(struct spu *spu, int class);
191void spu_int_route_set(struct spu *spu, u64 route);
192u64 spu_mfc_dar_get(struct spu *spu);
193u64 spu_mfc_dsisr_get(struct spu *spu);
194void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
195void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
196void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
197u64 spu_mfc_sr1_get(struct spu *spu);
198void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
199u64 spu_mfc_tclass_id_get(struct spu *spu);
200void spu_tlb_invalidate(struct spu *spu);
201void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
202u64 spu_resource_allocation_groupID_get(struct spu *spu);
203void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
204u64 spu_resource_allocation_enable_get(struct spu *spu);
205
206
207/*
208 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
209 */
210
211union mfc_tag_size_class_cmd {
212 struct {
213 u16 mfc_size;
214 u16 mfc_tag;
215 u8 pad;
216 u8 mfc_rclassid;
217 u16 mfc_cmd;
218 } u;
219 struct {
220 u32 mfc_size_tag32;
221 u32 mfc_class_cmd32;
222 } by32;
223 u64 all64;
224};
225
226struct mfc_cq_sr {
227 u64 mfc_cq_data0_RW;
228 u64 mfc_cq_data1_RW;
229 u64 mfc_cq_data2_RW;
230 u64 mfc_cq_data3_RW;
231};
232
233struct spu_problem {
234#define MS_SYNC_PENDING 1L
235 u64 spc_mssync_RW; /* 0x0000 */
236 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
237
238 /* DMA Area */
239 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
240 u32 mfc_lsa_W; /* 0x3004 */
241 u64 mfc_ea_W; /* 0x3008 */
242 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
243 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
244 u32 dma_qstatus_R; /* 0x3104 */
245 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
246 u32 dma_querytype_RW; /* 0x3204 */
247 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
248 u32 dma_querymask_RW; /* 0x321c */
249 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
250 u32 dma_tagstatus_R; /* 0x322c */
251#define DMA_TAGSTATUS_INTR_ANY 1u
252#define DMA_TAGSTATUS_INTR_ALL 2u
253 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
254
255 /* SPU Control Area */
256 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
257 u32 pu_mb_R; /* 0x4004 */
258 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
259 u32 spu_mb_W; /* 0x400c */
260 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
261 u32 mb_stat_R; /* 0x4014 */
262 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
263 u32 spu_runcntl_RW; /* 0x401c */
264#define SPU_RUNCNTL_STOP 0L
265#define SPU_RUNCNTL_RUNNABLE 1L
266 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
267 u32 spu_status_R; /* 0x4024 */
268#define SPU_STOP_STATUS_SHIFT 16
269#define SPU_STATUS_STOPPED 0x0
270#define SPU_STATUS_RUNNING 0x1
271#define SPU_STATUS_STOPPED_BY_STOP 0x2
272#define SPU_STATUS_STOPPED_BY_HALT 0x4
273#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
274#define SPU_STATUS_SINGLE_STEP 0x10
275#define SPU_STATUS_INVALID_INSTR 0x20
276#define SPU_STATUS_INVALID_CH 0x40
277#define SPU_STATUS_ISOLATED_STATE 0x80
278#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
279#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
280 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
281 u32 spu_spe_R; /* 0x402c */
282 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
283 u32 spu_npc_RW; /* 0x4034 */
284 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
285
286 /* Signal Notification Area */
287 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
288 u32 signal_notify1; /* 0x1400c */
289 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
290 u32 signal_notify2; /* 0x1c00c */
291} __attribute__ ((aligned(0x20000)));
292
293/* SPU Privilege 2 State Area */
294struct spu_priv2 {
295 /* MFC Registers */
296 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
297
298 /* SLB Management Registers */
299 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
300 u64 slb_index_W; /* 0x1108 */
301#define SLB_INDEX_MASK 0x7L
302 u64 slb_esid_RW; /* 0x1110 */
303 u64 slb_vsid_RW; /* 0x1118 */
304#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
305#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
306#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
307#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
308#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
309#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
310#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
311#define SLB_VSID_4K_PAGE (0x0 << 8)
312#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
313#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
314#define SLB_VSID_CLASS_MASK (0x1ull << 7)
315#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
316 u64 slb_invalidate_entry_W; /* 0x1120 */
317 u64 slb_invalidate_all_W; /* 0x1128 */
318 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
319
320 /* Context Save / Restore Area */
321 struct mfc_cq_sr spuq[16]; /* 0x2000 */
322 struct mfc_cq_sr puq[8]; /* 0x2200 */
323 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
324
325 /* MFC Control */
326 u64 mfc_control_RW; /* 0x3000 */
327#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
328#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
329#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
330#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
331#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
332#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
333#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
334#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
335#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
336#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
337#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
338#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
339#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
340#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
341#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
342#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
343#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
344#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
345#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
346#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
347#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
348#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
349 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
350
351 /* Interrupt Mailbox */
352 u64 puint_mb_R; /* 0x4000 */
353 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
354
355 /* SPU Control */
356 u64 spu_privcntl_RW; /* 0x4040 */
357#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
358#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
359#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
360#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
361#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
362#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
363#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
364#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
365 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
366 u64 spu_lslr_RW; /* 0x4058 */
367 u64 spu_chnlcntptr_RW; /* 0x4060 */
368 u64 spu_chnlcnt_RW; /* 0x4068 */
369 u64 spu_chnldata_RW; /* 0x4070 */
370 u64 spu_cfg_RW; /* 0x4078 */
371 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
372
373 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
374 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
375 u64 spu_tag_status_query_RW; /* 0x5008 */
376#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
377#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
378 u64 spu_cmd_buf1_RW; /* 0x5010 */
379#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
380#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
381 u64 spu_cmd_buf2_RW; /* 0x5018 */
382#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
383#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
384#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
385 u64 spu_atomic_status_RW; /* 0x5020 */
386} __attribute__ ((aligned(0x20000)));
387
388/* SPU Privilege 1 State Area */
389struct spu_priv1 {
390 /* Control and Configuration Area */
391 u64 mfc_sr1_RW; /* 0x000 */
392#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
393#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
394#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
395#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
396#define MFC_STATE1_RELOCATE_MASK 0x10ull
397#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
398 u64 mfc_lpid_RW; /* 0x008 */
399 u64 spu_idr_RW; /* 0x010 */
400 u64 mfc_vr_RO; /* 0x018 */
401#define MFC_VERSION_BITS (0xffff << 16)
402#define MFC_REVISION_BITS (0xffff)
403#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
404#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
405 u64 spu_vr_RO; /* 0x020 */
406#define SPU_VERSION_BITS (0xffff << 16)
407#define SPU_REVISION_BITS (0xffff)
408#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
409#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
410 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
411
412 /* Interrupt Area */
413 u64 int_mask_RW[3]; /* 0x100 */
414#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
415#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
416#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
417#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
418#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
419#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
420#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
421#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
422#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
423#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
424#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
425#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
426 u8 pad_0x118_0x140[0x28]; /* 0x118 */
427 u64 int_stat_RW[3]; /* 0x140 */
428 u8 pad_0x158_0x180[0x28]; /* 0x158 */
429 u64 int_route_RW; /* 0x180 */
430
431 /* Interrupt Routing */
432 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
433
434 /* Atomic Unit Control Area */
435 u64 mfc_atomic_flush_RW; /* 0x200 */
436#define mfc_atomic_flush_enable 0x1L
437 u8 pad_0x208_0x280[0x78]; /* 0x208 */
438 u64 resource_allocation_groupID_RW; /* 0x280 */
439 u64 resource_allocation_enable_RW; /* 0x288 */
440 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
441
442 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
443
444 u64 smf_sbi_signal_sel; /* 0x3c8 */
445#define smf_sbi_mask_lsb 56
446#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
447#define smf_sbi_mask (0x301LL << smf_sbi_shift)
448#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
449#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
450#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
451#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
452 u64 smf_ato_signal_sel; /* 0x3d0 */
453#define smf_ato_mask_lsb 35
454#define smf_ato_shift (63 - smf_ato_mask_lsb)
455#define smf_ato_mask (0x3LL << smf_ato_shift)
456#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
457#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
458 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
459
460 /* TLB Management Registers */
461 u64 mfc_sdr_RW; /* 0x400 */
462 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
463 u64 tlb_index_hint_RO; /* 0x500 */
464 u64 tlb_index_W; /* 0x508 */
465 u64 tlb_vpn_RW; /* 0x510 */
466 u64 tlb_rpn_RW; /* 0x518 */
467 u8 pad_0x520_0x540[0x20]; /* 0x520 */
468 u64 tlb_invalidate_entry_W; /* 0x540 */
469 u64 tlb_invalidate_all_W; /* 0x548 */
470 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
471
472 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
473 u64 smm_hid; /* 0x580 */
474#define PAGE_SIZE_MASK 0xf000000000000000ull
475#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
476 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
477
478 /* MFC Status/Control Area */
479 u64 mfc_accr_RW; /* 0x600 */
480#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
481#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
482#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
483#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
484 u8 pad_0x608_0x610[0x8]; /* 0x608 */
485 u64 mfc_dsisr_RW; /* 0x610 */
486#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
487#define MFC_DSISR_ACCESS_DENIED (1 << 27)
488#define MFC_DSISR_ATOMIC (1 << 26)
489#define MFC_DSISR_ACCESS_PUT (1 << 25)
490#define MFC_DSISR_ADDR_MATCH (1 << 22)
491#define MFC_DSISR_LS (1 << 17)
492#define MFC_DSISR_L (1 << 16)
493#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
494 u8 pad_0x618_0x620[0x8]; /* 0x618 */
495 u64 mfc_dar_RW; /* 0x620 */
496 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
497
498 /* Replacement Management Table (RMT) Area */
499 u64 rmt_index_RW; /* 0x700 */
500 u8 pad_0x708_0x710[0x8]; /* 0x708 */
501 u64 rmt_data1_RW; /* 0x710 */
502 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
503
504 /* Control/Configuration Registers */
505 u64 mfc_dsir_R; /* 0x800 */
506#define MFC_DSIR_Q (1 << 31)
507#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
508 u64 mfc_lsacr_RW; /* 0x808 */
509#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
510#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
511 u64 mfc_lscrr_R; /* 0x810 */
512#define MFC_LSCRR_Q (1 << 31)
513#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
514#define MFC_LSCRR_QI_SHIFT 32
515#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
516 u8 pad_0x818_0x820[0x8]; /* 0x818 */
517 u64 mfc_tclass_id_RW; /* 0x820 */
518#define MFC_TCLASS_ID_ENABLE (1L << 0L)
519#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
520#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
521#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
522#define MFC_TCLASS_QUOTA_2_SHIFT 8L
523#define MFC_TCLASS_QUOTA_1_SHIFT 16L
524#define MFC_TCLASS_QUOTA_0_SHIFT 24L
525#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
526#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
527#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
528 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
529
530 /* Real Mode Support Registers */
531 u64 mfc_rm_boundary; /* 0x900 */
532 u8 pad_0x908_0x938[0x30]; /* 0x908 */
533 u64 smf_dma_signal_sel; /* 0x938 */
534#define mfc_dma1_mask_lsb 41
535#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
536#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
537#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
538#define mfc_dma2_mask_lsb 43
539#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
540#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
541#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
542 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
543 u64 smm_signal_sel; /* 0xa38 */
544#define smm_sig_mask_lsb 12
545#define smm_sig_shift (63 - smm_sig_mask_lsb)
546#define smm_sig_mask (0x3LL << smm_sig_shift)
547#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
548#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
549 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
550
551 /* DMA Command Error Area */
552 u64 mfc_cer_R; /* 0xc00 */
553#define MFC_CER_Q (1 << 31)
554#define MFC_CER_SPU_QUEUE MFC_CER_Q
555 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
556
557 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
558 /* DMA Command Error Area */
559 u64 spu_ecc_cntl_RW; /* 0x1000 */
560#define SPU_ECC_CNTL_E (1ull << 0ull)
561#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
562#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
563#define SPU_ECC_CNTL_S (1ull << 1ull)
564#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
565#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
566#define SPU_ECC_CNTL_B (1ull << 2ull)
567#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
568#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
569#define SPU_ECC_CNTL_I_SHIFT 3ull
570#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
571#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
572#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
573#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
574#define SPU_ECC_CNTL_D (1ull << 5ull)
575#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
576#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
577 u64 spu_ecc_stat_RW; /* 0x1008 */
578#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
579#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
580#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
581#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
582#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
583#define SPU_ECC_DATA_ERROR (1ull << 5ul)
584#define SPU_ECC_DMA_ERROR (1ull << 6ul)
585#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
586 u64 spu_ecc_addr_RW; /* 0x1010 */
587 u64 spu_err_mask_RW; /* 0x1018 */
588#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
589#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
590 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
591
592 /* SPU Debug-Trace Bus (DTB) Selection Registers */
593 u64 spu_trig0_sel; /* 0x1028 */
594 u64 spu_trig1_sel; /* 0x1030 */
595 u64 spu_trig2_sel; /* 0x1038 */
596 u64 spu_trig3_sel; /* 0x1040 */
597 u64 spu_trace_sel; /* 0x1048 */
598#define spu_trace_sel_mask 0x1f1fLL
599#define spu_trace_sel_bus0_bits 0x1000LL
600#define spu_trace_sel_bus2_bits 0x0010LL
601 u64 spu_event0_sel; /* 0x1050 */
602 u64 spu_event1_sel; /* 0x1058 */
603 u64 spu_event2_sel; /* 0x1060 */
604 u64 spu_event3_sel; /* 0x1068 */
605 u64 spu_trace_cntl; /* 0x1070 */
606} __attribute__ ((aligned(0x2000)));
607
608#endif /* __KERNEL__ */
609#endif