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1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Ralf Baechle 7 */ 8#ifndef _ASM_ASMMACRO_H 9#define _ASM_ASMMACRO_H 10 11#include <linux/config.h> 12#include <asm/hazards.h> 13 14#ifdef CONFIG_32BIT 15#include <asm/asmmacro-32.h> 16#endif 17#ifdef CONFIG_64BIT 18#include <asm/asmmacro-64.h> 19#endif 20#ifdef CONFIG_MIPS_MT_SMTC 21#include <asm/mipsmtregs.h> 22#endif 23 24#ifdef CONFIG_MIPS_MT_SMTC 25 .macro local_irq_enable reg=t0 26 mfc0 \reg, CP0_TCSTATUS 27 ori \reg, \reg, TCSTATUS_IXMT 28 xori \reg, \reg, TCSTATUS_IXMT 29 mtc0 \reg, CP0_TCSTATUS 30 ehb 31 .endm 32 33 .macro local_irq_disable reg=t0 34 mfc0 \reg, CP0_TCSTATUS 35 ori \reg, \reg, TCSTATUS_IXMT 36 mtc0 \reg, CP0_TCSTATUS 37 ehb 38 .endm 39#else 40 .macro local_irq_enable reg=t0 41 mfc0 \reg, CP0_STATUS 42 ori \reg, \reg, 1 43 mtc0 \reg, CP0_STATUS 44 irq_enable_hazard 45 .endm 46 47 .macro local_irq_disable reg=t0 48 mfc0 \reg, CP0_STATUS 49 ori \reg, \reg, 1 50 xori \reg, \reg, 1 51 mtc0 \reg, CP0_STATUS 52 irq_disable_hazard 53 .endm 54#endif /* CONFIG_MIPS_MT_SMTC */ 55 56#ifdef CONFIG_CPU_SB1 57 .macro fpu_enable_hazard 58 .set push 59 .set noreorder 60 .set mips2 61 SSNOP 62 bnezl $0, .+4 63 SSNOP 64 .set pop 65 .endm 66#else 67 .macro fpu_enable_hazard 68 .endm 69#endif 70 71/* 72 * Temporary until all gas have MT ASE support 73 */ 74 .macro DMT reg=0 75 .word (0x41600bc1 | (\reg << 16)) 76 .endm 77 78 .macro EMT reg=0 79 .word (0x41600be1 | (\reg << 16)) 80 .endm 81 82 .macro DVPE reg=0 83 .word (0x41600001 | (\reg << 16)) 84 .endm 85 86 .macro EVPE reg=0 87 .word (0x41600021 | (\reg << 16)) 88 .endm 89 90 .macro MFTR rt=0, rd=0, u=0, sel=0 91 .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 92 .endm 93 94 .macro MTTR rt=0, rd=0, u=0, sel=0 95 .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 96 .endm 97 98#endif /* _ASM_ASMMACRO_H */