tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * linux/include/asm-arm/arch-versatile/platform.h
3 *
4 * Copyright (c) ARM Limited 2003. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __address_h
22#define __address_h 1
23
24/*
25 * Memory definitions
26 */
27#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
28#define VERSATILE_BOOT_ROM_HI 0x30000000
29#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
30#define VERSATILE_BOOT_ROM_SIZE SZ_64M
31
32#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
33#define VERSATILE_SSRAM_SIZE SZ_2M
34
35#define VERSATILE_FLASH_BASE 0x34000000
36#define VERSATILE_FLASH_SIZE SZ_64M
37
38/*
39 * SDRAM
40 */
41#define VERSATILE_SDRAM_BASE 0x00000000
42
43/*
44 * Logic expansion modules
45 *
46 */
47
48
49/* ------------------------------------------------------------------------
50 * Versatile Registers
51 * ------------------------------------------------------------------------
52 *
53 */
54#define VERSATILE_SYS_ID_OFFSET 0x00
55#define VERSATILE_SYS_SW_OFFSET 0x04
56#define VERSATILE_SYS_LED_OFFSET 0x08
57#define VERSATILE_SYS_OSC0_OFFSET 0x0C
58
59#if defined(CONFIG_ARCH_VERSATILE_PB)
60#define VERSATILE_SYS_OSC1_OFFSET 0x10
61#define VERSATILE_SYS_OSC2_OFFSET 0x14
62#define VERSATILE_SYS_OSC3_OFFSET 0x18
63#define VERSATILE_SYS_OSC4_OFFSET 0x1C
64#elif defined(CONFIG_MACH_VERSATILE_AB)
65#define VERSATILE_SYS_OSC1_OFFSET 0x1C
66#endif
67
68#define VERSATILE_SYS_LOCK_OFFSET 0x20
69#define VERSATILE_SYS_100HZ_OFFSET 0x24
70#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
71#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
72#define VERSATILE_SYS_FLAGS_OFFSET 0x30
73#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
74#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
75#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
76#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
77#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
78#define VERSATILE_SYS_RESETCTL_OFFSET 0x40
79#define VERSATILE_SYS_PCICTL_OFFSET 0x44
80#define VERSATILE_SYS_MCI_OFFSET 0x48
81#define VERSATILE_SYS_FLASH_OFFSET 0x4C
82#define VERSATILE_SYS_CLCD_OFFSET 0x50
83#define VERSATILE_SYS_CLCDSER_OFFSET 0x54
84#define VERSATILE_SYS_BOOTCS_OFFSET 0x58
85#define VERSATILE_SYS_24MHz_OFFSET 0x5C
86#define VERSATILE_SYS_MISC_OFFSET 0x60
87#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
88#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
89#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
90#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
91#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
92
93#define VERSATILE_SYS_BASE 0x10000000
94#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
95#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
96#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
97#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
98#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
99
100#if defined(CONFIG_ARCH_VERSATILE_PB)
101#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
102#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
103#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
104#endif
105
106#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
107#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
108#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
109#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
110#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
111#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
112#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
113#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
114#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
115#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
116#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
117#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
118#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
119#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
120#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
121#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
122#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
123#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
124#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
125#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
126#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
127#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
128#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
129#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
130
131/*
132 * Values for VERSATILE_SYS_RESET_CTRL
133 */
134#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
135#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
136#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
137#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
138#define VERSATILE_SYS_CTRL_RESET_POR 0x05
139#define VERSATILE_SYS_CTRL_RESET_DoC 0x06
140
141#define VERSATILE_SYS_CTRL_LED (1 << 0)
142
143
144/* ------------------------------------------------------------------------
145 * Versatile control registers
146 * ------------------------------------------------------------------------
147 */
148
149/*
150 * VERSATILE_IDFIELD
151 *
152 * 31:24 = manufacturer (0x41 = ARM)
153 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
154 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
155 * 11:4 = build value
156 * 3:0 = revision number (0x1 = rev B (AHB))
157 */
158
159/*
160 * VERSATILE_SYS_LOCK
161 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
162 * SYS_CLD, SYS_BOOTCS
163 */
164#define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
165#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
166
167/*
168 * VERSATILE_SYS_FLASH
169 */
170#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
171
172/*
173 * VERSATILE_INTREG
174 * - used to acknowledge and control MMCI and UART interrupts
175 */
176#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
177#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
178#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
179 /* write 1 to acknowledge and clear */
180#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
181#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
182
183/*
184 * VERSATILE peripheral addresses
185 */
186#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
187#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
188#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
189#define VERSATILE_AACI_BASE 0x10004000 /* Audio */
190#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
191#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
192#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
193#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
194#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
195#define VERSATILE_SCI1_BASE 0x1000A000
196#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
197 /* 0x1000C000 - 0x1000CFFF = reserved */
198#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
199#define VERSATILE_USB_BASE 0x10020000 /* USB */
200 /* 0x10030000 - 0x100FFFFF = reserved */
201#define VERSATILE_SMC_BASE 0x10100000 /* SMC */
202#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
203#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
204#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
205#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
206#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
207 /* 0x10000000 - 0x100FFFFF */
208#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
209#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
210#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
211#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
212#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
213#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
214#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
215#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
216#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
217#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
218 /* 0x101E9000 - reserved */
219#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
220#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
221#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
222#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
223#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
224
225#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
226#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
227#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
228
229/* PCI space */
230#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
231#define VERSATILE_PCI_CFG_BASE 0x42000000
232#define VERSATILE_PCI_MEM_BASE0 0x44000000
233#define VERSATILE_PCI_MEM_BASE1 0x50000000
234#define VERSATILE_PCI_MEM_BASE2 0x60000000
235/* Sizes of above maps */
236#define VERSATILE_PCI_BASE_SIZE 0x01000000
237#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
238#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
239#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
240#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
241
242#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
243#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
244
245/*
246 * Disk on Chip
247 */
248#define VERSATILE_DOC_BASE 0x2C000000
249#define VERSATILE_DOC_SIZE (16 << 20)
250#define VERSATILE_DOC_PAGE_SIZE 512
251#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
252
253#define ERASE_UNIT_PAGES 32
254#define START_PAGE 0x80
255
256/*
257 * LED settings, bits [7:0]
258 */
259#define VERSATILE_SYS_LED0 (1 << 0)
260#define VERSATILE_SYS_LED1 (1 << 1)
261#define VERSATILE_SYS_LED2 (1 << 2)
262#define VERSATILE_SYS_LED3 (1 << 3)
263#define VERSATILE_SYS_LED4 (1 << 4)
264#define VERSATILE_SYS_LED5 (1 << 5)
265#define VERSATILE_SYS_LED6 (1 << 6)
266#define VERSATILE_SYS_LED7 (1 << 7)
267
268#define ALL_LEDS 0xFF
269
270#define LED_BANK VERSATILE_SYS_LED
271
272/*
273 * Control registers
274 */
275#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */
276#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */
277#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
278#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
279
280
281/* ------------------------------------------------------------------------
282 * Versatile Interrupt Controller - control registers
283 * ------------------------------------------------------------------------
284 *
285 * Offsets from interrupt controller base
286 *
287 * System Controller interrupt controller base is
288 *
289 * VERSATILE_IC_BASE
290 *
291 * Core Module interrupt controller base is
292 *
293 * VERSATILE_SYS_IC
294 *
295 */
296/* VIC definitions in include/asm-arm/hardware/vic.h */
297
298#define SIC_IRQ_STATUS 0
299#define SIC_IRQ_RAW_STATUS 0x04
300#define SIC_IRQ_ENABLE 0x08
301#define SIC_IRQ_ENABLE_SET 0x08
302#define SIC_IRQ_ENABLE_CLEAR 0x0C
303#define SIC_INT_SOFT_SET 0x10
304#define SIC_INT_SOFT_CLEAR 0x14
305#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
306#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
307#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
308
309/* ------------------------------------------------------------------------
310 * Interrupts - bit assignment (primary)
311 * ------------------------------------------------------------------------
312 */
313
314#define INT_WDOGINT 0 /* Watchdog timer */
315#define INT_SOFTINT 1 /* Software interrupt */
316#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
317#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
318#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
319#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
320#define INT_GPIOINT0 6 /* GPIO 0 */
321#define INT_GPIOINT1 7 /* GPIO 1 */
322#define INT_GPIOINT2 8 /* GPIO 2 */
323#define INT_GPIOINT3 9 /* GPIO 3 */
324#define INT_RTCINT 10 /* Real Time Clock */
325#define INT_SSPINT 11 /* Synchronous Serial Port */
326#define INT_UARTINT0 12 /* UART 0 on development chip */
327#define INT_UARTINT1 13 /* UART 1 on development chip */
328#define INT_UARTINT2 14 /* UART 2 on development chip */
329#define INT_SCIINT 15 /* Smart Card Interface */
330#define INT_CLCDINT 16 /* CLCD controller */
331#define INT_DMAINT 17 /* DMA controller */
332#define INT_PWRFAILINT 18 /* Power failure */
333#define INT_MBXINT 19 /* Graphics processor */
334#define INT_GNDINT 20 /* Reserved */
335 /* External interrupt signals from logic tiles or secondary controller */
336#define INT_VICSOURCE21 21 /* Disk on Chip */
337#define INT_VICSOURCE22 22 /* MCI0A */
338#define INT_VICSOURCE23 23 /* MCI1A */
339#define INT_VICSOURCE24 24 /* AACI */
340#define INT_VICSOURCE25 25 /* Ethernet */
341#define INT_VICSOURCE26 26 /* USB */
342#define INT_VICSOURCE27 27 /* PCI 0 */
343#define INT_VICSOURCE28 28 /* PCI 1 */
344#define INT_VICSOURCE29 29 /* PCI 2 */
345#define INT_VICSOURCE30 30 /* PCI 3 */
346#define INT_VICSOURCE31 31 /* SIC source */
347
348/*
349 * Interrupt bit positions
350 *
351 */
352#define INTMASK_WDOGINT (1 << INT_WDOGINT)
353#define INTMASK_SOFTINT (1 << INT_SOFTINT)
354#define INTMASK_COMMRx (1 << INT_COMMRx)
355#define INTMASK_COMMTx (1 << INT_COMMTx)
356#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
357#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
358#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
359#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
360#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
361#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
362#define INTMASK_RTCINT (1 << INT_RTCINT)
363#define INTMASK_SSPINT (1 << INT_SSPINT)
364#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
365#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
366#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
367#define INTMASK_SCIINT (1 << INT_SCIINT)
368#define INTMASK_CLCDINT (1 << INT_CLCDINT)
369#define INTMASK_DMAINT (1 << INT_DMAINT)
370#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
371#define INTMASK_MBXINT (1 << INT_MBXINT)
372#define INTMASK_GNDINT (1 << INT_GNDINT)
373#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
374#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
375#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
376#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
377#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
378#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
379#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
380#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
381#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
382#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
383#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
384
385
386#define VERSATILE_SC_VALID_INT 0x003FFFFF
387
388#define MAXIRQNUM 31
389#define MAXFIQNUM 31
390#define MAXSWINUM 31
391
392/* ------------------------------------------------------------------------
393 * Interrupts - bit assignment (secondary)
394 * ------------------------------------------------------------------------
395 */
396#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
397#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
398#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
399#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
400#define SIC_INT_SCI3 5 /* Smart Card interface */
401#define SIC_INT_UART3 6 /* UART 3 empty or data available */
402#define SIC_INT_CLCD 7 /* Character LCD */
403#define SIC_INT_TOUCH 8 /* Touchscreen */
404#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
405 /* 10:20 - reserved */
406#define SIC_INT_DoC 21 /* Disk on Chip memory controller */
407#define SIC_INT_MMCI0A 22 /* MMC 0A */
408#define SIC_INT_MMCI1A 23 /* MMC 1A */
409#define SIC_INT_AACI 24 /* Audio Codec */
410#define SIC_INT_ETH 25 /* Ethernet controller */
411#define SIC_INT_USB 26 /* USB controller */
412#define SIC_INT_PCI0 27
413#define SIC_INT_PCI1 28
414#define SIC_INT_PCI2 29
415#define SIC_INT_PCI3 30
416
417
418#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
419#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
420#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
421#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
422#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
423#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
424#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
425#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
426#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
427#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
428#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
429#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
430#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
431#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
432#define SIC_INTMASK_USB (1 << SIC_INT_USB)
433#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
434#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
435#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
436#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
437/*
438 * Application Flash
439 *
440 */
441#define FLASH_BASE VERSATILE_FLASH_BASE
442#define FLASH_SIZE VERSATILE_FLASH_SIZE
443#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
444#define FLASH_BLOCK_SIZE SZ_128K
445
446/*
447 * Boot Flash
448 *
449 */
450#define EPROM_BASE VERSATILE_BOOT_ROM_HI
451#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE
452#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
453
454/*
455 * Clean base - dummy
456 *
457 */
458#define CLEAN_BASE EPROM_BASE
459
460/*
461 * System controller bit assignment
462 */
463#define VERSATILE_REFCLK 0
464#define VERSATILE_TIMCLK 1
465
466#define VERSATILE_TIMER1_EnSel 15
467#define VERSATILE_TIMER2_EnSel 17
468#define VERSATILE_TIMER3_EnSel 19
469#define VERSATILE_TIMER4_EnSel 21
470
471
472#define MAX_TIMER 2
473#define MAX_PERIOD 699050
474#define TICKS_PER_uSEC 1
475
476/*
477 * These are useconds NOT ticks.
478 *
479 */
480#define mSEC_1 1000
481#define mSEC_5 (mSEC_1 * 5)
482#define mSEC_10 (mSEC_1 * 10)
483#define mSEC_25 (mSEC_1 * 25)
484#define SEC_1 (mSEC_1 * 1000)
485
486#define VERSATILE_CSR_BASE 0x10000000
487#define VERSATILE_CSR_SIZE 0x10000000
488
489#ifdef CONFIG_MACH_VERSATILE_AB
490/*
491 * IB2 Versatile/AB expansion board definitions
492 */
493#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE
494#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000)
495
496/* VICINTSOURCE27 */
497#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000)
498#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0)
499#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4)
500
501#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
502#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0)
503#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4)
504#endif
505
506#endif
507
508/* END */