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1/* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 *
30 */
31
32#ifndef _I830_DRV_H_
33#define _I830_DRV_H_
34
35/* General customization:
36 */
37
38#define DRIVER_AUTHOR "VA Linux Systems Inc."
39
40#define DRIVER_NAME "i830"
41#define DRIVER_DESC "Intel 830M"
42#define DRIVER_DATE "20021108"
43
44/* Interface history:
45 *
46 * 1.1: Original.
47 * 1.2: ?
48 * 1.3: New irq emit/wait ioctls.
49 * New pageflip ioctl.
50 * New getparam ioctl.
51 * State for texunits 3&4 in sarea.
52 * New (alternative) layout for texture state.
53 */
54#define DRIVER_MAJOR 1
55#define DRIVER_MINOR 3
56#define DRIVER_PATCHLEVEL 2
57
58/* Driver will work either way: IRQ's save cpu time when waiting for
59 * the card, but are subject to subtle interactions between bios,
60 * hardware and the driver.
61 */
62/* XXX: Add vblank support? */
63#define USE_IRQS 0
64
65typedef struct drm_i830_buf_priv {
66 u32 *in_use;
67 int my_use_idx;
68 int currently_mapped;
69 void __user *virtual;
70 void *kernel_virtual;
71} drm_i830_buf_priv_t;
72
73typedef struct _drm_i830_ring_buffer {
74 int tail_mask;
75 unsigned long Start;
76 unsigned long End;
77 unsigned long Size;
78 u8 *virtual_start;
79 int head;
80 int tail;
81 int space;
82} drm_i830_ring_buffer_t;
83
84typedef struct drm_i830_private {
85 drm_map_t *sarea_map;
86 drm_map_t *mmio_map;
87
88 drm_i830_sarea_t *sarea_priv;
89 drm_i830_ring_buffer_t ring;
90
91 void *hw_status_page;
92 unsigned long counter;
93
94 dma_addr_t dma_status_page;
95
96 drm_buf_t *mmap_buffer;
97
98 u32 front_di1, back_di1, zi1;
99
100 int back_offset;
101 int depth_offset;
102 int front_offset;
103 int w, h;
104 int pitch;
105 int back_pitch;
106 int depth_pitch;
107 unsigned int cpp;
108
109 int do_boxes;
110 int dma_used;
111
112 int current_page;
113 int page_flipping;
114
115 wait_queue_head_t irq_queue;
116 atomic_t irq_received;
117 atomic_t irq_emitted;
118
119 int use_mi_batchbuffer_start;
120
121} drm_i830_private_t;
122
123extern drm_ioctl_desc_t i830_ioctls[];
124extern int i830_max_ioctl;
125
126/* i830_irq.c */
127extern int i830_irq_emit(struct inode *inode, struct file *filp,
128 unsigned int cmd, unsigned long arg);
129extern int i830_irq_wait(struct inode *inode, struct file *filp,
130 unsigned int cmd, unsigned long arg);
131
132extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS);
133extern void i830_driver_irq_preinstall(drm_device_t * dev);
134extern void i830_driver_irq_postinstall(drm_device_t * dev);
135extern void i830_driver_irq_uninstall(drm_device_t * dev);
136extern int i830_driver_load(struct drm_device *, unsigned long flags);
137extern void i830_driver_preclose(drm_device_t * dev, DRMFILE filp);
138extern void i830_driver_lastclose(drm_device_t * dev);
139extern void i830_driver_reclaim_buffers_locked(drm_device_t * dev,
140 struct file *filp);
141extern int i830_driver_dma_quiescent(drm_device_t * dev);
142extern int i830_driver_device_is_agp(drm_device_t * dev);
143
144#define I830_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
145#define I830_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
146#define I830_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
147#define I830_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
148
149#define I830_VERBOSE 0
150
151#define RING_LOCALS unsigned int outring, ringmask, outcount; \
152 volatile char *virt;
153
154#define BEGIN_LP_RING(n) do { \
155 if (I830_VERBOSE) \
156 printk("BEGIN_LP_RING(%d) in %s\n", \
157 n, __FUNCTION__); \
158 if (dev_priv->ring.space < n*4) \
159 i830_wait_ring(dev, n*4, __FUNCTION__); \
160 outcount = 0; \
161 outring = dev_priv->ring.tail; \
162 ringmask = dev_priv->ring.tail_mask; \
163 virt = dev_priv->ring.virtual_start; \
164} while (0)
165
166#define OUT_RING(n) do { \
167 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
168 *(volatile unsigned int *)(virt + outring) = n; \
169 outcount++; \
170 outring += 4; \
171 outring &= ringmask; \
172} while (0)
173
174#define ADVANCE_LP_RING() do { \
175 if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \
176 dev_priv->ring.tail = outring; \
177 dev_priv->ring.space -= outcount * 4; \
178 I830_WRITE(LP_RING + RING_TAIL, outring); \
179} while(0)
180
181extern int i830_wait_ring(drm_device_t * dev, int n, const char *caller);
182
183#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
184#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
185#define CMD_REPORT_HEAD (7<<23)
186#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
187#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
188
189#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
190#define LOAD_TEXTURE_MAP0 (1<<11)
191
192#define INST_PARSER_CLIENT 0x00000000
193#define INST_OP_FLUSH 0x02000000
194#define INST_FLUSH_MAP_CACHE 0x00000001
195
196#define BB1_START_ADDR_MASK (~0x7)
197#define BB1_PROTECTED (1<<0)
198#define BB1_UNPROTECTED (0<<0)
199#define BB2_END_ADDR_MASK (~0x7)
200
201#define I830REG_HWSTAM 0x02098
202#define I830REG_INT_IDENTITY_R 0x020a4
203#define I830REG_INT_MASK_R 0x020a8
204#define I830REG_INT_ENABLE_R 0x020a0
205
206#define I830_IRQ_RESERVED ((1<<13)|(3<<2))
207
208#define LP_RING 0x2030
209#define HP_RING 0x2040
210#define RING_TAIL 0x00
211#define TAIL_ADDR 0x001FFFF8
212#define RING_HEAD 0x04
213#define HEAD_WRAP_COUNT 0xFFE00000
214#define HEAD_WRAP_ONE 0x00200000
215#define HEAD_ADDR 0x001FFFFC
216#define RING_START 0x08
217#define START_ADDR 0x0xFFFFF000
218#define RING_LEN 0x0C
219#define RING_NR_PAGES 0x001FF000
220#define RING_REPORT_MASK 0x00000006
221#define RING_REPORT_64K 0x00000002
222#define RING_REPORT_128K 0x00000004
223#define RING_NO_REPORT 0x00000000
224#define RING_VALID_MASK 0x00000001
225#define RING_VALID 0x00000001
226#define RING_INVALID 0x00000000
227
228#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
229#define SC_UPDATE_SCISSOR (0x1<<1)
230#define SC_ENABLE_MASK (0x1<<0)
231#define SC_ENABLE (0x1<<0)
232
233#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
234#define SCI_YMIN_MASK (0xffff<<16)
235#define SCI_XMIN_MASK (0xffff<<0)
236#define SCI_YMAX_MASK (0xffff<<16)
237#define SCI_XMAX_MASK (0xffff<<0)
238
239#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
240#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
241#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
242#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
243#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
244#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
245#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
246#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
247
248#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
249
250#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
251#define ASYNC_FLIP (1<<22)
252
253#define CMD_3D (0x3<<29)
254#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16))
255#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
256
257#define BR00_BITBLT_CLIENT 0x40000000
258#define BR00_OP_COLOR_BLT 0x10000000
259#define BR00_OP_SRC_COPY_BLT 0x10C00000
260#define BR13_SOLID_PATTERN 0x80000000
261
262#define BUF_3D_ID_COLOR_BACK (0x3<<24)
263#define BUF_3D_ID_DEPTH (0x7<<24)
264#define BUF_3D_USE_FENCE (1<<23)
265#define BUF_3D_PITCH(x) (((x)/4)<<2)
266
267#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
268#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
269#define MAP_PALETTE_BOTH (1<<11)
270
271#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4)
272#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
273#define XY_COLOR_BLT_WRITE_RGB (1<<20)
274
275#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
276#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
277#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
278
279#define MI_BATCH_BUFFER ((0x30<<23)|1)
280#define MI_BATCH_BUFFER_START (0x31<<23)
281#define MI_BATCH_BUFFER_END (0xA<<23)
282#define MI_BATCH_NON_SECURE (1)
283
284#define MI_WAIT_FOR_EVENT ((0x3<<23))
285#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
286#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
287
288#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
289
290#endif