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1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/config.h>
21#include <linux/threads.h>
22#include <asm/percpu.h>
23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 char fdiv_bug;
65 char f00f_bug;
66 char coma_bug;
67 char pad0;
68 int x86_power;
69 unsigned long loops_per_jiffy;
70 unsigned char x86_max_cores; /* cpuid returned max cores value */
71 unsigned char booted_cores; /* number of cores as seen by OS */
72 unsigned char apicid;
73} __attribute__((__aligned__(SMP_CACHE_BYTES)));
74
75#define X86_VENDOR_INTEL 0
76#define X86_VENDOR_CYRIX 1
77#define X86_VENDOR_AMD 2
78#define X86_VENDOR_UMC 3
79#define X86_VENDOR_NEXGEN 4
80#define X86_VENDOR_CENTAUR 5
81#define X86_VENDOR_RISE 6
82#define X86_VENDOR_TRANSMETA 7
83#define X86_VENDOR_NSC 8
84#define X86_VENDOR_NUM 9
85#define X86_VENDOR_UNKNOWN 0xff
86
87/*
88 * capabilities of CPUs
89 */
90
91extern struct cpuinfo_x86 boot_cpu_data;
92extern struct cpuinfo_x86 new_cpu_data;
93extern struct tss_struct doublefault_tss;
94DECLARE_PER_CPU(struct tss_struct, init_tss);
95
96#ifdef CONFIG_SMP
97extern struct cpuinfo_x86 cpu_data[];
98#define current_cpu_data cpu_data[smp_processor_id()]
99#else
100#define cpu_data (&boot_cpu_data)
101#define current_cpu_data boot_cpu_data
102#endif
103
104extern int phys_proc_id[NR_CPUS];
105extern int cpu_core_id[NR_CPUS];
106extern char ignore_fpu_irq;
107
108extern void identify_cpu(struct cpuinfo_x86 *);
109extern void print_cpu_info(struct cpuinfo_x86 *);
110extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
111
112#ifdef CONFIG_X86_HT
113extern void detect_ht(struct cpuinfo_x86 *c);
114#else
115static inline void detect_ht(struct cpuinfo_x86 *c) {}
116#endif
117
118/*
119 * EFLAGS bits
120 */
121#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
122#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
123#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
124#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
125#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
126#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
127#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
128#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
129#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
130#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
131#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
132#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
133#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
134#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
135#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
136#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
137#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
138
139/*
140 * Generic CPUID function
141 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
142 * resulting in stale register contents being returned.
143 */
144static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
145{
146 __asm__("cpuid"
147 : "=a" (*eax),
148 "=b" (*ebx),
149 "=c" (*ecx),
150 "=d" (*edx)
151 : "0" (op), "c"(0));
152}
153
154/* Some CPUID calls want 'count' to be placed in ecx */
155static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
156 int *edx)
157{
158 __asm__("cpuid"
159 : "=a" (*eax),
160 "=b" (*ebx),
161 "=c" (*ecx),
162 "=d" (*edx)
163 : "0" (op), "c" (count));
164}
165
166/*
167 * CPUID functions returning a single datum
168 */
169static inline unsigned int cpuid_eax(unsigned int op)
170{
171 unsigned int eax;
172
173 __asm__("cpuid"
174 : "=a" (eax)
175 : "0" (op)
176 : "bx", "cx", "dx");
177 return eax;
178}
179static inline unsigned int cpuid_ebx(unsigned int op)
180{
181 unsigned int eax, ebx;
182
183 __asm__("cpuid"
184 : "=a" (eax), "=b" (ebx)
185 : "0" (op)
186 : "cx", "dx" );
187 return ebx;
188}
189static inline unsigned int cpuid_ecx(unsigned int op)
190{
191 unsigned int eax, ecx;
192
193 __asm__("cpuid"
194 : "=a" (eax), "=c" (ecx)
195 : "0" (op)
196 : "bx", "dx" );
197 return ecx;
198}
199static inline unsigned int cpuid_edx(unsigned int op)
200{
201 unsigned int eax, edx;
202
203 __asm__("cpuid"
204 : "=a" (eax), "=d" (edx)
205 : "0" (op)
206 : "bx", "cx");
207 return edx;
208}
209
210#define load_cr3(pgdir) write_cr3(__pa(pgdir))
211
212/*
213 * Intel CPU features in CR4
214 */
215#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
216#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
217#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
218#define X86_CR4_DE 0x0008 /* enable debugging extensions */
219#define X86_CR4_PSE 0x0010 /* enable page size extensions */
220#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
221#define X86_CR4_MCE 0x0040 /* Machine check enable */
222#define X86_CR4_PGE 0x0080 /* enable global pages */
223#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
224#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
225#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
226
227/*
228 * Save the cr4 feature set we're using (ie
229 * Pentium 4MB enable and PPro Global page
230 * enable), so that any CPU's that boot up
231 * after us can get the correct flags.
232 */
233extern unsigned long mmu_cr4_features;
234
235static inline void set_in_cr4 (unsigned long mask)
236{
237 unsigned cr4;
238 mmu_cr4_features |= mask;
239 cr4 = read_cr4();
240 cr4 |= mask;
241 write_cr4(cr4);
242}
243
244static inline void clear_in_cr4 (unsigned long mask)
245{
246 unsigned cr4;
247 mmu_cr4_features &= ~mask;
248 cr4 = read_cr4();
249 cr4 &= ~mask;
250 write_cr4(cr4);
251}
252
253/*
254 * NSC/Cyrix CPU configuration register indexes
255 */
256
257#define CX86_PCR0 0x20
258#define CX86_GCR 0xb8
259#define CX86_CCR0 0xc0
260#define CX86_CCR1 0xc1
261#define CX86_CCR2 0xc2
262#define CX86_CCR3 0xc3
263#define CX86_CCR4 0xe8
264#define CX86_CCR5 0xe9
265#define CX86_CCR6 0xea
266#define CX86_CCR7 0xeb
267#define CX86_PCR1 0xf0
268#define CX86_DIR0 0xfe
269#define CX86_DIR1 0xff
270#define CX86_ARR_BASE 0xc4
271#define CX86_RCR_BASE 0xdc
272
273/*
274 * NSC/Cyrix CPU indexed register access macros
275 */
276
277#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
278
279#define setCx86(reg, data) do { \
280 outb((reg), 0x22); \
281 outb((data), 0x23); \
282} while (0)
283
284/* Stop speculative execution */
285static inline void sync_core(void)
286{
287 int tmp;
288 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
289}
290
291static inline void __monitor(const void *eax, unsigned long ecx,
292 unsigned long edx)
293{
294 /* "monitor %eax,%ecx,%edx;" */
295 asm volatile(
296 ".byte 0x0f,0x01,0xc8;"
297 : :"a" (eax), "c" (ecx), "d"(edx));
298}
299
300static inline void __mwait(unsigned long eax, unsigned long ecx)
301{
302 /* "mwait %eax,%ecx;" */
303 asm volatile(
304 ".byte 0x0f,0x01,0xc9;"
305 : :"a" (eax), "c" (ecx));
306}
307
308/* from system description table in BIOS. Mostly for MCA use, but
309others may find it useful. */
310extern unsigned int machine_id;
311extern unsigned int machine_submodel_id;
312extern unsigned int BIOS_revision;
313extern unsigned int mca_pentium_flag;
314
315/* Boot loader type from the setup header */
316extern int bootloader_type;
317
318/*
319 * User space process size: 3GB (default).
320 */
321#define TASK_SIZE (PAGE_OFFSET)
322
323/* This decides where the kernel will search for a free chunk of vm
324 * space during mmap's.
325 */
326#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
327
328#define HAVE_ARCH_PICK_MMAP_LAYOUT
329
330/*
331 * Size of io_bitmap.
332 */
333#define IO_BITMAP_BITS 65536
334#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
335#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
336#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
337#define INVALID_IO_BITMAP_OFFSET 0x8000
338#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
339
340struct i387_fsave_struct {
341 long cwd;
342 long swd;
343 long twd;
344 long fip;
345 long fcs;
346 long foo;
347 long fos;
348 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
349 long status; /* software status information */
350};
351
352struct i387_fxsave_struct {
353 unsigned short cwd;
354 unsigned short swd;
355 unsigned short twd;
356 unsigned short fop;
357 long fip;
358 long fcs;
359 long foo;
360 long fos;
361 long mxcsr;
362 long mxcsr_mask;
363 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
364 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
365 long padding[56];
366} __attribute__ ((aligned (16)));
367
368struct i387_soft_struct {
369 long cwd;
370 long swd;
371 long twd;
372 long fip;
373 long fcs;
374 long foo;
375 long fos;
376 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
377 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
378 struct info *info;
379 unsigned long entry_eip;
380};
381
382union i387_union {
383 struct i387_fsave_struct fsave;
384 struct i387_fxsave_struct fxsave;
385 struct i387_soft_struct soft;
386};
387
388typedef struct {
389 unsigned long seg;
390} mm_segment_t;
391
392struct thread_struct;
393
394struct tss_struct {
395 unsigned short back_link,__blh;
396 unsigned long esp0;
397 unsigned short ss0,__ss0h;
398 unsigned long esp1;
399 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
400 unsigned long esp2;
401 unsigned short ss2,__ss2h;
402 unsigned long __cr3;
403 unsigned long eip;
404 unsigned long eflags;
405 unsigned long eax,ecx,edx,ebx;
406 unsigned long esp;
407 unsigned long ebp;
408 unsigned long esi;
409 unsigned long edi;
410 unsigned short es, __esh;
411 unsigned short cs, __csh;
412 unsigned short ss, __ssh;
413 unsigned short ds, __dsh;
414 unsigned short fs, __fsh;
415 unsigned short gs, __gsh;
416 unsigned short ldt, __ldth;
417 unsigned short trace, io_bitmap_base;
418 /*
419 * The extra 1 is there because the CPU will access an
420 * additional byte beyond the end of the IO permission
421 * bitmap. The extra byte must be all 1 bits, and must
422 * be within the limit.
423 */
424 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
425 /*
426 * Cache the current maximum and the last task that used the bitmap:
427 */
428 unsigned long io_bitmap_max;
429 struct thread_struct *io_bitmap_owner;
430 /*
431 * pads the TSS to be cacheline-aligned (size is 0x100)
432 */
433 unsigned long __cacheline_filler[35];
434 /*
435 * .. and then another 0x100 bytes for emergency kernel stack
436 */
437 unsigned long stack[64];
438} __attribute__((packed));
439
440#define ARCH_MIN_TASKALIGN 16
441
442struct thread_struct {
443/* cached TLS descriptors. */
444 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
445 unsigned long esp0;
446 unsigned long sysenter_cs;
447 unsigned long eip;
448 unsigned long esp;
449 unsigned long fs;
450 unsigned long gs;
451/* Hardware debugging registers */
452 unsigned long debugreg[8]; /* %%db0-7 debug registers */
453/* fault info */
454 unsigned long cr2, trap_no, error_code;
455/* floating point info */
456 union i387_union i387;
457/* virtual 86 mode info */
458 struct vm86_struct __user * vm86_info;
459 unsigned long screen_bitmap;
460 unsigned long v86flags, v86mask, saved_esp0;
461 unsigned int saved_fs, saved_gs;
462/* IO permissions */
463 unsigned long *io_bitmap_ptr;
464 unsigned long iopl;
465/* max allowed port in the bitmap, in bytes: */
466 unsigned long io_bitmap_max;
467};
468
469#define INIT_THREAD { \
470 .vm86_info = NULL, \
471 .sysenter_cs = __KERNEL_CS, \
472 .io_bitmap_ptr = NULL, \
473}
474
475/*
476 * Note that the .io_bitmap member must be extra-big. This is because
477 * the CPU will access an additional byte beyond the end of the IO
478 * permission bitmap. The extra byte must be all 1 bits, and must
479 * be within the limit.
480 */
481#define INIT_TSS { \
482 .esp0 = sizeof(init_stack) + (long)&init_stack, \
483 .ss0 = __KERNEL_DS, \
484 .ss1 = __KERNEL_CS, \
485 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
486 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
487}
488
489static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
490{
491 tss->esp0 = thread->esp0;
492 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
493 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
494 tss->ss1 = thread->sysenter_cs;
495 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
496 }
497}
498
499#define start_thread(regs, new_eip, new_esp) do { \
500 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
501 set_fs(USER_DS); \
502 regs->xds = __USER_DS; \
503 regs->xes = __USER_DS; \
504 regs->xss = __USER_DS; \
505 regs->xcs = __USER_CS; \
506 regs->eip = new_eip; \
507 regs->esp = new_esp; \
508} while (0)
509
510/*
511 * These special macros can be used to get or set a debugging register
512 */
513#define get_debugreg(var, register) \
514 __asm__("movl %%db" #register ", %0" \
515 :"=r" (var))
516#define set_debugreg(value, register) \
517 __asm__("movl %0,%%db" #register \
518 : /* no output */ \
519 :"r" (value))
520
521/*
522 * Set IOPL bits in EFLAGS from given mask
523 */
524static inline void set_iopl_mask(unsigned mask)
525{
526 unsigned int reg;
527 __asm__ __volatile__ ("pushfl;"
528 "popl %0;"
529 "andl %1, %0;"
530 "orl %2, %0;"
531 "pushl %0;"
532 "popfl"
533 : "=&r" (reg)
534 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
535}
536
537/* Forward declaration, a strange C thing */
538struct task_struct;
539struct mm_struct;
540
541/* Free all resources held by a thread. */
542extern void release_thread(struct task_struct *);
543
544/* Prepare to copy thread state - unlazy all lazy status */
545extern void prepare_to_copy(struct task_struct *tsk);
546
547/*
548 * create a kernel thread without removing it from tasklists
549 */
550extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
551
552extern unsigned long thread_saved_pc(struct task_struct *tsk);
553void show_trace(struct task_struct *task, unsigned long *stack);
554
555unsigned long get_wchan(struct task_struct *p);
556
557#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
558#define KSTK_TOP(info) \
559({ \
560 unsigned long *__ptr = (unsigned long *)(info); \
561 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
562})
563
564/*
565 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
566 * This is necessary to guarantee that the entire "struct pt_regs"
567 * is accessable even if the CPU haven't stored the SS/ESP registers
568 * on the stack (interrupt gate does not save these registers
569 * when switching to the same priv ring).
570 * Therefore beware: accessing the xss/esp fields of the
571 * "struct pt_regs" is possible, but they may contain the
572 * completely wrong values.
573 */
574#define task_pt_regs(task) \
575({ \
576 struct pt_regs *__regs__; \
577 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
578 __regs__ - 1; \
579})
580
581#define KSTK_EIP(task) (task_pt_regs(task)->eip)
582#define KSTK_ESP(task) (task_pt_regs(task)->esp)
583
584
585struct microcode_header {
586 unsigned int hdrver;
587 unsigned int rev;
588 unsigned int date;
589 unsigned int sig;
590 unsigned int cksum;
591 unsigned int ldrver;
592 unsigned int pf;
593 unsigned int datasize;
594 unsigned int totalsize;
595 unsigned int reserved[3];
596};
597
598struct microcode {
599 struct microcode_header hdr;
600 unsigned int bits[0];
601};
602
603typedef struct microcode microcode_t;
604typedef struct microcode_header microcode_header_t;
605
606/* microcode format is extended from prescott processors */
607struct extended_signature {
608 unsigned int sig;
609 unsigned int pf;
610 unsigned int cksum;
611};
612
613struct extended_sigtable {
614 unsigned int count;
615 unsigned int cksum;
616 unsigned int reserved[3];
617 struct extended_signature sigs[0];
618};
619/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
620#define MICROCODE_IOCFREE _IO('6',0)
621
622/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
623static inline void rep_nop(void)
624{
625 __asm__ __volatile__("rep;nop": : :"memory");
626}
627
628#define cpu_relax() rep_nop()
629
630/* generic versions from gas */
631#define GENERIC_NOP1 ".byte 0x90\n"
632#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
633#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
634#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
635#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
636#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
637#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
638#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
639
640/* Opteron nops */
641#define K8_NOP1 GENERIC_NOP1
642#define K8_NOP2 ".byte 0x66,0x90\n"
643#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
644#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
645#define K8_NOP5 K8_NOP3 K8_NOP2
646#define K8_NOP6 K8_NOP3 K8_NOP3
647#define K8_NOP7 K8_NOP4 K8_NOP3
648#define K8_NOP8 K8_NOP4 K8_NOP4
649
650/* K7 nops */
651/* uses eax dependencies (arbitary choice) */
652#define K7_NOP1 GENERIC_NOP1
653#define K7_NOP2 ".byte 0x8b,0xc0\n"
654#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
655#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
656#define K7_NOP5 K7_NOP4 ASM_NOP1
657#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
658#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
659#define K7_NOP8 K7_NOP7 ASM_NOP1
660
661#ifdef CONFIG_MK8
662#define ASM_NOP1 K8_NOP1
663#define ASM_NOP2 K8_NOP2
664#define ASM_NOP3 K8_NOP3
665#define ASM_NOP4 K8_NOP4
666#define ASM_NOP5 K8_NOP5
667#define ASM_NOP6 K8_NOP6
668#define ASM_NOP7 K8_NOP7
669#define ASM_NOP8 K8_NOP8
670#elif defined(CONFIG_MK7)
671#define ASM_NOP1 K7_NOP1
672#define ASM_NOP2 K7_NOP2
673#define ASM_NOP3 K7_NOP3
674#define ASM_NOP4 K7_NOP4
675#define ASM_NOP5 K7_NOP5
676#define ASM_NOP6 K7_NOP6
677#define ASM_NOP7 K7_NOP7
678#define ASM_NOP8 K7_NOP8
679#else
680#define ASM_NOP1 GENERIC_NOP1
681#define ASM_NOP2 GENERIC_NOP2
682#define ASM_NOP3 GENERIC_NOP3
683#define ASM_NOP4 GENERIC_NOP4
684#define ASM_NOP5 GENERIC_NOP5
685#define ASM_NOP6 GENERIC_NOP6
686#define ASM_NOP7 GENERIC_NOP7
687#define ASM_NOP8 GENERIC_NOP8
688#endif
689
690#define ASM_NOP_MAX 8
691
692/* Prefetch instructions for Pentium III and AMD Athlon */
693/* It's not worth to care about 3dnow! prefetches for the K6
694 because they are microcoded there and very slow.
695 However we don't do prefetches for pre XP Athlons currently
696 That should be fixed. */
697#define ARCH_HAS_PREFETCH
698static inline void prefetch(const void *x)
699{
700 alternative_input(ASM_NOP4,
701 "prefetchnta (%1)",
702 X86_FEATURE_XMM,
703 "r" (x));
704}
705
706#define ARCH_HAS_PREFETCH
707#define ARCH_HAS_PREFETCHW
708#define ARCH_HAS_SPINLOCK_PREFETCH
709
710/* 3dnow! prefetch to get an exclusive cache line. Useful for
711 spinlocks to avoid one state transition in the cache coherency protocol. */
712static inline void prefetchw(const void *x)
713{
714 alternative_input(ASM_NOP4,
715 "prefetchw (%1)",
716 X86_FEATURE_3DNOW,
717 "r" (x));
718}
719#define spin_lock_prefetch(x) prefetchw(x)
720
721extern void select_idle_routine(const struct cpuinfo_x86 *c);
722
723#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
724
725extern unsigned long boot_option_idle_override;
726extern void enable_sep_cpu(void);
727extern int sysenter_setup(void);
728
729#ifdef CONFIG_MTRR
730extern void mtrr_ap_init(void);
731extern void mtrr_bp_init(void);
732#else
733#define mtrr_ap_init() do {} while (0)
734#define mtrr_bp_init() do {} while (0)
735#endif
736
737#ifdef CONFIG_X86_MCE
738extern void mcheck_init(struct cpuinfo_x86 *c);
739#else
740#define mcheck_init(c) do {} while(0)
741#endif
742
743#endif /* __ASM_I386_PROCESSOR_H */