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linux
1# drivers/mtd/chips/Kconfig
2# $Id: Kconfig,v 1.18 2005/11/07 11:14:22 gleixner Exp $
3
4menu "RAM/ROM/Flash chip drivers"
5 depends on MTD!=n
6
7config MTD_CFI
8 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
9 depends on MTD
10 select MTD_GEN_PROBE
11 help
12 The Common Flash Interface specification was developed by Intel,
13 AMD and other flash manufactures that provides a universal method
14 for probing the capabilities of flash devices. If you wish to
15 support any device that is CFI-compliant, you need to enable this
16 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
17 for more information on CFI.
18
19config MTD_JEDECPROBE
20 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
21 depends on MTD
22 select MTD_GEN_PROBE
23 help
24 This option enables JEDEC-style probing of flash chips which are not
25 compatible with the Common Flash Interface, but will use the common
26 CFI-targetted flash drivers for any chips which are identified which
27 are in fact compatible in all but the probe method. This actually
28 covers most AMD/Fujitsu-compatible chips, and will shortly cover also
29 non-CFI Intel chips (that code is in MTD CVS and should shortly be sent
30 for inclusion in Linus' tree)
31
32config MTD_GEN_PROBE
33 tristate
34 select OBSOLETE_INTERMODULE
35
36config MTD_CFI_ADV_OPTIONS
37 bool "Flash chip driver advanced configuration options"
38 depends on MTD_GEN_PROBE
39 help
40 If you need to specify a specific endianness for access to flash
41 chips, or if you wish to reduce the size of the kernel by including
42 support for only specific arrangements of flash chips, say 'Y'. This
43 option does not directly affect the code, but will enable other
44 configuration options which allow you to do so.
45
46 If unsure, say 'N'.
47
48choice
49 prompt "Flash cmd/query data swapping"
50 depends on MTD_CFI_ADV_OPTIONS
51 default MTD_CFI_NOSWAP
52
53config MTD_CFI_NOSWAP
54 bool "NO"
55 ---help---
56 This option defines the way in which the CPU attempts to arrange
57 data bits when writing the 'magic' commands to the chips. Saying
58 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
59 enabled, means that the CPU will not do any swapping; the chips
60 are expected to be wired to the CPU in 'host-endian' form.
61 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
62 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
63
64 If you have a LART, on which the data (and address) lines were
65 connected in a fashion which ensured that the nets were as short
66 as possible, resulting in a bit-shuffling which seems utterly
67 random to the untrained eye, you need the LART_ENDIAN_BYTE option.
68
69 Yes, there really exists something sicker than PDP-endian :)
70
71config MTD_CFI_BE_BYTE_SWAP
72 bool "BIG_ENDIAN_BYTE"
73
74config MTD_CFI_LE_BYTE_SWAP
75 bool "LITTLE_ENDIAN_BYTE"
76
77endchoice
78
79config MTD_CFI_GEOMETRY
80 bool "Specific CFI Flash geometry selection"
81 depends on MTD_CFI_ADV_OPTIONS
82 help
83 This option does not affect the code directly, but will enable
84 some other configuration options which would allow you to reduce
85 the size of the kernel by including support for only certain
86 arrangements of CFI chips. If unsure, say 'N' and all options
87 which are supported by the current code will be enabled.
88
89config MTD_MAP_BANK_WIDTH_1
90 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
91 default y
92 help
93 If you wish to support CFI devices on a physical bus which is
94 8 bits wide, say 'Y'.
95
96config MTD_MAP_BANK_WIDTH_2
97 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
98 default y
99 help
100 If you wish to support CFI devices on a physical bus which is
101 16 bits wide, say 'Y'.
102
103config MTD_MAP_BANK_WIDTH_4
104 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
105 default y
106 help
107 If you wish to support CFI devices on a physical bus which is
108 32 bits wide, say 'Y'.
109
110config MTD_MAP_BANK_WIDTH_8
111 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
112 default n
113 help
114 If you wish to support CFI devices on a physical bus which is
115 64 bits wide, say 'Y'.
116
117config MTD_MAP_BANK_WIDTH_16
118 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
119 default n
120 help
121 If you wish to support CFI devices on a physical bus which is
122 128 bits wide, say 'Y'.
123
124config MTD_MAP_BANK_WIDTH_32
125 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
126 default n
127 help
128 If you wish to support CFI devices on a physical bus which is
129 256 bits wide, say 'Y'.
130
131config MTD_CFI_I1
132 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
133 default y
134 help
135 If your flash chips are not interleaved - i.e. you only have one
136 flash chip addressed by each bus cycle, then say 'Y'.
137
138config MTD_CFI_I2
139 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
140 default y
141 help
142 If your flash chips are interleaved in pairs - i.e. you have two
143 flash chips addressed by each bus cycle, then say 'Y'.
144
145config MTD_CFI_I4
146 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
147 default n
148 help
149 If your flash chips are interleaved in fours - i.e. you have four
150 flash chips addressed by each bus cycle, then say 'Y'.
151
152config MTD_CFI_I8
153 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
154 default n
155 help
156 If your flash chips are interleaved in eights - i.e. you have eight
157 flash chips addressed by each bus cycle, then say 'Y'.
158
159config MTD_OTP
160 bool "Protection Registers aka one-time programmable (OTP) bits"
161 depends on MTD_CFI_ADV_OPTIONS
162 default n
163 help
164 This enables support for reading, writing and locking so called
165 "Protection Registers" present on some flash chips.
166 A subset of them are pre-programmed at the factory with a
167 unique set of values. The rest is user-programmable.
168
169 The user-programmable Protection Registers contain one-time
170 programmable (OTP) bits; when programmed, register bits cannot be
171 erased. Each Protection Register can be accessed multiple times to
172 program individual bits, as long as the register remains unlocked.
173
174 Each Protection Register has an associated Lock Register bit. When a
175 Lock Register bit is programmed, the associated Protection Register
176 can only be read; it can no longer be programmed. Additionally,
177 because the Lock Register bits themselves are OTP, when programmed,
178 Lock Register bits cannot be erased. Therefore, when a Protection
179 Register is locked, it cannot be unlocked.
180
181 This feature should therefore be used with extreme care. Any mistake
182 in the programming of OTP bits will waste them.
183
184config MTD_CFI_INTELEXT
185 tristate "Support for Intel/Sharp flash chips"
186 depends on MTD_GEN_PROBE
187 select MTD_CFI_UTIL
188 help
189 The Common Flash Interface defines a number of different command
190 sets which a CFI-compliant chip may claim to implement. This code
191 provides support for one of those command sets, used on Intel
192 StrataFlash and other parts.
193
194config MTD_CFI_AMDSTD
195 tristate "Support for AMD/Fujitsu flash chips"
196 depends on MTD_GEN_PROBE
197 select MTD_CFI_UTIL
198 help
199 The Common Flash Interface defines a number of different command
200 sets which a CFI-compliant chip may claim to implement. This code
201 provides support for one of those command sets, used on chips
202 including the AMD Am29LV320.
203
204config MTD_CFI_AMDSTD_RETRY
205 int "Retry failed commands (erase/program)"
206 depends on MTD_CFI_AMDSTD
207 default "0"
208 help
209 Some chips, when attached to a shared bus, don't properly filter
210 bus traffic that is destined to other devices. This broken
211 behavior causes erase and program sequences to be aborted when
212 the sequences are mixed with traffic for other devices.
213
214 SST49LF040 (and related) chips are know to be broken.
215
216config MTD_CFI_AMDSTD_RETRY_MAX
217 int "Max retries of failed commands (erase/program)"
218 depends on MTD_CFI_AMDSTD_RETRY
219 default "0"
220 help
221 If you have an SST49LF040 (or related chip) then this value should
222 be set to at least 1. This can also be adjusted at driver load
223 time with the retry_cmd_max module parameter.
224
225config MTD_CFI_STAA
226 tristate "Support for ST (Advanced Architecture) flash chips"
227 depends on MTD_GEN_PROBE
228 select MTD_CFI_UTIL
229 help
230 The Common Flash Interface defines a number of different command
231 sets which a CFI-compliant chip may claim to implement. This code
232 provides support for one of those command sets.
233
234config MTD_CFI_UTIL
235 tristate
236
237config MTD_RAM
238 tristate "Support for RAM chips in bus mapping"
239 depends on MTD
240 help
241 This option enables basic support for RAM chips accessed through
242 a bus mapping driver.
243
244config MTD_ROM
245 tristate "Support for ROM chips in bus mapping"
246 depends on MTD
247 help
248 This option enables basic support for ROM chips accessed through
249 a bus mapping driver.
250
251config MTD_ABSENT
252 tristate "Support for absent chips in bus mapping"
253 depends on MTD
254 help
255 This option enables support for a dummy probing driver used to
256 allocated placeholder MTD devices on systems that have socketed
257 or removable media. Use of this driver as a fallback chip probe
258 preserves the expected registration order of MTD device nodes on
259 the system regardless of media presence. Device nodes created
260 with this driver will return -ENODEV upon access.
261
262config MTD_OBSOLETE_CHIPS
263 depends on MTD
264 bool "Older (theoretically obsoleted now) drivers for non-CFI chips"
265 help
266 This option does not enable any code directly, but will allow you to
267 select some other chip drivers which are now considered obsolete,
268 because the generic CONFIG_JEDECPROBE code above should now detect
269 the chips which are supported by these drivers, and allow the generic
270 CFI-compatible drivers to drive the chips. Say 'N' here unless you have
271 already tried the CONFIG_JEDECPROBE method and reported its failure
272 to the MTD mailing list at <linux-mtd@lists.infradead.org>
273
274config MTD_AMDSTD
275 tristate "AMD compatible flash chip support (non-CFI)"
276 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN
277 help
278 This option enables support for flash chips using AMD-compatible
279 commands, including some which are not CFI-compatible and hence
280 cannot be used with the CONFIG_MTD_CFI_AMDSTD option.
281
282 It also works on AMD compatible chips that do conform to CFI.
283
284config MTD_SHARP
285 tristate "pre-CFI Sharp chip support"
286 depends on MTD && MTD_OBSOLETE_CHIPS
287 help
288 This option enables support for flash chips using Sharp-compatible
289 commands, including some which are not CFI-compatible and hence
290 cannot be used with the CONFIG_MTD_CFI_INTELxxx options.
291
292config MTD_JEDEC
293 tristate "JEDEC device support"
294 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN
295 help
296 Enable older older JEDEC flash interface devices for self
297 programming flash. It is commonly used in older AMD chips. It is
298 only called JEDEC because the JEDEC association
299 <http://www.jedec.org/> distributes the identification codes for the
300 chips.
301
302config MTD_XIP
303 bool "XIP aware MTD support"
304 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
305 default y if XIP_KERNEL
306 help
307 This allows MTD support to work with flash memory which is also
308 used for XIP purposes. If you're not sure what this is all about
309 then say N.
310
311endmenu
312