tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/asm-parisc/cache.h
3 */
4
5#ifndef __ARCH_PARISC_CACHE_H
6#define __ARCH_PARISC_CACHE_H
7
8#include <linux/config.h>
9
10/*
11 * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
12 * 32-byte cachelines. The default configuration is not for SMP anyway,
13 * so if you're building for SMP, you should select the appropriate
14 * processor type. There is a potential livelock danger when running
15 * a machine with this value set too small, but it's more probable you'll
16 * just ruin performance.
17 */
18#ifdef CONFIG_PA20
19#define L1_CACHE_BYTES 64
20#define L1_CACHE_SHIFT 6
21#else
22#define L1_CACHE_BYTES 32
23#define L1_CACHE_SHIFT 5
24#endif
25
26#ifndef __ASSEMBLY__
27
28#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
29
30#define SMP_CACHE_BYTES L1_CACHE_BYTES
31
32extern void flush_data_cache_local(void *); /* flushes local data-cache only */
33extern void flush_instruction_cache_local(void *); /* flushes local code-cache only */
34#ifdef CONFIG_SMP
35extern void flush_data_cache(void); /* flushes data-cache only (all processors) */
36extern void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
37#else
38#define flush_data_cache() flush_data_cache_local(NULL)
39#define flush_instruction_cache() flush_instruction_cache_local(NULL)
40#endif
41
42extern void parisc_cache_init(void); /* initializes cache-flushing */
43extern void flush_all_caches(void); /* flush everything (tlb & cache) */
44extern int get_cache_info(char *);
45extern void flush_user_icache_range_asm(unsigned long, unsigned long);
46extern void flush_kernel_icache_range_asm(unsigned long, unsigned long);
47extern void flush_user_dcache_range_asm(unsigned long, unsigned long);
48extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
49extern void flush_kernel_dcache_page(void *);
50extern void flush_kernel_icache_page(void *);
51extern void disable_sr_hashing(void); /* turns off space register hashing */
52extern void disable_sr_hashing_asm(int); /* low level support for above */
53extern void free_sid(unsigned long);
54unsigned long alloc_sid(void);
55extern void flush_user_dcache_page(unsigned long);
56extern void flush_user_icache_page(unsigned long);
57
58struct seq_file;
59extern void show_cache_info(struct seq_file *m);
60
61extern int split_tlb;
62extern int dcache_stride;
63extern int icache_stride;
64extern struct pdc_cache_info cache_info;
65
66#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
67#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
68#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
69
70#endif /* ! __ASSEMBLY__ */
71
72/* Classes of processor wrt: disabling space register hashing */
73
74#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
75#define SRHASH_PCXL 1 /* pcxl */
76#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
77
78#endif