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Linux kernel mirror (for testing)
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linux
1#ifndef __ASM_SH_IRQ_H
2#define __ASM_SH_IRQ_H
3
4/*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <linux/config.h>
15#include <asm/machvec.h>
16#include <asm/ptrace.h> /* for pt_regs */
17
18#if defined(CONFIG_SH_HP6XX) || \
19 defined(CONFIG_SH_RTS7751R2D) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_HS7751RVOIP) || \
22 defined(CONFIG_SH_SH03) || \
23 defined(CONFIG_SH_R7780RP) || \
24 defined(CONFIG_SH_LANDISK)
25#include <asm/mach/ide.h>
26#endif
27
28#ifndef CONFIG_CPU_SUBTYPE_SH7780
29
30#define INTC_DMAC0_MSK 0
31
32#if defined(CONFIG_CPU_SH3)
33#define INTC_IPRA 0xfffffee2UL
34#define INTC_IPRB 0xfffffee4UL
35#elif defined(CONFIG_CPU_SH4)
36#define INTC_IPRA 0xffd00004UL
37#define INTC_IPRB 0xffd00008UL
38#define INTC_IPRC 0xffd0000cUL
39#define INTC_IPRD 0xffd00010UL
40#endif
41
42#ifdef CONFIG_IDE
43# ifndef IRQ_CFCARD
44# define IRQ_CFCARD 14
45# endif
46# ifndef IRQ_PCMCIA
47# define IRQ_PCMCIA 15
48# endif
49#endif
50
51#define TIMER_IRQ 16
52#define TIMER_IPR_ADDR INTC_IPRA
53#define TIMER_IPR_POS 3
54#define TIMER_PRIORITY 2
55
56#define TIMER1_IRQ 17
57#define TIMER1_IPR_ADDR INTC_IPRA
58#define TIMER1_IPR_POS 2
59#define TIMER1_PRIORITY 4
60
61#define RTC_IRQ 22
62#define RTC_IPR_ADDR INTC_IPRA
63#define RTC_IPR_POS 0
64#define RTC_PRIORITY TIMER_PRIORITY
65
66#if defined(CONFIG_CPU_SH3)
67#define DMTE0_IRQ 48
68#define DMTE1_IRQ 49
69#define DMTE2_IRQ 50
70#define DMTE3_IRQ 51
71#define DMA_IPR_ADDR INTC_IPRE
72#define DMA_IPR_POS 3
73#define DMA_PRIORITY 7
74#if defined(CONFIG_CPU_SUBTYPE_SH7300)
75/* TMU2 */
76#define TIMER2_IRQ 18
77#define TIMER2_IPR_ADDR INTC_IPRA
78#define TIMER2_IPR_POS 1
79#define TIMER2_PRIORITY 2
80
81/* WDT */
82#define WDT_IRQ 27
83#define WDT_IPR_ADDR INTC_IPRB
84#define WDT_IPR_POS 3
85#define WDT_PRIORITY 2
86
87/* SIM (SIM Card Module) */
88#define SIM_ERI_IRQ 23
89#define SIM_RXI_IRQ 24
90#define SIM_TXI_IRQ 25
91#define SIM_TEND_IRQ 26
92#define SIM_IPR_ADDR INTC_IPRB
93#define SIM_IPR_POS 1
94#define SIM_PRIORITY 2
95
96/* VIO (Video I/O) */
97#define VIO_IRQ 52
98#define VIO_IPR_ADDR INTC_IPRE
99#define VIO_IPR_POS 2
100#define VIO_PRIORITY 2
101
102/* MFI (Multi Functional Interface) */
103#define MFI_IRQ 56
104#define MFI_IPR_ADDR INTC_IPRE
105#define MFI_IPR_POS 1
106#define MFI_PRIORITY 2
107
108/* VPU (Video Processing Unit) */
109#define VPU_IRQ 60
110#define VPU_IPR_ADDR INTC_IPRE
111#define VPU_IPR_POS 0
112#define VPU_PRIORITY 2
113
114/* KEY (Key Scan Interface) */
115#define KEY_IRQ 79
116#define KEY_IPR_ADDR INTC_IPRF
117#define KEY_IPR_POS 3
118#define KEY_PRIORITY 2
119
120/* CMT (Compare Match Timer) */
121#define CMT_IRQ 104
122#define CMT_IPR_ADDR INTC_IPRF
123#define CMT_IPR_POS 0
124#define CMT_PRIORITY 2
125
126/* DMAC(1) */
127#define DMTE0_IRQ 48
128#define DMTE1_IRQ 49
129#define DMTE2_IRQ 50
130#define DMTE3_IRQ 51
131#define DMA1_IPR_ADDR INTC_IPRE
132#define DMA1_IPR_POS 3
133#define DMA1_PRIORITY 7
134
135/* DMAC(2) */
136#define DMTE4_IRQ 76
137#define DMTE5_IRQ 77
138#define DMA2_IPR_ADDR INTC_IPRF
139#define DMA2_IPR_POS 2
140#define DMA2_PRIORITY 7
141
142/* SIOF0 */
143#define SIOF0_IRQ 84
144#define SIOF0_IPR_ADDR INTC_IPRH
145#define SIOF0_IPR_POS 3
146#define SIOF0_PRIORITY 3
147
148/* FLCTL (Flash Memory Controller) */
149#define FLSTE_IRQ 92
150#define FLTEND_IRQ 93
151#define FLTRQ0_IRQ 94
152#define FLTRQ1_IRQ 95
153#define FLCTL_IPR_ADDR INTC_IPRH
154#define FLCTL_IPR_POS 1
155#define FLCTL_PRIORITY 3
156
157/* IIC (IIC Bus Interface) */
158#define IIC_ALI_IRQ 96
159#define IIC_TACKI_IRQ 97
160#define IIC_WAITI_IRQ 98
161#define IIC_DTEI_IRQ 99
162#define IIC_IPR_ADDR INTC_IPRH
163#define IIC_IPR_POS 0
164#define IIC_PRIORITY 3
165
166/* SIO0 */
167#define SIO0_IRQ 88
168#define SIO0_IPR_ADDR INTC_IPRI
169#define SIO0_IPR_POS 3
170#define SIO0_PRIORITY 3
171
172/* SIU (Sound Interface Unit) */
173#define SIU_IRQ 108
174#define SIU_IPR_ADDR INTC_IPRJ
175#define SIU_IPR_POS 1
176#define SIU_PRIORITY 3
177
178#endif
179#elif defined(CONFIG_CPU_SH4)
180#define DMTE0_IRQ 34
181#define DMTE1_IRQ 35
182#define DMTE2_IRQ 36
183#define DMTE3_IRQ 37
184#define DMTE4_IRQ 44 /* 7751R only */
185#define DMTE5_IRQ 45 /* 7751R only */
186#define DMTE6_IRQ 46 /* 7751R only */
187#define DMTE7_IRQ 47 /* 7751R only */
188#define DMAE_IRQ 38
189#define DMA_IPR_ADDR INTC_IPRC
190#define DMA_IPR_POS 2
191#define DMA_PRIORITY 7
192#endif
193
194#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
195 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
196 defined (CONFIG_CPU_SUBTYPE_SH7751)
197#define SCI_ERI_IRQ 23
198#define SCI_RXI_IRQ 24
199#define SCI_TXI_IRQ 25
200#define SCI_IPR_ADDR INTC_IPRB
201#define SCI_IPR_POS 1
202#define SCI_PRIORITY 3
203#endif
204
205#if defined(CONFIG_CPU_SUBTYPE_SH7300)
206#define SCIF0_IRQ 80
207#define SCIF0_IPR_ADDR INTC_IPRG
208#define SCIF0_IPR_POS 3
209#define SCIF0_PRIORITY 3
210#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
212 defined(CONFIG_CPU_SUBTYPE_SH7709)
213#define SCIF_ERI_IRQ 56
214#define SCIF_RXI_IRQ 57
215#define SCIF_BRI_IRQ 58
216#define SCIF_TXI_IRQ 59
217#define SCIF_IPR_ADDR INTC_IPRE
218#define SCIF_IPR_POS 1
219#define SCIF_PRIORITY 3
220
221#define IRDA_ERI_IRQ 52
222#define IRDA_RXI_IRQ 53
223#define IRDA_BRI_IRQ 54
224#define IRDA_TXI_IRQ 55
225#define IRDA_IPR_ADDR INTC_IPRE
226#define IRDA_IPR_POS 2
227#define IRDA_PRIORITY 3
228#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
229 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
230#define SCIF_ERI_IRQ 40
231#define SCIF_RXI_IRQ 41
232#define SCIF_BRI_IRQ 42
233#define SCIF_TXI_IRQ 43
234#define SCIF_IPR_ADDR INTC_IPRC
235#define SCIF_IPR_POS 1
236#define SCIF_PRIORITY 3
237#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
238#define SCIF1_ERI_IRQ 23
239#define SCIF1_RXI_IRQ 24
240#define SCIF1_BRI_IRQ 25
241#define SCIF1_TXI_IRQ 26
242#define SCIF1_IPR_ADDR INTC_IPRB
243#define SCIF1_IPR_POS 1
244#define SCIF1_PRIORITY 3
245#endif /* ST40STB1 */
246
247#endif /* 775x / SH4-202 / ST40STB1 */
248#endif /* 7780 */
249
250/* NR_IRQS is made from three components:
251 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
252 * 2. PINT_NR_IRQS - number of PINT interrupts
253 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
254 */
255
256/* 1. ONCHIP_NR_IRQS */
257#if defined(CONFIG_CPU_SUBTYPE_SH7604)
258# define ONCHIP_NR_IRQS 24 // Actually 21
259#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
260# define ONCHIP_NR_IRQS 64
261# define PINT_NR_IRQS 16
262#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
263# define ONCHIP_NR_IRQS 32
264#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7705)
266# define ONCHIP_NR_IRQS 64 // Actually 61
267# define PINT_NR_IRQS 16
268#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
269# define ONCHIP_NR_IRQS 48 // Actually 44
270#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
271# define ONCHIP_NR_IRQS 72
272#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
273# define ONCHIP_NR_IRQS 112 /* XXX */
274#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
275# define ONCHIP_NR_IRQS 72
276#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
277# define ONCHIP_NR_IRQS 144
278#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
279 defined(CONFIG_CPU_SUBTYPE_SH73180)
280# define ONCHIP_NR_IRQS 109
281#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
282# define ONCHIP_NR_IRQS 111
283#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
284# define ONCHIP_NR_IRQS 144
285#endif
286
287/* 2. PINT_NR_IRQS */
288#ifdef CONFIG_SH_UNKNOWN
289# define PINT_NR_IRQS 16
290#else
291# ifndef PINT_NR_IRQS
292# define PINT_NR_IRQS 0
293# endif
294#endif
295
296#if PINT_NR_IRQS > 0
297# define PINT_IRQ_BASE ONCHIP_NR_IRQS
298#endif
299
300/* 3. OFFCHIP_NR_IRQS */
301#if defined(CONFIG_HD64461)
302# define OFFCHIP_NR_IRQS 18
303#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
304# define OFFCHIP_NR_IRQS 48
305#elif defined(CONFIG_HD64465)
306# define OFFCHIP_NR_IRQS 16
307#elif defined (CONFIG_SH_EC3104)
308# define OFFCHIP_NR_IRQS 16
309#elif defined (CONFIG_SH_DREAMCAST)
310# define OFFCHIP_NR_IRQS 96
311#elif defined (CONFIG_SH_TITAN)
312# define OFFCHIP_NR_IRQS 4
313#elif defined(CONFIG_SH_R7780RP)
314# define OFFCHIP_NR_IRQS 16
315#elif defined(CONFIG_SH_UNKNOWN)
316# define OFFCHIP_NR_IRQS 16 /* Must also be last */
317#else
318# define OFFCHIP_NR_IRQS 0
319#endif
320
321#if OFFCHIP_NR_IRQS > 0
322# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
323#endif
324
325/* NR_IRQS. 1+2+3 */
326#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
327
328extern void disable_irq(unsigned int);
329extern void disable_irq_nosync(unsigned int);
330extern void enable_irq(unsigned int);
331
332/*
333 * Simple Mask Register Support
334 */
335extern void make_maskreg_irq(unsigned int irq);
336extern unsigned short *irq_mask_register;
337
338/*
339 * Function for "on chip support modules".
340 */
341extern void make_ipr_irq(unsigned int irq, unsigned int addr,
342 int pos, int priority);
343extern void make_imask_irq(unsigned int irq);
344
345#if defined(CONFIG_CPU_SUBTYPE_SH7300)
346#undef INTC_IPRA
347#undef INTC_IPRB
348#define INTC_IPRA 0xA414FEE2UL
349#define INTC_IPRB 0xA414FEE4UL
350#define INTC_IPRC 0xA4140016UL
351#define INTC_IPRD 0xA4140018UL
352#define INTC_IPRE 0xA414001AUL
353#define INTC_IPRF 0xA4080000UL
354#define INTC_IPRG 0xA4080002UL
355#define INTC_IPRH 0xA4080004UL
356#define INTC_IPRI 0xA4080006UL
357#define INTC_IPRJ 0xA4080008UL
358
359#define INTC_IMR0 0xA4080040UL
360#define INTC_IMR1 0xA4080042UL
361#define INTC_IMR2 0xA4080044UL
362#define INTC_IMR3 0xA4080046UL
363#define INTC_IMR4 0xA4080048UL
364#define INTC_IMR5 0xA408004AUL
365#define INTC_IMR6 0xA408004CUL
366#define INTC_IMR7 0xA408004EUL
367#define INTC_IMR8 0xA4080050UL
368#define INTC_IMR9 0xA4080052UL
369#define INTC_IMR10 0xA4080054UL
370
371#define INTC_IMCR0 0xA4080060UL
372#define INTC_IMCR1 0xA4080062UL
373#define INTC_IMCR2 0xA4080064UL
374#define INTC_IMCR3 0xA4080066UL
375#define INTC_IMCR4 0xA4080068UL
376#define INTC_IMCR5 0xA408006AUL
377#define INTC_IMCR6 0xA408006CUL
378#define INTC_IMCR7 0xA408006EUL
379#define INTC_IMCR8 0xA4080070UL
380#define INTC_IMCR9 0xA4080072UL
381#define INTC_IMCR10 0xA4080074UL
382
383#define INTC_ICR0 0xA414FEE0UL
384#define INTC_ICR1 0xA4140010UL
385
386#define INTC_IRR0 0xA4140004UL
387
388#define PORT_PACR 0xA4050100UL
389#define PORT_PBCR 0xA4050102UL
390#define PORT_PCCR 0xA4050104UL
391#define PORT_PDCR 0xA4050106UL
392#define PORT_PECR 0xA4050108UL
393#define PORT_PFCR 0xA405010AUL
394#define PORT_PGCR 0xA405010CUL
395#define PORT_PHCR 0xA405010EUL
396#define PORT_PJCR 0xA4050110UL
397#define PORT_PKCR 0xA4050112UL
398#define PORT_PLCR 0xA4050114UL
399#define PORT_SCPCR 0xA4050116UL
400#define PORT_PMCR 0xA4050118UL
401#define PORT_PNCR 0xA405011AUL
402#define PORT_PQCR 0xA405011CUL
403
404#define PORT_PSELA 0xA4050140UL
405#define PORT_PSELB 0xA4050142UL
406#define PORT_PSELC 0xA4050144UL
407
408#define PORT_HIZCRA 0xA4050146UL
409#define PORT_HIZCRB 0xA4050148UL
410#define PORT_DRVCR 0xA4050150UL
411
412#define PORT_PADR 0xA4050120UL
413#define PORT_PBDR 0xA4050122UL
414#define PORT_PCDR 0xA4050124UL
415#define PORT_PDDR 0xA4050126UL
416#define PORT_PEDR 0xA4050128UL
417#define PORT_PFDR 0xA405012AUL
418#define PORT_PGDR 0xA405012CUL
419#define PORT_PHDR 0xA405012EUL
420#define PORT_PJDR 0xA4050130UL
421#define PORT_PKDR 0xA4050132UL
422#define PORT_PLDR 0xA4050134UL
423#define PORT_SCPDR 0xA4050136UL
424#define PORT_PMDR 0xA4050138UL
425#define PORT_PNDR 0xA405013AUL
426#define PORT_PQDR 0xA405013CUL
427
428#define IRQ0_IRQ 32
429#define IRQ1_IRQ 33
430#define IRQ2_IRQ 34
431#define IRQ3_IRQ 35
432#define IRQ4_IRQ 36
433#define IRQ5_IRQ 37
434
435#define IRQ0_IPR_ADDR INTC_IPRC
436#define IRQ1_IPR_ADDR INTC_IPRC
437#define IRQ2_IPR_ADDR INTC_IPRC
438#define IRQ3_IPR_ADDR INTC_IPRC
439#define IRQ4_IPR_ADDR INTC_IPRD
440#define IRQ5_IPR_ADDR INTC_IPRD
441
442#define IRQ0_IPR_POS 0
443#define IRQ1_IPR_POS 1
444#define IRQ2_IPR_POS 2
445#define IRQ3_IPR_POS 3
446#define IRQ4_IPR_POS 0
447#define IRQ5_IPR_POS 1
448
449#define IRQ0_PRIORITY 1
450#define IRQ1_PRIORITY 1
451#define IRQ2_PRIORITY 1
452#define IRQ3_PRIORITY 1
453#define IRQ4_PRIORITY 1
454#define IRQ5_PRIORITY 1
455
456extern int ipr_irq_demux(int irq);
457#define __irq_demux(irq) ipr_irq_demux(irq)
458
459#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
460#define INTC_IPRA 0xfffffee2UL
461#define INTC_IPRB 0xfffffe60UL
462
463#define INTC_VCRA 0xfffffe62UL
464#define INTC_VCRB 0xfffffe64UL
465#define INTC_VCRC 0xfffffe66UL
466#define INTC_VCRD 0xfffffe68UL
467
468#define INTC_VCRWDT 0xfffffee4UL
469#define INTC_VCRDIV 0xffffff0cUL
470#define INTC_VCRDMA0 0xffffffa0UL
471#define INTC_VCRDMA1 0xffffffa8UL
472
473#define INTC_ICR 0xfffffee0UL
474#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7709)
477#define INTC_IRR0 0xa4000004UL
478#define INTC_IRR1 0xa4000006UL
479#define INTC_IRR2 0xa4000008UL
480
481#define INTC_ICR0 0xfffffee0UL
482#define INTC_ICR1 0xa4000010UL
483#define INTC_ICR2 0xa4000012UL
484#define INTC_INTER 0xa4000014UL
485
486#define INTC_IPRC 0xa4000016UL
487#define INTC_IPRD 0xa4000018UL
488#define INTC_IPRE 0xa400001aUL
489#if defined(CONFIG_CPU_SUBTYPE_SH7707)
490#define INTC_IPRF 0xa400001cUL
491#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
492#define INTC_IPRF 0xa4080000UL
493#define INTC_IPRG 0xa4080002UL
494#define INTC_IPRH 0xa4080004UL
495#endif
496
497#define PORT_PACR 0xa4000100UL
498#define PORT_PBCR 0xa4000102UL
499#define PORT_PCCR 0xa4000104UL
500#define PORT_PFCR 0xa400010aUL
501#define PORT_PADR 0xa4000120UL
502#define PORT_PBDR 0xa4000122UL
503#define PORT_PCDR 0xa4000124UL
504#define PORT_PFDR 0xa400012aUL
505
506#define IRQ0_IRQ 32
507#define IRQ1_IRQ 33
508#define IRQ2_IRQ 34
509#define IRQ3_IRQ 35
510#define IRQ4_IRQ 36
511#define IRQ5_IRQ 37
512
513#define IRQ0_IPR_ADDR INTC_IPRC
514#define IRQ1_IPR_ADDR INTC_IPRC
515#define IRQ2_IPR_ADDR INTC_IPRC
516#define IRQ3_IPR_ADDR INTC_IPRC
517#define IRQ4_IPR_ADDR INTC_IPRD
518#define IRQ5_IPR_ADDR INTC_IPRD
519
520#define IRQ0_IPR_POS 0
521#define IRQ1_IPR_POS 1
522#define IRQ2_IPR_POS 2
523#define IRQ3_IPR_POS 3
524#define IRQ4_IPR_POS 0
525#define IRQ5_IPR_POS 1
526
527#define IRQ0_PRIORITY 1
528#define IRQ1_PRIORITY 1
529#define IRQ2_PRIORITY 1
530#define IRQ3_PRIORITY 1
531#define IRQ4_PRIORITY 1
532#define IRQ5_PRIORITY 1
533
534#define PINT0_IRQ 40
535#define PINT8_IRQ 41
536
537#define PINT0_IPR_ADDR INTC_IPRD
538#define PINT8_IPR_ADDR INTC_IPRD
539
540#define PINT0_IPR_POS 3
541#define PINT8_IPR_POS 2
542#define PINT0_PRIORITY 2
543#define PINT8_PRIORITY 2
544
545extern int ipr_irq_demux(int irq);
546#define __irq_demux(irq) ipr_irq_demux(irq)
547#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
548
549#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
550 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
551#define INTC_ICR 0xffd00000
552#define INTC_ICR_NMIL (1<<15)
553#define INTC_ICR_MAI (1<<14)
554#define INTC_ICR_NMIB (1<<9)
555#define INTC_ICR_NMIE (1<<8)
556#define INTC_ICR_IRLM (1<<7)
557#endif
558
559#ifdef CONFIG_CPU_SUBTYPE_SH7780
560#include <asm/irq-sh7780.h>
561#endif
562
563/* SH with INTC2-style interrupts */
564#ifdef CONFIG_CPU_HAS_INTC2_IRQ
565#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
566#define INTC2_BASE 0xfe080000
567#define INTC2_FIRST_IRQ 64
568#define INTC2_INTREQ_OFFSET 0x20
569#define INTC2_INTMSK_OFFSET 0x40
570#define INTC2_INTMSKCLR_OFFSET 0x60
571#define NR_INTC2_IRQS 25
572#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
573#define INTC2_BASE 0xfe080000
574#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
575#define INTC2_INTREQ_OFFSET 0x20
576#define INTC2_INTMSK_OFFSET 0x40
577#define INTC2_INTMSKCLR_OFFSET 0x60
578#define NR_INTC2_IRQS 64
579#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
580#define INTC2_BASE 0xffd40000
581#define INTC2_FIRST_IRQ 22
582#define INTC2_INTMSK_OFFSET (0x38)
583#define INTC2_INTMSKCLR_OFFSET (0x3c)
584#define NR_INTC2_IRQS 60
585#endif
586
587#define INTC2_INTPRI_OFFSET 0x00
588
589void make_intc2_irq(unsigned int irq,
590 unsigned int ipr_offset, unsigned int ipr_shift,
591 unsigned int msk_offset, unsigned int msk_shift,
592 unsigned int priority);
593void init_IRQ_intc2(void);
594void intc2_add_clear_irq(int irq, int (*fn)(int));
595
596#endif
597
598static inline int generic_irq_demux(int irq)
599{
600 return irq;
601}
602
603#ifndef __irq_demux
604#define __irq_demux(irq) (irq)
605#endif
606#define irq_canonicalize(irq) (irq)
607#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
608
609#if defined(CONFIG_CPU_SUBTYPE_SH73180)
610#include <asm/irq-sh73180.h>
611#endif
612
613#endif /* __ASM_SH_IRQ_H */