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1#ifndef _ASM_POWERPC_PGTABLE_64K_H
2#define _ASM_POWERPC_PGTABLE_64K_H
3#ifdef __KERNEL__
4
5#include <asm-generic/pgtable-nopud.h>
6
7
8#define PTE_INDEX_SIZE 12
9#define PMD_INDEX_SIZE 12
10#define PUD_INDEX_SIZE 0
11#define PGD_INDEX_SIZE 4
12
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16
17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
20
21/* With 4k base page size, hugepage PTEs go at the PMD level */
22#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
23
24/* PMD_SHIFT determines what a second-level page table entry can map */
25#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
26#define PMD_SIZE (1UL << PMD_SHIFT)
27#define PMD_MASK (~(PMD_SIZE-1))
28
29/* PGDIR_SHIFT determines what a third-level page table entry can map */
30#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
31#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
32#define PGDIR_MASK (~(PGDIR_SIZE-1))
33
34/* Additional PTE bits (don't change without checking asm in hash_low.S) */
35#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
36#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
37#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
38#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
39#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
40
41/* PTE flags to conserve for HPTE identification */
42#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
43 _PAGE_COMBO)
44
45/* Shift to put page number into pte.
46 *
47 * That gives us a max RPN of 32 bits, which means a max of 48 bits
48 * of addressable physical space.
49 * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
50 * 32 makes PTEs more readable for debugging for now :)
51 */
52#define PTE_RPN_SHIFT (32)
53#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
54#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
55
56/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
57 * pgprot changes
58 */
59#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
60 _PAGE_ACCESSED)
61
62/* Bits to mask out from a PMD to get to the PTE page */
63#define PMD_MASKED_BITS 0x1ff
64/* Bits to mask out from a PGD/PUD to get to the PMD page */
65#define PUD_MASKED_BITS 0x1ff
66
67#ifndef __ASSEMBLY__
68
69/* Manipulate "rpte" values */
70#define __real_pte(e,p) ((real_pte_t) { \
71 (e), pte_val(*((p) + PTRS_PER_PTE)) })
72#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
73 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
74#define __rpte_to_pte(r) ((r).pte)
75#define __rpte_sub_valid(rpte, index) \
76 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
77
78
79/* Trick: we set __end to va + 64k, which happens works for
80 * a 16M page as well as we want only one iteration
81 */
82#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
83 do { \
84 unsigned long __end = va + PAGE_SIZE; \
85 unsigned __split = (psize == MMU_PAGE_4K || \
86 psize == MMU_PAGE_64K_AP); \
87 shift = mmu_psize_defs[psize].shift; \
88 for (index = 0; va < __end; index++, va += (1 << shift)) { \
89 if (!__split || __rpte_sub_valid(rpte, index)) do { \
90
91#define pte_iterate_hashed_end() } while(0); } } while(0)
92
93
94#endif /* __ASSEMBLY__ */
95#endif /* __KERNEL__ */
96#endif /* _ASM_POWERPC_PGTABLE_64K_H */