tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/ppc/syslib/ppc85xx_setup.c
3 *
4 * MPC85XX common board code
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/types.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21#include <linux/serial.h>
22#include <linux/tty.h> /* for linux/serial_core.h */
23#include <linux/serial_core.h>
24#include <linux/serial_8250.h>
25
26#include <asm/time.h>
27#include <asm/mpc85xx.h>
28#include <asm/immap_85xx.h>
29#include <asm/mmu.h>
30#include <asm/ppc_sys.h>
31#include <asm/kgdb.h>
32#include <asm/machdep.h>
33
34#include <syslib/ppc85xx_setup.h>
35
36extern void abort(void);
37
38/* Return the amount of memory */
39unsigned long __init
40mpc85xx_find_end_of_memory(void)
41{
42 bd_t *binfo;
43
44 binfo = (bd_t *) __res;
45
46 return binfo->bi_memsize;
47}
48
49/* The decrementer counts at the system (internal) clock freq divided by 8 */
50void __init
51mpc85xx_calibrate_decr(void)
52{
53 bd_t *binfo = (bd_t *) __res;
54 unsigned int freq, divisor;
55
56 /* get the core frequency */
57 freq = binfo->bi_busfreq;
58
59 /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
60 divisor = 8;
61 tb_ticks_per_jiffy = freq / divisor / HZ;
62 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
63
64 /* Set the time base to zero */
65 mtspr(SPRN_TBWL, 0);
66 mtspr(SPRN_TBWU, 0);
67
68 /* Clear any pending timer interrupts */
69 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
70
71 /* Enable decrementer interrupt */
72 mtspr(SPRN_TCR, TCR_DIE);
73}
74
75#ifdef CONFIG_SERIAL_8250
76void __init
77mpc85xx_early_serial_map(void)
78{
79#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
80 struct uart_port serial_req;
81#endif
82 struct plat_serial8250_port *pdata;
83 bd_t *binfo = (bd_t *) __res;
84 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
85
86 /* Setup serial port access */
87 pdata[0].uartclk = binfo->bi_busfreq;
88 pdata[0].mapbase += binfo->bi_immr_base;
89 pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
90
91#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
92 memset(&serial_req, 0, sizeof (serial_req));
93 serial_req.iotype = UPIO_MEM;
94 serial_req.mapbase = pdata[0].mapbase;
95 serial_req.membase = pdata[0].membase;
96 serial_req.regshift = 0;
97
98 gen550_init(0, &serial_req);
99#endif
100
101 pdata[1].uartclk = binfo->bi_busfreq;
102 pdata[1].mapbase += binfo->bi_immr_base;
103 pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
104
105#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
106 /* Assume gen550_init() doesn't modify serial_req */
107 serial_req.mapbase = pdata[1].mapbase;
108 serial_req.membase = pdata[1].membase;
109
110 gen550_init(1, &serial_req);
111#endif
112}
113#endif
114
115void
116mpc85xx_restart(char *cmd)
117{
118 local_irq_disable();
119 abort();
120}
121
122void
123mpc85xx_power_off(void)
124{
125 local_irq_disable();
126 for(;;);
127}
128
129void
130mpc85xx_halt(void)
131{
132 local_irq_disable();
133 for(;;);
134}
135
136#ifdef CONFIG_PCI
137
138#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
139extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
140extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
141#endif
142
143static void __init
144mpc85xx_setup_pci1(struct pci_controller *hose)
145{
146 volatile struct ccsr_pci *pci;
147 volatile struct ccsr_guts *guts;
148 unsigned short temps;
149 bd_t *binfo = (bd_t *) __res;
150
151 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
152 MPC85xx_PCI1_SIZE);
153
154 guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
155 MPC85xx_GUTS_SIZE);
156
157 early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
158 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
159 early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
160
161#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
162 if (guts->pordevsr & PORDEVSR_PCI) {
163 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
164 } else {
165 /* PCI-X init */
166 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
167 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
168 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
169 }
170
171 /* Disable all windows (except powar0 since its ignored) */
172 pci->powar1 = 0;
173 pci->powar2 = 0;
174 pci->powar3 = 0;
175 pci->powar4 = 0;
176 pci->piwar1 = 0;
177 pci->piwar2 = 0;
178 pci->piwar3 = 0;
179
180 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
181 pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
182 pci->potear1 = 0x00000000;
183 pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
184 /* Enable, Mem R/W */
185 pci->powar1 = 0x80044000 |
186 (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
187
188 /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
189 pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
190 pci->potear2 = 0x00000000;
191 pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
192 /* Enable, IO R/W */
193 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
194
195 /* Setup 2G inbound Memory Window @ 0 */
196 pci->pitar1 = 0x00000000;
197 pci->piwbar1 = 0x00000000;
198 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
199 Mem, Snoop R/W, 2G */
200}
201
202
203extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
204extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
205
206#ifdef CONFIG_85xx_PCI2
207static void __init
208mpc85xx_setup_pci2(struct pci_controller *hose)
209{
210 volatile struct ccsr_pci *pci;
211 unsigned short temps;
212 bd_t *binfo = (bd_t *) __res;
213
214 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
215 MPC85xx_PCI2_SIZE);
216
217 early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
218 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
219 early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
220 early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
221
222 /* Disable all windows (except powar0 since its ignored) */
223 pci->powar1 = 0;
224 pci->powar2 = 0;
225 pci->powar3 = 0;
226 pci->powar4 = 0;
227 pci->piwar1 = 0;
228 pci->piwar2 = 0;
229 pci->piwar3 = 0;
230
231 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
232 pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
233 pci->potear1 = 0x00000000;
234 pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
235 /* Enable, Mem R/W */
236 pci->powar1 = 0x80044000 |
237 (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
238
239 /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
240 pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;;
241 pci->potear2 = 0x00000000;
242 pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
243 /* Enable, IO R/W */
244 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
245
246 /* Setup 2G inbound Memory Window @ 0 */
247 pci->pitar1 = 0x00000000;
248 pci->piwbar1 = 0x00000000;
249 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
250 Mem, Snoop R/W, 2G */
251}
252#endif /* CONFIG_85xx_PCI2 */
253
254int mpc85xx_pci1_last_busno = 0;
255
256void __init
257mpc85xx_setup_hose(void)
258{
259 struct pci_controller *hose_a;
260#ifdef CONFIG_85xx_PCI2
261 struct pci_controller *hose_b;
262#endif
263 bd_t *binfo = (bd_t *) __res;
264
265 hose_a = pcibios_alloc_controller();
266
267 if (!hose_a)
268 return;
269
270 ppc_md.pci_swizzle = common_swizzle;
271 ppc_md.pci_map_irq = mpc85xx_map_irq;
272
273 hose_a->first_busno = 0;
274 hose_a->bus_offset = 0;
275 hose_a->last_busno = 0xff;
276
277 setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
278 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
279 hose_a->set_cfg_type = 1;
280
281 mpc85xx_setup_pci1(hose_a);
282
283 hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
284 hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
285 hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
286
287 hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
288 hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
289 hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
290#ifdef CONFIG_85xx_PCI2
291 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
292 MPC85XX_PCI1_IO_SIZE +
293 MPC85XX_PCI2_IO_SIZE);
294#else
295 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
296 MPC85XX_PCI1_IO_SIZE);
297#endif
298 isa_io_base = (unsigned long)hose_a->io_base_virt;
299
300 /* setup resources */
301 pci_init_resource(&hose_a->mem_resources[0],
302 MPC85XX_PCI1_LOWER_MEM,
303 MPC85XX_PCI1_UPPER_MEM,
304 IORESOURCE_MEM, "PCI1 host bridge");
305
306 pci_init_resource(&hose_a->io_resource,
307 MPC85XX_PCI1_LOWER_IO,
308 MPC85XX_PCI1_UPPER_IO,
309 IORESOURCE_IO, "PCI1 host bridge");
310
311 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
312
313#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
314 /* Pre pciauto_bus_scan VIA init */
315 mpc85xx_cds_enable_via(hose_a);
316#endif
317
318 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
319
320#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
321 /* Post pciauto_bus_scan VIA fixup */
322 mpc85xx_cds_fixup_via(hose_a);
323#endif
324
325#ifdef CONFIG_85xx_PCI2
326 hose_b = pcibios_alloc_controller();
327
328 if (!hose_b)
329 return;
330
331 hose_b->bus_offset = hose_a->last_busno + 1;
332 hose_b->first_busno = hose_a->last_busno + 1;
333 hose_b->last_busno = 0xff;
334
335 setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
336 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
337 hose_b->set_cfg_type = 1;
338
339 mpc85xx_setup_pci2(hose_b);
340
341 hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
342 hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
343 hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
344
345 hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
346 hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
347 hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
348 hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
349
350 /* setup resources */
351 pci_init_resource(&hose_b->mem_resources[0],
352 MPC85XX_PCI2_LOWER_MEM,
353 MPC85XX_PCI2_UPPER_MEM,
354 IORESOURCE_MEM, "PCI2 host bridge");
355
356 pci_init_resource(&hose_b->io_resource,
357 MPC85XX_PCI2_LOWER_IO,
358 MPC85XX_PCI2_UPPER_IO,
359 IORESOURCE_IO, "PCI2 host bridge");
360
361 hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
362
363 /* let board code know what the last bus number was on PCI1 */
364 mpc85xx_pci1_last_busno = hose_a->last_busno;
365#endif
366 return;
367}
368#endif /* CONFIG_PCI */
369
370