tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
3 *
4 * MPC85xx Device descriptions
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/device.h>
19#include <linux/serial_8250.h>
20#include <linux/fsl_devices.h>
21#include <asm/mpc85xx.h>
22#include <asm/irq.h>
23#include <asm/ppc_sys.h>
24
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49};
50
51static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
57};
58
59static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
65};
66
67static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
73};
74
75static struct gianfar_platform_data mpc85xx_fec_pdata = {
76 .device_flags = 0,
77};
78
79static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
81};
82
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85};
86
87static struct plat_serial8250_port serial_platform_data[] = {
88 [0] = {
89 .mapbase = 0x4500,
90 .irq = MPC85xx_IRQ_DUART,
91 .iotype = UPIO_MEM,
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
93 },
94 [1] = {
95 .mapbase = 0x4600,
96 .irq = MPC85xx_IRQ_DUART,
97 .iotype = UPIO_MEM,
98 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
99 },
100 { },
101};
102
103struct platform_device ppc_sys_platform_devices[] = {
104 [MPC85xx_TSEC1] = {
105 .name = "fsl-gianfar",
106 .id = 1,
107 .dev.platform_data = &mpc85xx_tsec1_pdata,
108 .num_resources = 4,
109 .resource = (struct resource[]) {
110 {
111 .start = MPC85xx_ENET1_OFFSET,
112 .end = MPC85xx_ENET1_OFFSET +
113 MPC85xx_ENET1_SIZE - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "tx",
118 .start = MPC85xx_IRQ_TSEC1_TX,
119 .end = MPC85xx_IRQ_TSEC1_TX,
120 .flags = IORESOURCE_IRQ,
121 },
122 {
123 .name = "rx",
124 .start = MPC85xx_IRQ_TSEC1_RX,
125 .end = MPC85xx_IRQ_TSEC1_RX,
126 .flags = IORESOURCE_IRQ,
127 },
128 {
129 .name = "error",
130 .start = MPC85xx_IRQ_TSEC1_ERROR,
131 .end = MPC85xx_IRQ_TSEC1_ERROR,
132 .flags = IORESOURCE_IRQ,
133 },
134 },
135 },
136 [MPC85xx_TSEC2] = {
137 .name = "fsl-gianfar",
138 .id = 2,
139 .dev.platform_data = &mpc85xx_tsec2_pdata,
140 .num_resources = 4,
141 .resource = (struct resource[]) {
142 {
143 .start = MPC85xx_ENET2_OFFSET,
144 .end = MPC85xx_ENET2_OFFSET +
145 MPC85xx_ENET2_SIZE - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .name = "tx",
150 .start = MPC85xx_IRQ_TSEC2_TX,
151 .end = MPC85xx_IRQ_TSEC2_TX,
152 .flags = IORESOURCE_IRQ,
153 },
154 {
155 .name = "rx",
156 .start = MPC85xx_IRQ_TSEC2_RX,
157 .end = MPC85xx_IRQ_TSEC2_RX,
158 .flags = IORESOURCE_IRQ,
159 },
160 {
161 .name = "error",
162 .start = MPC85xx_IRQ_TSEC2_ERROR,
163 .end = MPC85xx_IRQ_TSEC2_ERROR,
164 .flags = IORESOURCE_IRQ,
165 },
166 },
167 },
168 [MPC85xx_FEC] = {
169 .name = "fsl-gianfar",
170 .id = 3,
171 .dev.platform_data = &mpc85xx_fec_pdata,
172 .num_resources = 2,
173 .resource = (struct resource[]) {
174 {
175 .start = MPC85xx_ENET3_OFFSET,
176 .end = MPC85xx_ENET3_OFFSET +
177 MPC85xx_ENET3_SIZE - 1,
178 .flags = IORESOURCE_MEM,
179
180 },
181 {
182 .start = MPC85xx_IRQ_FEC,
183 .end = MPC85xx_IRQ_FEC,
184 .flags = IORESOURCE_IRQ,
185 },
186 },
187 },
188 [MPC85xx_IIC1] = {
189 .name = "fsl-i2c",
190 .id = 1,
191 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
192 .num_resources = 2,
193 .resource = (struct resource[]) {
194 {
195 .start = MPC85xx_IIC1_OFFSET,
196 .end = MPC85xx_IIC1_OFFSET +
197 MPC85xx_IIC1_SIZE - 1,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = MPC85xx_IRQ_IIC1,
202 .end = MPC85xx_IRQ_IIC1,
203 .flags = IORESOURCE_IRQ,
204 },
205 },
206 },
207 [MPC85xx_DMA0] = {
208 .name = "fsl-dma",
209 .id = 0,
210 .num_resources = 2,
211 .resource = (struct resource[]) {
212 {
213 .start = MPC85xx_DMA0_OFFSET,
214 .end = MPC85xx_DMA0_OFFSET +
215 MPC85xx_DMA0_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .start = MPC85xx_IRQ_DMA0,
220 .end = MPC85xx_IRQ_DMA0,
221 .flags = IORESOURCE_IRQ,
222 },
223 },
224 },
225 [MPC85xx_DMA1] = {
226 .name = "fsl-dma",
227 .id = 1,
228 .num_resources = 2,
229 .resource = (struct resource[]) {
230 {
231 .start = MPC85xx_DMA1_OFFSET,
232 .end = MPC85xx_DMA1_OFFSET +
233 MPC85xx_DMA1_SIZE - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .start = MPC85xx_IRQ_DMA1,
238 .end = MPC85xx_IRQ_DMA1,
239 .flags = IORESOURCE_IRQ,
240 },
241 },
242 },
243 [MPC85xx_DMA2] = {
244 .name = "fsl-dma",
245 .id = 2,
246 .num_resources = 2,
247 .resource = (struct resource[]) {
248 {
249 .start = MPC85xx_DMA2_OFFSET,
250 .end = MPC85xx_DMA2_OFFSET +
251 MPC85xx_DMA2_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 {
255 .start = MPC85xx_IRQ_DMA2,
256 .end = MPC85xx_IRQ_DMA2,
257 .flags = IORESOURCE_IRQ,
258 },
259 },
260 },
261 [MPC85xx_DMA3] = {
262 .name = "fsl-dma",
263 .id = 3,
264 .num_resources = 2,
265 .resource = (struct resource[]) {
266 {
267 .start = MPC85xx_DMA3_OFFSET,
268 .end = MPC85xx_DMA3_OFFSET +
269 MPC85xx_DMA3_SIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = MPC85xx_IRQ_DMA3,
274 .end = MPC85xx_IRQ_DMA3,
275 .flags = IORESOURCE_IRQ,
276 },
277 },
278 },
279 [MPC85xx_DUART] = {
280 .name = "serial8250",
281 .id = PLAT8250_DEV_PLATFORM,
282 .dev.platform_data = serial_platform_data,
283 },
284 [MPC85xx_PERFMON] = {
285 .name = "fsl-perfmon",
286 .id = 1,
287 .num_resources = 2,
288 .resource = (struct resource[]) {
289 {
290 .start = MPC85xx_PERFMON_OFFSET,
291 .end = MPC85xx_PERFMON_OFFSET +
292 MPC85xx_PERFMON_SIZE - 1,
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = MPC85xx_IRQ_PERFMON,
297 .end = MPC85xx_IRQ_PERFMON,
298 .flags = IORESOURCE_IRQ,
299 },
300 },
301 },
302 [MPC85xx_SEC2] = {
303 .name = "fsl-sec2",
304 .id = 1,
305 .num_resources = 2,
306 .resource = (struct resource[]) {
307 {
308 .start = MPC85xx_SEC2_OFFSET,
309 .end = MPC85xx_SEC2_OFFSET +
310 MPC85xx_SEC2_SIZE - 1,
311 .flags = IORESOURCE_MEM,
312 },
313 {
314 .start = MPC85xx_IRQ_SEC2,
315 .end = MPC85xx_IRQ_SEC2,
316 .flags = IORESOURCE_IRQ,
317 },
318 },
319 },
320 [MPC85xx_CPM_FCC1] = {
321 .name = "fsl-cpm-fcc",
322 .id = 1,
323 .num_resources = 3,
324 .resource = (struct resource[]) {
325 {
326 .start = 0x91300,
327 .end = 0x9131F,
328 .flags = IORESOURCE_MEM,
329 },
330 {
331 .start = 0x91380,
332 .end = 0x9139F,
333 .flags = IORESOURCE_MEM,
334 },
335 {
336 .start = SIU_INT_FCC1,
337 .end = SIU_INT_FCC1,
338 .flags = IORESOURCE_IRQ,
339 },
340 },
341 },
342 [MPC85xx_CPM_FCC2] = {
343 .name = "fsl-cpm-fcc",
344 .id = 2,
345 .num_resources = 3,
346 .resource = (struct resource[]) {
347 {
348 .start = 0x91320,
349 .end = 0x9133F,
350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = 0x913A0,
354 .end = 0x913CF,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .start = SIU_INT_FCC2,
359 .end = SIU_INT_FCC2,
360 .flags = IORESOURCE_IRQ,
361 },
362 },
363 },
364 [MPC85xx_CPM_FCC3] = {
365 .name = "fsl-cpm-fcc",
366 .id = 3,
367 .num_resources = 3,
368 .resource = (struct resource[]) {
369 {
370 .start = 0x91340,
371 .end = 0x9135F,
372 .flags = IORESOURCE_MEM,
373 },
374 {
375 .start = 0x913D0,
376 .end = 0x913FF,
377 .flags = IORESOURCE_MEM,
378 },
379 {
380 .start = SIU_INT_FCC3,
381 .end = SIU_INT_FCC3,
382 .flags = IORESOURCE_IRQ,
383 },
384 },
385 },
386 [MPC85xx_CPM_I2C] = {
387 .name = "fsl-cpm-i2c",
388 .id = 1,
389 .num_resources = 2,
390 .resource = (struct resource[]) {
391 {
392 .start = 0x91860,
393 .end = 0x918BF,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = SIU_INT_I2C,
398 .end = SIU_INT_I2C,
399 .flags = IORESOURCE_IRQ,
400 },
401 },
402 },
403 [MPC85xx_CPM_SCC1] = {
404 .name = "fsl-cpm-scc",
405 .id = 1,
406 .num_resources = 2,
407 .resource = (struct resource[]) {
408 {
409 .start = 0x91A00,
410 .end = 0x91A1F,
411 .flags = IORESOURCE_MEM,
412 },
413 {
414 .start = SIU_INT_SCC1,
415 .end = SIU_INT_SCC1,
416 .flags = IORESOURCE_IRQ,
417 },
418 },
419 },
420 [MPC85xx_CPM_SCC2] = {
421 .name = "fsl-cpm-scc",
422 .id = 2,
423 .num_resources = 2,
424 .resource = (struct resource[]) {
425 {
426 .start = 0x91A20,
427 .end = 0x91A3F,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 .start = SIU_INT_SCC2,
432 .end = SIU_INT_SCC2,
433 .flags = IORESOURCE_IRQ,
434 },
435 },
436 },
437 [MPC85xx_CPM_SCC3] = {
438 .name = "fsl-cpm-scc",
439 .id = 3,
440 .num_resources = 2,
441 .resource = (struct resource[]) {
442 {
443 .start = 0x91A40,
444 .end = 0x91A5F,
445 .flags = IORESOURCE_MEM,
446 },
447 {
448 .start = SIU_INT_SCC3,
449 .end = SIU_INT_SCC3,
450 .flags = IORESOURCE_IRQ,
451 },
452 },
453 },
454 [MPC85xx_CPM_SCC4] = {
455 .name = "fsl-cpm-scc",
456 .id = 4,
457 .num_resources = 2,
458 .resource = (struct resource[]) {
459 {
460 .start = 0x91A60,
461 .end = 0x91A7F,
462 .flags = IORESOURCE_MEM,
463 },
464 {
465 .start = SIU_INT_SCC4,
466 .end = SIU_INT_SCC4,
467 .flags = IORESOURCE_IRQ,
468 },
469 },
470 },
471 [MPC85xx_CPM_SPI] = {
472 .name = "fsl-cpm-spi",
473 .id = 1,
474 .num_resources = 2,
475 .resource = (struct resource[]) {
476 {
477 .start = 0x91AA0,
478 .end = 0x91AFF,
479 .flags = IORESOURCE_MEM,
480 },
481 {
482 .start = SIU_INT_SPI,
483 .end = SIU_INT_SPI,
484 .flags = IORESOURCE_IRQ,
485 },
486 },
487 },
488 [MPC85xx_CPM_MCC1] = {
489 .name = "fsl-cpm-mcc",
490 .id = 1,
491 .num_resources = 2,
492 .resource = (struct resource[]) {
493 {
494 .start = 0x91B30,
495 .end = 0x91B3F,
496 .flags = IORESOURCE_MEM,
497 },
498 {
499 .start = SIU_INT_MCC1,
500 .end = SIU_INT_MCC1,
501 .flags = IORESOURCE_IRQ,
502 },
503 },
504 },
505 [MPC85xx_CPM_MCC2] = {
506 .name = "fsl-cpm-mcc",
507 .id = 2,
508 .num_resources = 2,
509 .resource = (struct resource[]) {
510 {
511 .start = 0x91B50,
512 .end = 0x91B5F,
513 .flags = IORESOURCE_MEM,
514 },
515 {
516 .start = SIU_INT_MCC2,
517 .end = SIU_INT_MCC2,
518 .flags = IORESOURCE_IRQ,
519 },
520 },
521 },
522 [MPC85xx_CPM_SMC1] = {
523 .name = "fsl-cpm-smc",
524 .id = 1,
525 .num_resources = 2,
526 .resource = (struct resource[]) {
527 {
528 .start = 0x91A80,
529 .end = 0x91A8F,
530 .flags = IORESOURCE_MEM,
531 },
532 {
533 .start = SIU_INT_SMC1,
534 .end = SIU_INT_SMC1,
535 .flags = IORESOURCE_IRQ,
536 },
537 },
538 },
539 [MPC85xx_CPM_SMC2] = {
540 .name = "fsl-cpm-smc",
541 .id = 2,
542 .num_resources = 2,
543 .resource = (struct resource[]) {
544 {
545 .start = 0x91A90,
546 .end = 0x91A9F,
547 .flags = IORESOURCE_MEM,
548 },
549 {
550 .start = SIU_INT_SMC2,
551 .end = SIU_INT_SMC2,
552 .flags = IORESOURCE_IRQ,
553 },
554 },
555 },
556 [MPC85xx_CPM_USB] = {
557 .name = "fsl-cpm-usb",
558 .id = 2,
559 .num_resources = 2,
560 .resource = (struct resource[]) {
561 {
562 .start = 0x91B60,
563 .end = 0x91B7F,
564 .flags = IORESOURCE_MEM,
565 },
566 {
567 .start = SIU_INT_USB,
568 .end = SIU_INT_USB,
569 .flags = IORESOURCE_IRQ,
570 },
571 },
572 },
573 [MPC85xx_eTSEC1] = {
574 .name = "fsl-gianfar",
575 .id = 1,
576 .dev.platform_data = &mpc85xx_etsec1_pdata,
577 .num_resources = 4,
578 .resource = (struct resource[]) {
579 {
580 .start = MPC85xx_ENET1_OFFSET,
581 .end = MPC85xx_ENET1_OFFSET +
582 MPC85xx_ENET1_SIZE - 1,
583 .flags = IORESOURCE_MEM,
584 },
585 {
586 .name = "tx",
587 .start = MPC85xx_IRQ_TSEC1_TX,
588 .end = MPC85xx_IRQ_TSEC1_TX,
589 .flags = IORESOURCE_IRQ,
590 },
591 {
592 .name = "rx",
593 .start = MPC85xx_IRQ_TSEC1_RX,
594 .end = MPC85xx_IRQ_TSEC1_RX,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 .name = "error",
599 .start = MPC85xx_IRQ_TSEC1_ERROR,
600 .end = MPC85xx_IRQ_TSEC1_ERROR,
601 .flags = IORESOURCE_IRQ,
602 },
603 },
604 },
605 [MPC85xx_eTSEC2] = {
606 .name = "fsl-gianfar",
607 .id = 2,
608 .dev.platform_data = &mpc85xx_etsec2_pdata,
609 .num_resources = 4,
610 .resource = (struct resource[]) {
611 {
612 .start = MPC85xx_ENET2_OFFSET,
613 .end = MPC85xx_ENET2_OFFSET +
614 MPC85xx_ENET2_SIZE - 1,
615 .flags = IORESOURCE_MEM,
616 },
617 {
618 .name = "tx",
619 .start = MPC85xx_IRQ_TSEC2_TX,
620 .end = MPC85xx_IRQ_TSEC2_TX,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .name = "rx",
625 .start = MPC85xx_IRQ_TSEC2_RX,
626 .end = MPC85xx_IRQ_TSEC2_RX,
627 .flags = IORESOURCE_IRQ,
628 },
629 {
630 .name = "error",
631 .start = MPC85xx_IRQ_TSEC2_ERROR,
632 .end = MPC85xx_IRQ_TSEC2_ERROR,
633 .flags = IORESOURCE_IRQ,
634 },
635 },
636 },
637 [MPC85xx_eTSEC3] = {
638 .name = "fsl-gianfar",
639 .id = 3,
640 .dev.platform_data = &mpc85xx_etsec3_pdata,
641 .num_resources = 4,
642 .resource = (struct resource[]) {
643 {
644 .start = MPC85xx_ENET3_OFFSET,
645 .end = MPC85xx_ENET3_OFFSET +
646 MPC85xx_ENET3_SIZE - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 {
650 .name = "tx",
651 .start = MPC85xx_IRQ_TSEC3_TX,
652 .end = MPC85xx_IRQ_TSEC3_TX,
653 .flags = IORESOURCE_IRQ,
654 },
655 {
656 .name = "rx",
657 .start = MPC85xx_IRQ_TSEC3_RX,
658 .end = MPC85xx_IRQ_TSEC3_RX,
659 .flags = IORESOURCE_IRQ,
660 },
661 {
662 .name = "error",
663 .start = MPC85xx_IRQ_TSEC3_ERROR,
664 .end = MPC85xx_IRQ_TSEC3_ERROR,
665 .flags = IORESOURCE_IRQ,
666 },
667 },
668 },
669 [MPC85xx_eTSEC4] = {
670 .name = "fsl-gianfar",
671 .id = 4,
672 .dev.platform_data = &mpc85xx_etsec4_pdata,
673 .num_resources = 4,
674 .resource = (struct resource[]) {
675 {
676 .start = 0x27000,
677 .end = 0x27fff,
678 .flags = IORESOURCE_MEM,
679 },
680 {
681 .name = "tx",
682 .start = MPC85xx_IRQ_TSEC4_TX,
683 .end = MPC85xx_IRQ_TSEC4_TX,
684 .flags = IORESOURCE_IRQ,
685 },
686 {
687 .name = "rx",
688 .start = MPC85xx_IRQ_TSEC4_RX,
689 .end = MPC85xx_IRQ_TSEC4_RX,
690 .flags = IORESOURCE_IRQ,
691 },
692 {
693 .name = "error",
694 .start = MPC85xx_IRQ_TSEC4_ERROR,
695 .end = MPC85xx_IRQ_TSEC4_ERROR,
696 .flags = IORESOURCE_IRQ,
697 },
698 },
699 },
700 [MPC85xx_IIC2] = {
701 .name = "fsl-i2c",
702 .id = 2,
703 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
704 .num_resources = 2,
705 .resource = (struct resource[]) {
706 {
707 .start = 0x03100,
708 .end = 0x031ff,
709 .flags = IORESOURCE_MEM,
710 },
711 {
712 .start = MPC85xx_IRQ_IIC1,
713 .end = MPC85xx_IRQ_IIC1,
714 .flags = IORESOURCE_IRQ,
715 },
716 },
717 },
718 [MPC85xx_MDIO] = {
719 .name = "fsl-gianfar_mdio",
720 .id = 0,
721 .dev.platform_data = &mpc85xx_mdio_pdata,
722 .num_resources = 1,
723 .resource = (struct resource[]) {
724 {
725 .start = 0x24520,
726 .end = 0x2453f,
727 .flags = IORESOURCE_MEM,
728 },
729 },
730 },
731};
732
733static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
734{
735 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
736 return 0;
737}
738
739static int __init mach_mpc85xx_init(void)
740{
741 ppc_sys_device_fixup = mach_mpc85xx_fixup;
742 return 0;
743}
744
745postcore_initcall(mach_mpc85xx_init);