tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/ppc/platforms/chestnut.c
3 *
4 * Board setup routines for IBM Chestnut
5 *
6 * Author: <source@mvista.com>
7 *
8 * <2004> (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/blkdev.h>
23#include <linux/console.h>
24#include <linux/root_dev.h>
25#include <linux/initrd.h>
26#include <linux/delay.h>
27#include <linux/seq_file.h>
28#include <linux/ide.h>
29#include <linux/serial.h>
30#include <linux/serial_core.h>
31#include <linux/mtd/physmap.h>
32#include <asm/system.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/time.h>
36#include <asm/dma.h>
37#include <asm/io.h>
38#include <asm/hw_irq.h>
39#include <asm/machdep.h>
40#include <asm/kgdb.h>
41#include <asm/bootinfo.h>
42#include <asm/mv64x60.h>
43#include <platforms/chestnut.h>
44
45static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
46static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
47
48static mv64x60_handle_t bh;
49
50extern void gen550_progress(char *, unsigned short);
51extern void gen550_init(int, struct uart_port *);
52extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
53
54#define BIT(x) (1<<x)
55#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
56 BIT(MV64x60_CPU2DEV_1_WIN) | \
57 BIT(MV64x60_CPU2DEV_2_WIN) | \
58 BIT(MV64x60_CPU2DEV_3_WIN) | \
59 BIT(MV64x60_CPU2BOOT_WIN))
60/**************************************************************************
61 * FUNCTION: chestnut_calibrate_decr
62 *
63 * DESCRIPTION: initialize decrementer interrupt frequency (used as system
64 * timer)
65 *
66 ****/
67static void __init
68chestnut_calibrate_decr(void)
69{
70 ulong freq;
71
72 freq = CHESTNUT_BUS_SPEED / 4;
73
74 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
75 freq/1000000, freq%1000000);
76
77 tb_ticks_per_jiffy = freq / HZ;
78 tb_to_us = mulhwu_scale_factor(freq, 1000000);
79}
80
81static int
82chestnut_show_cpuinfo(struct seq_file *m)
83{
84 seq_printf(m, "vendor\t\t: IBM\n");
85 seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
86
87 return 0;
88}
89
90/**************************************************************************
91 * FUNCTION: chestnut_find_end_of_memory
92 *
93 * DESCRIPTION: ppc_md memory size callback
94 *
95 ****/
96unsigned long __init
97chestnut_find_end_of_memory(void)
98{
99 static int mem_size = 0;
100
101 if (mem_size == 0) {
102 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
103 MV64x60_TYPE_MV64460);
104 }
105 return mem_size;
106}
107
108#if defined(CONFIG_SERIAL_8250)
109static void __init
110chestnut_early_serial_map(void)
111{
112 struct uart_port port;
113
114 /* Setup serial port access */
115 memset(&port, 0, sizeof(port));
116 port.uartclk = BASE_BAUD * 16;
117 port.irq = UART0_INT;
118 port.flags = STD_COM_FLAGS | UPF_IOREMAP;
119 port.iotype = UPIO_MEM;
120 port.mapbase = CHESTNUT_UART0_IO_BASE;
121 port.regshift = 0;
122
123 if (early_serial_setup(&port) != 0)
124 printk("Early serial init of port 0 failed\n");
125
126 /* Assume early_serial_setup() doesn't modify serial_req */
127 port.line = 1;
128 port.irq = UART1_INT;
129 port.mapbase = CHESTNUT_UART1_IO_BASE;
130
131 if (early_serial_setup(&port) != 0)
132 printk("Early serial init of port 1 failed\n");
133}
134#endif
135
136/**************************************************************************
137 * FUNCTION: chestnut_map_irq
138 *
139 * DESCRIPTION: 0 return since PCI IRQs not needed
140 *
141 ****/
142static int __init
143chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
144{
145 static char pci_irq_table[][4] = {
146 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
147 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
148 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
149 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
150 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
151 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
152 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
153 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
154 };
155 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
156
157 return PCI_IRQ_TABLE_LOOKUP;
158}
159
160
161/**************************************************************************
162 * FUNCTION: chestnut_setup_bridge
163 *
164 * DESCRIPTION: initalize board-specific settings on the MV64360
165 *
166 ****/
167static void __init
168chestnut_setup_bridge(void)
169{
170 struct mv64x60_setup_info si;
171 int i;
172
173 if ( ppc_md.progress )
174 ppc_md.progress("chestnut_setup_bridge: enter", 0);
175
176 memset(&si, 0, sizeof(si));
177
178 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
179
180 /* setup only PCI bus 0 (bus 1 not used) */
181 si.pci_0.enable_bus = 1;
182 si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
183 si.pci_0.pci_io.pci_base_hi = 0;
184 si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
185 si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
186 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
187 si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
188 si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
189 si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
190 si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
191 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
192 si.pci_0.pci_cmd_bits = 0;
193 si.pci_0.latency_timer = 0x80;
194
195 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
196#if defined(CONFIG_NOT_COHERENT_CACHE)
197 si.cpu_prot_options[i] = 0;
198 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
199 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
200 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
201
202 si.pci_1.acc_cntl_options[i] =
203 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
204 MV64360_PCI_ACC_CNTL_SWAP_NONE |
205 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
206 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
207#else
208 si.cpu_prot_options[i] = 0;
209 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
210 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
211 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
212
213 si.pci_1.acc_cntl_options[i] =
214 MV64360_PCI_ACC_CNTL_SNOOP_WB |
215 MV64360_PCI_ACC_CNTL_SWAP_NONE |
216 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
217 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
218#endif
219 }
220
221 /* Lookup host bridge - on CPU 0 - no SMP support */
222 if (mv64x60_init(&bh, &si)) {
223 printk("\n\nPCI Bridge initialization failed!\n");
224 }
225
226 pci_dram_offset = 0;
227 ppc_md.pci_swizzle = common_swizzle;
228 ppc_md.pci_map_irq = chestnut_map_irq;
229 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
230
231 mv64x60_set_bus(&bh, 0, 0);
232 bh.hose_a->first_busno = 0;
233 bh.hose_a->last_busno = 0xff;
234 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
235}
236
237void __init
238chestnut_setup_peripherals(void)
239{
240 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
241 CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
242 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
243
244 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
245 CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
246 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
247
248 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
249 CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
250 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
251 cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
252
253 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
254 CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
255 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
256
257 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
258 CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
259 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
260
261 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
262 CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
263 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
264
265#ifdef CONFIG_NOT_COHERENT_CACHE
266 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
267#else
268 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
269#endif
270 sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
271 memset(sram_base, 0, MV64360_SRAM_SIZE);
272
273 /*
274 * Configure MPP pins for PCI DMA
275 *
276 * PCI Slot GNT pin REQ pin
277 * 0 MPP16 MPP17
278 * 1 MPP18 MPP19
279 * 2 MPP20 MPP21
280 * 3 MPP22 MPP23
281 */
282 mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
283 (0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */
284 (0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */
285 (0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */
286 (0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */
287 (0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */
288 (0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */
289 (0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */
290 (0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */
291 /*
292 * Set unused MPP pins for output, as per schematic note
293 *
294 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
295 * MPP09, MPP10, MPP13, MPP14, MPP15
296 */
297 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
298 (0xf << 4) | /* MPPSel01 GPIO[1] */
299 (0xf << 8) | /* MPPSel02 GPIO[2] */
300 (0xf << 16) | /* MPPSel04 GPIO[4] */
301 (0xf << 20) | /* MPPSel05 GPIO[5] */
302 (0xf << 24)); /* MPPSel06 GPIO[6] */
303 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
304 (0xf << 4) | /* MPPSel09 GPIO[9] */
305 (0xf << 8) | /* MPPSel10 GPIO[10] */
306 (0xf << 20) | /* MPPSel13 GPIO[13] */
307 (0xf << 24) | /* MPPSel14 GPIO[14] */
308 (0xf << 28)); /* MPPSel15 GPIO[15] */
309 mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
310 BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
311 BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
312
313 /*
314 * Configure the following MPP pins to indicate a level
315 * triggered interrupt
316 *
317 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
318 * MPP25 - UART A (high)
319 * MPP26 - UART B (high)
320 * MPP28 - PCI Slot 3 (low)
321 * MPP29 - PCI Slot 2 (low)
322 * MPP30 - PCI Slot 1 (low)
323 * MPP31 - PCI Slot 0 (low)
324 */
325 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
326 BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */
327 BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */
328 BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */
329 BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */
330 BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */
331 BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */
332 BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */
333
334 /*
335 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
336 * 31 (low) interrupt polarity input signal and level triggered
337 */
338 mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
339 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
340 BIT(28) | BIT(29) | BIT(30) | BIT(31));
341 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
342 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
343 BIT(31));
344
345 /* Config GPP interrupt controller to respond to level trigger */
346 mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
347
348 /*
349 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
350 */
351 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
352 ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
353 BIT(31)));
354 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
355 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
356 BIT(31));
357
358 /*
359 * Dismiss and then enable interrupt on CPU #0 high cause register
360 * BIT27 summarizes GPP interrupts 24-31
361 */
362 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
363
364 if (ppc_md.progress)
365 ppc_md.progress("chestnut_setup_bridge: exit", 0);
366}
367
368/**************************************************************************
369 * FUNCTION: chestnut_setup_arch
370 *
371 * DESCRIPTION: ppc_md machine configuration callback
372 *
373 ****/
374static void __init
375chestnut_setup_arch(void)
376{
377 if (ppc_md.progress)
378 ppc_md.progress("chestnut_setup_arch: enter", 0);
379
380 /* init to some ~sane value until calibrate_delay() runs */
381 loops_per_jiffy = 50000000 / HZ;
382
383 /* if the time base value is greater than bus freq/4 (the TB and
384 * decrementer tick rate) + signed integer rollover value, we
385 * can spend a fair amount of time waiting for the rollover to
386 * happen. To get around this, initialize the time base register
387 * to a "safe" value.
388 */
389 set_tb(0, 0);
390
391#ifdef CONFIG_BLK_DEV_INITRD
392 if (initrd_start)
393 ROOT_DEV = Root_RAM0;
394 else
395#endif
396#ifdef CONFIG_ROOT_NFS
397 ROOT_DEV = Root_NFS;
398#else
399 ROOT_DEV = Root_SDA2;
400#endif
401
402 /*
403 * Set up the L2CR register.
404 */
405 _set_L2CR(_get_L2CR() | L2CR_L2E);
406
407 chestnut_setup_bridge();
408 chestnut_setup_peripherals();
409
410#ifdef CONFIG_DUMMY_CONSOLE
411 conswitchp = &dummy_con;
412#endif
413
414#if defined(CONFIG_SERIAL_8250)
415 chestnut_early_serial_map();
416#endif
417
418 /* Identify the system */
419 printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
420 printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
421 " (source@mvista.com)\n");
422
423 if (ppc_md.progress)
424 ppc_md.progress("chestnut_setup_arch: exit", 0);
425}
426
427#ifdef CONFIG_MTD_PHYSMAP
428static struct mtd_partition ptbl;
429
430static int __init
431chestnut_setup_mtd(void)
432{
433 memset(&ptbl, 0, sizeof(ptbl));
434
435 ptbl.name = "User FS";
436 ptbl.size = CHESTNUT_32BIT_SIZE;
437
438 physmap_map.size = CHESTNUT_32BIT_SIZE;
439 physmap_set_partitions(&ptbl, 1);
440 return 0;
441}
442
443arch_initcall(chestnut_setup_mtd);
444#endif
445
446/**************************************************************************
447 * FUNCTION: chestnut_restart
448 *
449 * DESCRIPTION: ppc_md machine reset callback
450 * reset the board via the CPLD command register
451 *
452 ****/
453static void
454chestnut_restart(char *cmd)
455{
456 volatile ulong i = 10000000;
457
458 local_irq_disable();
459
460 /*
461 * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
462 *
463 * MPP24 - board reset
464 */
465 writeb(0x1, cpld_base + 3);
466
467 /* GPP pin tied to MPP earlier */
468 mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
469
470 while (i-- > 0);
471 panic("restart failed\n");
472}
473
474static void
475chestnut_halt(void)
476{
477 local_irq_disable();
478 for (;;);
479 /* NOTREACHED */
480}
481
482static void
483chestnut_power_off(void)
484{
485 chestnut_halt();
486 /* NOTREACHED */
487}
488
489/**************************************************************************
490 * FUNCTION: chestnut_map_io
491 *
492 * DESCRIPTION: configure fixed memory-mapped IO
493 *
494 ****/
495static void __init
496chestnut_map_io(void)
497{
498#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
499 io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
500 _PAGE_IO);
501#endif
502}
503
504/**************************************************************************
505 * FUNCTION: chestnut_set_bat
506 *
507 * DESCRIPTION: configures a (temporary) bat mapping for early access to
508 * device I/O
509 *
510 ****/
511static __inline__ void
512chestnut_set_bat(void)
513{
514 mb();
515 mtspr(SPRN_DBAT3U, 0xf0001ffe);
516 mtspr(SPRN_DBAT3L, 0xf000002a);
517 mb();
518}
519
520/**************************************************************************
521 * FUNCTION: platform_init
522 *
523 * DESCRIPTION: main entry point for configuring board-specific machine
524 * callbacks
525 *
526 ****/
527void __init
528platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
529 unsigned long r6, unsigned long r7)
530{
531 parse_bootinfo(find_bootinfo());
532
533 /* Copy the kernel command line arguments to a safe place. */
534
535 if (r6) {
536 *(char *) (r7 + KERNELBASE) = 0;
537 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
538 }
539
540 isa_mem_base = 0;
541
542 ppc_md.setup_arch = chestnut_setup_arch;
543 ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
544 ppc_md.init_IRQ = mv64360_init_irq;
545 ppc_md.get_irq = mv64360_get_irq;
546 ppc_md.init = NULL;
547
548 ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
549 ppc_md.setup_io_mappings = chestnut_map_io;
550
551 ppc_md.restart = chestnut_restart;
552 ppc_md.power_off = chestnut_power_off;
553 ppc_md.halt = chestnut_halt;
554
555 ppc_md.time_init = NULL;
556 ppc_md.set_rtc_time = NULL;
557 ppc_md.get_rtc_time = NULL;
558 ppc_md.calibrate_decr = chestnut_calibrate_decr;
559
560 ppc_md.nvram_read_val = NULL;
561 ppc_md.nvram_write_val = NULL;
562
563 ppc_md.heartbeat = NULL;
564
565 bh.p_base = CONFIG_MV64X60_NEW_BASE;
566
567 chestnut_set_bat();
568
569#if defined(CONFIG_SERIAL_TEXT_DEBUG)
570 ppc_md.progress = gen550_progress;
571#endif
572#if defined(CONFIG_KGDB)
573 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
574#endif
575
576 if (ppc_md.progress)
577 ppc_md.progress("chestnut_init(): exit", 0);
578}