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1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32#include <linux/config.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/errno.h>
36#include <linux/string.h>
37#include <linux/mm.h>
38#include <linux/tty.h>
39#include <linux/slab.h>
40#include <linux/delay.h>
41#include <linux/fb.h>
42#include <linux/init.h>
43#include <linux/pci.h>
44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/backlight.h>
53#endif
54
55#include "rivafb.h"
56#include "nvreg.h"
57
58#ifndef CONFIG_PCI /* sanity check */
59#error This driver requires PCI support.
60#endif
61
62/* version number of this driver */
63#define RIVAFB_VERSION "0.9.5b"
64
65/* ------------------------------------------------------------------------- *
66 *
67 * various helpful macros and constants
68 *
69 * ------------------------------------------------------------------------- */
70#ifdef CONFIG_FB_RIVA_DEBUG
71#define NVTRACE printk
72#else
73#define NVTRACE if(0) printk
74#endif
75
76#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
78
79#ifdef CONFIG_FB_RIVA_DEBUG
80#define assert(expr) \
81 if(!(expr)) { \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
84 BUG(); \
85 }
86#else
87#define assert(expr)
88#endif
89
90#define PFX "rivafb: "
91
92/* macro that allows you to set overflow bits */
93#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94#define SetBit(n) (1<<(n))
95#define Set8Bits(value) ((value)&0xff)
96
97/* HW cursor parameters */
98#define MAX_CURS 32
99
100/* ------------------------------------------------------------------------- *
101 *
102 * prototypes
103 *
104 * ------------------------------------------------------------------------- */
105
106static int rivafb_blank(int blank, struct fb_info *info);
107
108/* ------------------------------------------------------------------------- *
109 *
110 * card identification
111 *
112 * ------------------------------------------------------------------------- */
113
114static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
201};
202MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
203
204/* ------------------------------------------------------------------------- *
205 *
206 * global variables
207 *
208 * ------------------------------------------------------------------------- */
209
210/* command line data, set in rivafb_setup() */
211static int flatpanel __devinitdata = -1; /* Autodetect later */
212static int forceCRTC __devinitdata = -1;
213static int noaccel __devinitdata = 0;
214#ifdef CONFIG_MTRR
215static int nomtrr __devinitdata = 0;
216#endif
217
218static char *mode_option __devinitdata = NULL;
219static int strictmode = 0;
220
221static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
223 .xpanstep = 1,
224 .ypanstep = 1,
225};
226
227static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
228 .xres = 640,
229 .yres = 480,
230 .xres_virtual = 640,
231 .yres_virtual = 480,
232 .bits_per_pixel = 8,
233 .red = {0, 8, 0},
234 .green = {0, 8, 0},
235 .blue = {0, 8, 0},
236 .transp = {0, 0, 0},
237 .activate = FB_ACTIVATE_NOW,
238 .height = -1,
239 .width = -1,
240 .pixclock = 39721,
241 .left_margin = 40,
242 .right_margin = 24,
243 .upper_margin = 32,
244 .lower_margin = 11,
245 .hsync_len = 96,
246 .vsync_len = 2,
247 .vmode = FB_VMODE_NONINTERLACED
248};
249
250/* from GGI */
251static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, /* 0x40 */
264 },
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
266 0xFF},
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
268 0xEB /* MISC */
269};
270
271/*
272 * Backlight control
273 */
274#ifdef CONFIG_PMAC_BACKLIGHT
275
276static int riva_backlight_levels[] = {
277 0x158,
278 0x192,
279 0x1c6,
280 0x200,
281 0x234,
282 0x268,
283 0x2a2,
284 0x2d6,
285 0x310,
286 0x344,
287 0x378,
288 0x3b2,
289 0x3e6,
290 0x41a,
291 0x454,
292 0x534,
293};
294
295static int riva_set_backlight_enable(int on, int level, void *data);
296static int riva_set_backlight_level(int level, void *data);
297static struct backlight_controller riva_backlight_controller = {
298 riva_set_backlight_enable,
299 riva_set_backlight_level
300};
301#endif /* CONFIG_PMAC_BACKLIGHT */
302
303/* ------------------------------------------------------------------------- *
304 *
305 * MMIO access macros
306 *
307 * ------------------------------------------------------------------------- */
308
309static inline void CRTCout(struct riva_par *par, unsigned char index,
310 unsigned char val)
311{
312 VGA_WR08(par->riva.PCIO, 0x3d4, index);
313 VGA_WR08(par->riva.PCIO, 0x3d5, val);
314}
315
316static inline unsigned char CRTCin(struct riva_par *par,
317 unsigned char index)
318{
319 VGA_WR08(par->riva.PCIO, 0x3d4, index);
320 return (VGA_RD08(par->riva.PCIO, 0x3d5));
321}
322
323static inline void GRAout(struct riva_par *par, unsigned char index,
324 unsigned char val)
325{
326 VGA_WR08(par->riva.PVIO, 0x3ce, index);
327 VGA_WR08(par->riva.PVIO, 0x3cf, val);
328}
329
330static inline unsigned char GRAin(struct riva_par *par,
331 unsigned char index)
332{
333 VGA_WR08(par->riva.PVIO, 0x3ce, index);
334 return (VGA_RD08(par->riva.PVIO, 0x3cf));
335}
336
337static inline void SEQout(struct riva_par *par, unsigned char index,
338 unsigned char val)
339{
340 VGA_WR08(par->riva.PVIO, 0x3c4, index);
341 VGA_WR08(par->riva.PVIO, 0x3c5, val);
342}
343
344static inline unsigned char SEQin(struct riva_par *par,
345 unsigned char index)
346{
347 VGA_WR08(par->riva.PVIO, 0x3c4, index);
348 return (VGA_RD08(par->riva.PVIO, 0x3c5));
349}
350
351static inline void ATTRout(struct riva_par *par, unsigned char index,
352 unsigned char val)
353{
354 VGA_WR08(par->riva.PCIO, 0x3c0, index);
355 VGA_WR08(par->riva.PCIO, 0x3c0, val);
356}
357
358static inline unsigned char ATTRin(struct riva_par *par,
359 unsigned char index)
360{
361 VGA_WR08(par->riva.PCIO, 0x3c0, index);
362 return (VGA_RD08(par->riva.PCIO, 0x3c1));
363}
364
365static inline void MISCout(struct riva_par *par, unsigned char val)
366{
367 VGA_WR08(par->riva.PVIO, 0x3c2, val);
368}
369
370static inline unsigned char MISCin(struct riva_par *par)
371{
372 return (VGA_RD08(par->riva.PVIO, 0x3cc));
373}
374
375static u8 byte_rev[256] = {
376 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
377 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
378 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
379 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
380 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
381 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
382 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
383 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
384 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
385 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
386 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
387 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
388 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
389 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
390 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
391 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
392 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
393 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
394 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
395 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
396 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
397 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
398 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
399 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
400 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
401 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
402 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
403 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
404 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
405 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
406 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
407 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
408};
409
410static inline void reverse_order(u32 *l)
411{
412 u8 *a = (u8 *)l;
413 *a = byte_rev[*a], a++;
414 *a = byte_rev[*a], a++;
415 *a = byte_rev[*a], a++;
416 *a = byte_rev[*a];
417}
418
419/* ------------------------------------------------------------------------- *
420 *
421 * cursor stuff
422 *
423 * ------------------------------------------------------------------------- */
424
425/**
426 * rivafb_load_cursor_image - load cursor image to hardware
427 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
428 * @par: pointer to private data
429 * @w: width of cursor image in pixels
430 * @h: height of cursor image in scanlines
431 * @bg: background color (ARGB1555) - alpha bit determines opacity
432 * @fg: foreground color (ARGB1555)
433 *
434 * DESCRIPTiON:
435 * Loads cursor image based on a monochrome source and mask bitmap. The
436 * image bits determines the color of the pixel, 0 for background, 1 for
437 * foreground. Only the affected region (as determined by @w and @h
438 * parameters) will be updated.
439 *
440 * CALLED FROM:
441 * rivafb_cursor()
442 */
443static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
444 u16 bg, u16 fg, u32 w, u32 h)
445{
446 int i, j, k = 0;
447 u32 b, tmp;
448 u32 *data = (u32 *)data8;
449 bg = le16_to_cpu(bg);
450 fg = le16_to_cpu(fg);
451
452 w = (w + 1) & ~1;
453
454 for (i = 0; i < h; i++) {
455 b = *data++;
456 reverse_order(&b);
457
458 for (j = 0; j < w/2; j++) {
459 tmp = 0;
460#if defined (__BIG_ENDIAN)
461 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
462 b <<= 1;
463 tmp |= (b & (1 << 31)) ? fg : bg;
464 b <<= 1;
465#else
466 tmp = (b & 1) ? fg : bg;
467 b >>= 1;
468 tmp |= (b & 1) ? fg << 16 : bg << 16;
469 b >>= 1;
470#endif
471 writel(tmp, &par->riva.CURSOR[k++]);
472 }
473 k += (MAX_CURS - w)/2;
474 }
475}
476
477/* ------------------------------------------------------------------------- *
478 *
479 * general utility functions
480 *
481 * ------------------------------------------------------------------------- */
482
483/**
484 * riva_wclut - set CLUT entry
485 * @chip: pointer to RIVA_HW_INST object
486 * @regnum: register number
487 * @red: red component
488 * @green: green component
489 * @blue: blue component
490 *
491 * DESCRIPTION:
492 * Sets color register @regnum.
493 *
494 * CALLED FROM:
495 * rivafb_setcolreg()
496 */
497static void riva_wclut(RIVA_HW_INST *chip,
498 unsigned char regnum, unsigned char red,
499 unsigned char green, unsigned char blue)
500{
501 VGA_WR08(chip->PDIO, 0x3c8, regnum);
502 VGA_WR08(chip->PDIO, 0x3c9, red);
503 VGA_WR08(chip->PDIO, 0x3c9, green);
504 VGA_WR08(chip->PDIO, 0x3c9, blue);
505}
506
507/**
508 * riva_rclut - read fromCLUT register
509 * @chip: pointer to RIVA_HW_INST object
510 * @regnum: register number
511 * @red: red component
512 * @green: green component
513 * @blue: blue component
514 *
515 * DESCRIPTION:
516 * Reads red, green, and blue from color register @regnum.
517 *
518 * CALLED FROM:
519 * rivafb_setcolreg()
520 */
521static void riva_rclut(RIVA_HW_INST *chip,
522 unsigned char regnum, unsigned char *red,
523 unsigned char *green, unsigned char *blue)
524{
525
526 VGA_WR08(chip->PDIO, 0x3c7, regnum);
527 *red = VGA_RD08(chip->PDIO, 0x3c9);
528 *green = VGA_RD08(chip->PDIO, 0x3c9);
529 *blue = VGA_RD08(chip->PDIO, 0x3c9);
530}
531
532/**
533 * riva_save_state - saves current chip state
534 * @par: pointer to riva_par object containing info for current riva board
535 * @regs: pointer to riva_regs object
536 *
537 * DESCRIPTION:
538 * Saves current chip state to @regs.
539 *
540 * CALLED FROM:
541 * rivafb_probe()
542 */
543/* from GGI */
544static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
545{
546 int i;
547
548 NVTRACE_ENTER();
549 par->riva.LockUnlock(&par->riva, 0);
550
551 par->riva.UnloadStateExt(&par->riva, ®s->ext);
552
553 regs->misc_output = MISCin(par);
554
555 for (i = 0; i < NUM_CRT_REGS; i++)
556 regs->crtc[i] = CRTCin(par, i);
557
558 for (i = 0; i < NUM_ATC_REGS; i++)
559 regs->attr[i] = ATTRin(par, i);
560
561 for (i = 0; i < NUM_GRC_REGS; i++)
562 regs->gra[i] = GRAin(par, i);
563
564 for (i = 0; i < NUM_SEQ_REGS; i++)
565 regs->seq[i] = SEQin(par, i);
566 NVTRACE_LEAVE();
567}
568
569/**
570 * riva_load_state - loads current chip state
571 * @par: pointer to riva_par object containing info for current riva board
572 * @regs: pointer to riva_regs object
573 *
574 * DESCRIPTION:
575 * Loads chip state from @regs.
576 *
577 * CALLED FROM:
578 * riva_load_video_mode()
579 * rivafb_probe()
580 * rivafb_remove()
581 */
582/* from GGI */
583static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
584{
585 RIVA_HW_STATE *state = ®s->ext;
586 int i;
587
588 NVTRACE_ENTER();
589 CRTCout(par, 0x11, 0x00);
590
591 par->riva.LockUnlock(&par->riva, 0);
592
593 par->riva.LoadStateExt(&par->riva, state);
594
595 MISCout(par, regs->misc_output);
596
597 for (i = 0; i < NUM_CRT_REGS; i++) {
598 switch (i) {
599 case 0x19:
600 case 0x20 ... 0x40:
601 break;
602 default:
603 CRTCout(par, i, regs->crtc[i]);
604 }
605 }
606
607 for (i = 0; i < NUM_ATC_REGS; i++)
608 ATTRout(par, i, regs->attr[i]);
609
610 for (i = 0; i < NUM_GRC_REGS; i++)
611 GRAout(par, i, regs->gra[i]);
612
613 for (i = 0; i < NUM_SEQ_REGS; i++)
614 SEQout(par, i, regs->seq[i]);
615 NVTRACE_LEAVE();
616}
617
618/**
619 * riva_load_video_mode - calculate timings
620 * @info: pointer to fb_info object containing info for current riva board
621 *
622 * DESCRIPTION:
623 * Calculate some timings and then send em off to riva_load_state().
624 *
625 * CALLED FROM:
626 * rivafb_set_par()
627 */
628static void riva_load_video_mode(struct fb_info *info)
629{
630 int bpp, width, hDisplaySize, hDisplay, hStart,
631 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
632 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
633 struct riva_par *par = info->par;
634 struct riva_regs newmode;
635
636 NVTRACE_ENTER();
637 /* time to calculate */
638 rivafb_blank(1, info);
639
640 bpp = info->var.bits_per_pixel;
641 if (bpp == 16 && info->var.green.length == 5)
642 bpp = 15;
643 width = info->var.xres_virtual;
644 hDisplaySize = info->var.xres;
645 hDisplay = (hDisplaySize / 8) - 1;
646 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
647 hEnd = (hDisplaySize + info->var.right_margin +
648 info->var.hsync_len) / 8 - 1;
649 hTotal = (hDisplaySize + info->var.right_margin +
650 info->var.hsync_len + info->var.left_margin) / 8 - 5;
651 hBlankStart = hDisplay;
652 hBlankEnd = hTotal + 4;
653
654 height = info->var.yres_virtual;
655 vDisplay = info->var.yres - 1;
656 vStart = info->var.yres + info->var.lower_margin - 1;
657 vEnd = info->var.yres + info->var.lower_margin +
658 info->var.vsync_len - 1;
659 vTotal = info->var.yres + info->var.lower_margin +
660 info->var.vsync_len + info->var.upper_margin + 2;
661 vBlankStart = vDisplay;
662 vBlankEnd = vTotal + 1;
663 dotClock = 1000000000 / info->var.pixclock;
664
665 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
666
667 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
668 vTotal |= 1;
669
670 if (par->FlatPanel) {
671 vStart = vTotal - 3;
672 vEnd = vTotal - 2;
673 vBlankStart = vStart;
674 hStart = hTotal - 3;
675 hEnd = hTotal - 2;
676 hBlankEnd = hTotal + 4;
677 }
678
679 newmode.crtc[0x0] = Set8Bits (hTotal);
680 newmode.crtc[0x1] = Set8Bits (hDisplay);
681 newmode.crtc[0x2] = Set8Bits (hBlankStart);
682 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
683 newmode.crtc[0x4] = Set8Bits (hStart);
684 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
685 | SetBitField (hEnd, 4: 0, 4:0);
686 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
687 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
688 | SetBitField (vDisplay, 8: 8, 1:1)
689 | SetBitField (vStart, 8: 8, 2:2)
690 | SetBitField (vBlankStart, 8: 8, 3:3)
691 | SetBit (4)
692 | SetBitField (vTotal, 9: 9, 5:5)
693 | SetBitField (vDisplay, 9: 9, 6:6)
694 | SetBitField (vStart, 9: 9, 7:7);
695 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
696 | SetBit (6);
697 newmode.crtc[0x10] = Set8Bits (vStart);
698 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
699 | SetBit (5);
700 newmode.crtc[0x12] = Set8Bits (vDisplay);
701 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
702 newmode.crtc[0x15] = Set8Bits (vBlankStart);
703 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
704
705 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
706 | SetBitField(vBlankStart,10:10,3:3)
707 | SetBitField(vStart,10:10,2:2)
708 | SetBitField(vDisplay,10:10,1:1)
709 | SetBitField(vTotal,10:10,0:0);
710 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
711 | SetBitField(hDisplay,8:8,1:1)
712 | SetBitField(hBlankStart,8:8,2:2)
713 | SetBitField(hStart,8:8,3:3);
714 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
715 | SetBitField(vDisplay,11:11,2:2)
716 | SetBitField(vStart,11:11,4:4)
717 | SetBitField(vBlankStart,11:11,6:6);
718
719 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
720 int tmp = (hTotal >> 1) & ~1;
721 newmode.ext.interlace = Set8Bits(tmp);
722 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
723 } else
724 newmode.ext.interlace = 0xff; /* interlace off */
725
726 if (par->riva.Architecture >= NV_ARCH_10)
727 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
728
729 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
730 newmode.misc_output &= ~0x40;
731 else
732 newmode.misc_output |= 0x40;
733 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
734 newmode.misc_output &= ~0x80;
735 else
736 newmode.misc_output |= 0x80;
737
738 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
739 hDisplaySize, height, dotClock);
740
741 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
742 0xfff000ff;
743 if (par->FlatPanel == 1) {
744 newmode.ext.pixel |= (1 << 7);
745 newmode.ext.scale |= (1 << 8);
746 }
747 if (par->SecondCRTC) {
748 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
749 ~0x00001000;
750 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
751 0x00001000;
752 newmode.ext.crtcOwner = 3;
753 newmode.ext.pllsel |= 0x20000800;
754 newmode.ext.vpll2 = newmode.ext.vpll;
755 } else if (par->riva.twoHeads) {
756 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
757 0x00001000;
758 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
759 ~0x00001000;
760 newmode.ext.crtcOwner = 0;
761 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
762 }
763 if (par->FlatPanel == 1) {
764 newmode.ext.pixel |= (1 << 7);
765 newmode.ext.scale |= (1 << 8);
766 }
767 newmode.ext.cursorConfig = 0x02000100;
768 par->current_state = newmode;
769 riva_load_state(par, &par->current_state);
770 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
771 rivafb_blank(0, info);
772 NVTRACE_LEAVE();
773}
774
775static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
776{
777 NVTRACE_ENTER();
778 var->xres = var->xres_virtual = modedb->xres;
779 var->yres = modedb->yres;
780 if (var->yres_virtual < var->yres)
781 var->yres_virtual = var->yres;
782 var->xoffset = var->yoffset = 0;
783 var->pixclock = modedb->pixclock;
784 var->left_margin = modedb->left_margin;
785 var->right_margin = modedb->right_margin;
786 var->upper_margin = modedb->upper_margin;
787 var->lower_margin = modedb->lower_margin;
788 var->hsync_len = modedb->hsync_len;
789 var->vsync_len = modedb->vsync_len;
790 var->sync = modedb->sync;
791 var->vmode = modedb->vmode;
792 NVTRACE_LEAVE();
793}
794
795/**
796 * rivafb_do_maximize -
797 * @info: pointer to fb_info object containing info for current riva board
798 * @var:
799 * @nom:
800 * @den:
801 *
802 * DESCRIPTION:
803 * .
804 *
805 * RETURNS:
806 * -EINVAL on failure, 0 on success
807 *
808 *
809 * CALLED FROM:
810 * rivafb_check_var()
811 */
812static int rivafb_do_maximize(struct fb_info *info,
813 struct fb_var_screeninfo *var,
814 int nom, int den)
815{
816 static struct {
817 int xres, yres;
818 } modes[] = {
819 {1600, 1280},
820 {1280, 1024},
821 {1024, 768},
822 {800, 600},
823 {640, 480},
824 {-1, -1}
825 };
826 int i;
827
828 NVTRACE_ENTER();
829 /* use highest possible virtual resolution */
830 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
831 printk(KERN_WARNING PFX
832 "using maximum available virtual resolution\n");
833 for (i = 0; modes[i].xres != -1; i++) {
834 if (modes[i].xres * nom / den * modes[i].yres <
835 info->fix.smem_len)
836 break;
837 }
838 if (modes[i].xres == -1) {
839 printk(KERN_ERR PFX
840 "could not find a virtual resolution that fits into video memory!!\n");
841 NVTRACE("EXIT - EINVAL error\n");
842 return -EINVAL;
843 }
844 var->xres_virtual = modes[i].xres;
845 var->yres_virtual = modes[i].yres;
846
847 printk(KERN_INFO PFX
848 "virtual resolution set to maximum of %dx%d\n",
849 var->xres_virtual, var->yres_virtual);
850 } else if (var->xres_virtual == -1) {
851 var->xres_virtual = (info->fix.smem_len * den /
852 (nom * var->yres_virtual)) & ~15;
853 printk(KERN_WARNING PFX
854 "setting virtual X resolution to %d\n", var->xres_virtual);
855 } else if (var->yres_virtual == -1) {
856 var->xres_virtual = (var->xres_virtual + 15) & ~15;
857 var->yres_virtual = info->fix.smem_len * den /
858 (nom * var->xres_virtual);
859 printk(KERN_WARNING PFX
860 "setting virtual Y resolution to %d\n", var->yres_virtual);
861 } else {
862 var->xres_virtual = (var->xres_virtual + 15) & ~15;
863 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
864 printk(KERN_ERR PFX
865 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
866 var->xres, var->yres, var->bits_per_pixel);
867 NVTRACE("EXIT - EINVAL error\n");
868 return -EINVAL;
869 }
870 }
871
872 if (var->xres_virtual * nom / den >= 8192) {
873 printk(KERN_WARNING PFX
874 "virtual X resolution (%d) is too high, lowering to %d\n",
875 var->xres_virtual, 8192 * den / nom - 16);
876 var->xres_virtual = 8192 * den / nom - 16;
877 }
878
879 if (var->xres_virtual < var->xres) {
880 printk(KERN_ERR PFX
881 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
882 return -EINVAL;
883 }
884
885 if (var->yres_virtual < var->yres) {
886 printk(KERN_ERR PFX
887 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
888 return -EINVAL;
889 }
890 if (var->yres_virtual > 0x7fff/nom)
891 var->yres_virtual = 0x7fff/nom;
892 if (var->xres_virtual > 0x7fff/nom)
893 var->xres_virtual = 0x7fff/nom;
894 NVTRACE_LEAVE();
895 return 0;
896}
897
898static void
899riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
900{
901 RIVA_FIFO_FREE(par->riva, Patt, 4);
902 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
903 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
904 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
905 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
906}
907
908/* acceleration routines */
909static inline void wait_for_idle(struct riva_par *par)
910{
911 while (par->riva.Busy(&par->riva));
912}
913
914/*
915 * Set ROP. Translate X rop into ROP3. Internal routine.
916 */
917static void
918riva_set_rop_solid(struct riva_par *par, int rop)
919{
920 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
921 RIVA_FIFO_FREE(par->riva, Rop, 1);
922 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
923
924}
925
926static void riva_setup_accel(struct fb_info *info)
927{
928 struct riva_par *par = info->par;
929
930 RIVA_FIFO_FREE(par->riva, Clip, 2);
931 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
932 NV_WR32(&par->riva.Clip->WidthHeight, 0,
933 (info->var.xres_virtual & 0xffff) |
934 (info->var.yres_virtual << 16));
935 riva_set_rop_solid(par, 0xcc);
936 wait_for_idle(par);
937}
938
939/**
940 * riva_get_cmap_len - query current color map length
941 * @var: standard kernel fb changeable data
942 *
943 * DESCRIPTION:
944 * Get current color map length.
945 *
946 * RETURNS:
947 * Length of color map
948 *
949 * CALLED FROM:
950 * rivafb_setcolreg()
951 */
952static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
953{
954 int rc = 256; /* reasonable default */
955
956 switch (var->green.length) {
957 case 8:
958 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
959 break;
960 case 5:
961 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
962 break;
963 case 6:
964 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
965 break;
966 default:
967 /* should not occur */
968 break;
969 }
970 return rc;
971}
972
973/* ------------------------------------------------------------------------- *
974 *
975 * Backlight operations
976 *
977 * ------------------------------------------------------------------------- */
978
979#ifdef CONFIG_PMAC_BACKLIGHT
980static int riva_set_backlight_enable(int on, int level, void *data)
981{
982 struct riva_par *par = data;
983 U032 tmp_pcrt, tmp_pmc;
984
985 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
986 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
987 if(on && (level > BACKLIGHT_OFF)) {
988 tmp_pcrt |= 0x1;
989 tmp_pmc |= (1 << 31); // backlight bit
990 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
991 }
992 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
993 par->riva.PMC[0x10F0/4] = tmp_pmc;
994 return 0;
995}
996
997static int riva_set_backlight_level(int level, void *data)
998{
999 return riva_set_backlight_enable(1, level, data);
1000}
1001#endif /* CONFIG_PMAC_BACKLIGHT */
1002
1003/* ------------------------------------------------------------------------- *
1004 *
1005 * framebuffer operations
1006 *
1007 * ------------------------------------------------------------------------- */
1008
1009static int rivafb_open(struct fb_info *info, int user)
1010{
1011 struct riva_par *par = info->par;
1012 int cnt = atomic_read(&par->ref_count);
1013
1014 NVTRACE_ENTER();
1015 if (!cnt) {
1016#ifdef CONFIG_X86
1017 memset(&par->state, 0, sizeof(struct vgastate));
1018 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1019 /* save the DAC for Riva128 */
1020 if (par->riva.Architecture == NV_ARCH_03)
1021 par->state.flags |= VGA_SAVE_CMAP;
1022 save_vga(&par->state);
1023#endif
1024 /* vgaHWunlock() + riva unlock (0x7F) */
1025 CRTCout(par, 0x11, 0xFF);
1026 par->riva.LockUnlock(&par->riva, 0);
1027
1028 riva_save_state(par, &par->initial_state);
1029 }
1030 atomic_inc(&par->ref_count);
1031 NVTRACE_LEAVE();
1032 return 0;
1033}
1034
1035static int rivafb_release(struct fb_info *info, int user)
1036{
1037 struct riva_par *par = info->par;
1038 int cnt = atomic_read(&par->ref_count);
1039
1040 NVTRACE_ENTER();
1041 if (!cnt)
1042 return -EINVAL;
1043 if (cnt == 1) {
1044 par->riva.LockUnlock(&par->riva, 0);
1045 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1046 riva_load_state(par, &par->initial_state);
1047#ifdef CONFIG_X86
1048 restore_vga(&par->state);
1049#endif
1050 par->riva.LockUnlock(&par->riva, 1);
1051 }
1052 atomic_dec(&par->ref_count);
1053 NVTRACE_LEAVE();
1054 return 0;
1055}
1056
1057static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1058{
1059 struct fb_videomode *mode;
1060 struct riva_par *par = info->par;
1061 int nom, den; /* translating from pixels->bytes */
1062 int mode_valid = 0;
1063
1064 NVTRACE_ENTER();
1065 switch (var->bits_per_pixel) {
1066 case 1 ... 8:
1067 var->red.offset = var->green.offset = var->blue.offset = 0;
1068 var->red.length = var->green.length = var->blue.length = 8;
1069 var->bits_per_pixel = 8;
1070 nom = den = 1;
1071 break;
1072 case 9 ... 15:
1073 var->green.length = 5;
1074 /* fall through */
1075 case 16:
1076 var->bits_per_pixel = 16;
1077 /* The Riva128 supports RGB555 only */
1078 if (par->riva.Architecture == NV_ARCH_03)
1079 var->green.length = 5;
1080 if (var->green.length == 5) {
1081 /* 0rrrrrgg gggbbbbb */
1082 var->red.offset = 10;
1083 var->green.offset = 5;
1084 var->blue.offset = 0;
1085 var->red.length = 5;
1086 var->green.length = 5;
1087 var->blue.length = 5;
1088 } else {
1089 /* rrrrrggg gggbbbbb */
1090 var->red.offset = 11;
1091 var->green.offset = 5;
1092 var->blue.offset = 0;
1093 var->red.length = 5;
1094 var->green.length = 6;
1095 var->blue.length = 5;
1096 }
1097 nom = 2;
1098 den = 1;
1099 break;
1100 case 17 ... 32:
1101 var->red.length = var->green.length = var->blue.length = 8;
1102 var->bits_per_pixel = 32;
1103 var->red.offset = 16;
1104 var->green.offset = 8;
1105 var->blue.offset = 0;
1106 nom = 4;
1107 den = 1;
1108 break;
1109 default:
1110 printk(KERN_ERR PFX
1111 "mode %dx%dx%d rejected...color depth not supported.\n",
1112 var->xres, var->yres, var->bits_per_pixel);
1113 NVTRACE("EXIT, returning -EINVAL\n");
1114 return -EINVAL;
1115 }
1116
1117 if (!strictmode) {
1118 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1119 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1120 mode_valid = 1;
1121 }
1122
1123 /* calculate modeline if supported by monitor */
1124 if (!mode_valid && info->monspecs.gtf) {
1125 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1126 mode_valid = 1;
1127 }
1128
1129 if (!mode_valid) {
1130 mode = fb_find_best_mode(var, &info->modelist);
1131 if (mode) {
1132 riva_update_var(var, mode);
1133 mode_valid = 1;
1134 }
1135 }
1136
1137 if (!mode_valid && info->monspecs.modedb_len)
1138 return -EINVAL;
1139
1140 if (var->xres_virtual < var->xres)
1141 var->xres_virtual = var->xres;
1142 if (var->yres_virtual <= var->yres)
1143 var->yres_virtual = -1;
1144 if (rivafb_do_maximize(info, var, nom, den) < 0)
1145 return -EINVAL;
1146
1147 if (var->xoffset < 0)
1148 var->xoffset = 0;
1149 if (var->yoffset < 0)
1150 var->yoffset = 0;
1151
1152 /* truncate xoffset and yoffset to maximum if too high */
1153 if (var->xoffset > var->xres_virtual - var->xres)
1154 var->xoffset = var->xres_virtual - var->xres - 1;
1155
1156 if (var->yoffset > var->yres_virtual - var->yres)
1157 var->yoffset = var->yres_virtual - var->yres - 1;
1158
1159 var->red.msb_right =
1160 var->green.msb_right =
1161 var->blue.msb_right =
1162 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1163 NVTRACE_LEAVE();
1164 return 0;
1165}
1166
1167static int rivafb_set_par(struct fb_info *info)
1168{
1169 struct riva_par *par = info->par;
1170
1171 NVTRACE_ENTER();
1172 /* vgaHWunlock() + riva unlock (0x7F) */
1173 CRTCout(par, 0x11, 0xFF);
1174 par->riva.LockUnlock(&par->riva, 0);
1175 riva_load_video_mode(info);
1176 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1177 riva_setup_accel(info);
1178
1179 par->cursor_reset = 1;
1180 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1181 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1182 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1183
1184 if (info->flags & FBINFO_HWACCEL_DISABLED)
1185 info->pixmap.scan_align = 1;
1186 else
1187 info->pixmap.scan_align = 4;
1188 NVTRACE_LEAVE();
1189 return 0;
1190}
1191
1192/**
1193 * rivafb_pan_display
1194 * @var: standard kernel fb changeable data
1195 * @con: TODO
1196 * @info: pointer to fb_info object containing info for current riva board
1197 *
1198 * DESCRIPTION:
1199 * Pan (or wrap, depending on the `vmode' field) the display using the
1200 * `xoffset' and `yoffset' fields of the `var' structure.
1201 * If the values don't fit, return -EINVAL.
1202 *
1203 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1204 */
1205static int rivafb_pan_display(struct fb_var_screeninfo *var,
1206 struct fb_info *info)
1207{
1208 struct riva_par *par = info->par;
1209 unsigned int base;
1210
1211 NVTRACE_ENTER();
1212 base = var->yoffset * info->fix.line_length + var->xoffset;
1213 par->riva.SetStartAddress(&par->riva, base);
1214 NVTRACE_LEAVE();
1215 return 0;
1216}
1217
1218static int rivafb_blank(int blank, struct fb_info *info)
1219{
1220 struct riva_par *par= info->par;
1221 unsigned char tmp, vesa;
1222
1223 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1224 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1225
1226 NVTRACE_ENTER();
1227
1228 if (blank)
1229 tmp |= 0x20;
1230
1231 switch (blank) {
1232 case FB_BLANK_UNBLANK:
1233 case FB_BLANK_NORMAL:
1234 break;
1235 case FB_BLANK_VSYNC_SUSPEND:
1236 vesa |= 0x80;
1237 break;
1238 case FB_BLANK_HSYNC_SUSPEND:
1239 vesa |= 0x40;
1240 break;
1241 case FB_BLANK_POWERDOWN:
1242 vesa |= 0xc0;
1243 break;
1244 }
1245
1246 SEQout(par, 0x01, tmp);
1247 CRTCout(par, 0x1a, vesa);
1248
1249#ifdef CONFIG_PMAC_BACKLIGHT
1250 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1251 set_backlight_enable(!blank);
1252 }
1253#endif
1254
1255 NVTRACE_LEAVE();
1256
1257 return 0;
1258}
1259
1260/**
1261 * rivafb_setcolreg
1262 * @regno: register index
1263 * @red: red component
1264 * @green: green component
1265 * @blue: blue component
1266 * @transp: transparency
1267 * @info: pointer to fb_info object containing info for current riva board
1268 *
1269 * DESCRIPTION:
1270 * Set a single color register. The values supplied have a 16 bit
1271 * magnitude.
1272 *
1273 * RETURNS:
1274 * Return != 0 for invalid regno.
1275 *
1276 * CALLED FROM:
1277 * fbcmap.c:fb_set_cmap()
1278 */
1279static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1280 unsigned blue, unsigned transp,
1281 struct fb_info *info)
1282{
1283 struct riva_par *par = info->par;
1284 RIVA_HW_INST *chip = &par->riva;
1285 int i;
1286
1287 if (regno >= riva_get_cmap_len(&info->var))
1288 return -EINVAL;
1289
1290 if (info->var.grayscale) {
1291 /* gray = 0.30*R + 0.59*G + 0.11*B */
1292 red = green = blue =
1293 (red * 77 + green * 151 + blue * 28) >> 8;
1294 }
1295
1296 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1297 ((u32 *) info->pseudo_palette)[regno] =
1298 (regno << info->var.red.offset) |
1299 (regno << info->var.green.offset) |
1300 (regno << info->var.blue.offset);
1301 /*
1302 * The Riva128 2D engine requires color information in
1303 * TrueColor format even if framebuffer is in DirectColor
1304 */
1305 if (par->riva.Architecture == NV_ARCH_03) {
1306 switch (info->var.bits_per_pixel) {
1307 case 16:
1308 par->palette[regno] = ((red & 0xf800) >> 1) |
1309 ((green & 0xf800) >> 6) |
1310 ((blue & 0xf800) >> 11);
1311 break;
1312 case 32:
1313 par->palette[regno] = ((red & 0xff00) << 8) |
1314 ((green & 0xff00)) |
1315 ((blue & 0xff00) >> 8);
1316 break;
1317 }
1318 }
1319 }
1320
1321 switch (info->var.bits_per_pixel) {
1322 case 8:
1323 /* "transparent" stuff is completely ignored. */
1324 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1325 break;
1326 case 16:
1327 if (info->var.green.length == 5) {
1328 for (i = 0; i < 8; i++) {
1329 riva_wclut(chip, regno*8+i, red >> 8,
1330 green >> 8, blue >> 8);
1331 }
1332 } else {
1333 u8 r, g, b;
1334
1335 if (regno < 32) {
1336 for (i = 0; i < 8; i++) {
1337 riva_wclut(chip, regno*8+i,
1338 red >> 8, green >> 8,
1339 blue >> 8);
1340 }
1341 }
1342 riva_rclut(chip, regno*4, &r, &g, &b);
1343 for (i = 0; i < 4; i++)
1344 riva_wclut(chip, regno*4+i, r,
1345 green >> 8, b);
1346 }
1347 break;
1348 case 32:
1349 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1350 break;
1351 default:
1352 /* do nothing */
1353 break;
1354 }
1355 return 0;
1356}
1357
1358/**
1359 * rivafb_fillrect - hardware accelerated color fill function
1360 * @info: pointer to fb_info structure
1361 * @rect: pointer to fb_fillrect structure
1362 *
1363 * DESCRIPTION:
1364 * This function fills up a region of framebuffer memory with a solid
1365 * color with a choice of two different ROP's, copy or invert.
1366 *
1367 * CALLED FROM:
1368 * framebuffer hook
1369 */
1370static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1371{
1372 struct riva_par *par = info->par;
1373 u_int color, rop = 0;
1374
1375 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1376 cfb_fillrect(info, rect);
1377 return;
1378 }
1379
1380 if (info->var.bits_per_pixel == 8)
1381 color = rect->color;
1382 else {
1383 if (par->riva.Architecture != NV_ARCH_03)
1384 color = ((u32 *)info->pseudo_palette)[rect->color];
1385 else
1386 color = par->palette[rect->color];
1387 }
1388
1389 switch (rect->rop) {
1390 case ROP_XOR:
1391 rop = 0x66;
1392 break;
1393 case ROP_COPY:
1394 default:
1395 rop = 0xCC;
1396 break;
1397 }
1398
1399 riva_set_rop_solid(par, rop);
1400
1401 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1402 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1403
1404 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1405 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1406 (rect->dx << 16) | rect->dy);
1407 mb();
1408 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1409 (rect->width << 16) | rect->height);
1410 mb();
1411 riva_set_rop_solid(par, 0xcc);
1412
1413}
1414
1415/**
1416 * rivafb_copyarea - hardware accelerated blit function
1417 * @info: pointer to fb_info structure
1418 * @region: pointer to fb_copyarea structure
1419 *
1420 * DESCRIPTION:
1421 * This copies an area of pixels from one location to another
1422 *
1423 * CALLED FROM:
1424 * framebuffer hook
1425 */
1426static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1427{
1428 struct riva_par *par = info->par;
1429
1430 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1431 cfb_copyarea(info, region);
1432 return;
1433 }
1434
1435 RIVA_FIFO_FREE(par->riva, Blt, 3);
1436 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1437 (region->sy << 16) | region->sx);
1438 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1439 (region->dy << 16) | region->dx);
1440 mb();
1441 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1442 (region->height << 16) | region->width);
1443 mb();
1444}
1445
1446static inline void convert_bgcolor_16(u32 *col)
1447{
1448 *col = ((*col & 0x0000F800) << 8)
1449 | ((*col & 0x00007E0) << 5)
1450 | ((*col & 0x0000001F) << 3)
1451 | 0xFF000000;
1452 mb();
1453}
1454
1455/**
1456 * rivafb_imageblit: hardware accelerated color expand function
1457 * @info: pointer to fb_info structure
1458 * @image: pointer to fb_image structure
1459 *
1460 * DESCRIPTION:
1461 * If the source is a monochrome bitmap, the function fills up a a region
1462 * of framebuffer memory with pixels whose color is determined by the bit
1463 * setting of the bitmap, 1 - foreground, 0 - background.
1464 *
1465 * If the source is not a monochrome bitmap, color expansion is not done.
1466 * In this case, it is channeled to a software function.
1467 *
1468 * CALLED FROM:
1469 * framebuffer hook
1470 */
1471static void rivafb_imageblit(struct fb_info *info,
1472 const struct fb_image *image)
1473{
1474 struct riva_par *par = info->par;
1475 u32 fgx = 0, bgx = 0, width, tmp;
1476 u8 *cdat = (u8 *) image->data;
1477 volatile u32 __iomem *d;
1478 int i, size;
1479
1480 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1481 cfb_imageblit(info, image);
1482 return;
1483 }
1484
1485 switch (info->var.bits_per_pixel) {
1486 case 8:
1487 fgx = image->fg_color;
1488 bgx = image->bg_color;
1489 break;
1490 case 16:
1491 case 32:
1492 if (par->riva.Architecture != NV_ARCH_03) {
1493 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1494 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1495 } else {
1496 fgx = par->palette[image->fg_color];
1497 bgx = par->palette[image->bg_color];
1498 }
1499 if (info->var.green.length == 6)
1500 convert_bgcolor_16(&bgx);
1501 break;
1502 }
1503
1504 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1505 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1506 (image->dy << 16) | (image->dx & 0xFFFF));
1507 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1508 (((image->dy + image->height) << 16) |
1509 ((image->dx + image->width) & 0xffff)));
1510 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1511 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1512 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1513 (image->height << 16) | ((image->width + 31) & ~31));
1514 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1515 (image->height << 16) | ((image->width + 31) & ~31));
1516 NV_WR32(&par->riva.Bitmap->PointE, 0,
1517 (image->dy << 16) | (image->dx & 0xFFFF));
1518
1519 d = &par->riva.Bitmap->MonochromeData01E;
1520
1521 width = (image->width + 31)/32;
1522 size = width * image->height;
1523 while (size >= 16) {
1524 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1525 for (i = 0; i < 16; i++) {
1526 tmp = *((u32 *)cdat);
1527 cdat = (u8 *)((u32 *)cdat + 1);
1528 reverse_order(&tmp);
1529 NV_WR32(d, i*4, tmp);
1530 }
1531 size -= 16;
1532 }
1533 if (size) {
1534 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1535 for (i = 0; i < size; i++) {
1536 tmp = *((u32 *) cdat);
1537 cdat = (u8 *)((u32 *)cdat + 1);
1538 reverse_order(&tmp);
1539 NV_WR32(d, i*4, tmp);
1540 }
1541 }
1542}
1543
1544/**
1545 * rivafb_cursor - hardware cursor function
1546 * @info: pointer to info structure
1547 * @cursor: pointer to fbcursor structure
1548 *
1549 * DESCRIPTION:
1550 * A cursor function that supports displaying a cursor image via hardware.
1551 * Within the kernel, copy and invert rops are supported. If exported
1552 * to user space, only the copy rop will be supported.
1553 *
1554 * CALLED FROM
1555 * framebuffer hook
1556 */
1557static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1558{
1559 struct riva_par *par = info->par;
1560 u8 data[MAX_CURS * MAX_CURS/8];
1561 int i, set = cursor->set;
1562 u16 fg, bg;
1563
1564 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1565 return -ENXIO;
1566
1567 par->riva.ShowHideCursor(&par->riva, 0);
1568
1569 if (par->cursor_reset) {
1570 set = FB_CUR_SETALL;
1571 par->cursor_reset = 0;
1572 }
1573
1574 if (set & FB_CUR_SETSIZE)
1575 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1576
1577 if (set & FB_CUR_SETPOS) {
1578 u32 xx, yy, temp;
1579
1580 yy = cursor->image.dy - info->var.yoffset;
1581 xx = cursor->image.dx - info->var.xoffset;
1582 temp = xx & 0xFFFF;
1583 temp |= yy << 16;
1584
1585 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1586 }
1587
1588
1589 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1590 u32 bg_idx = cursor->image.bg_color;
1591 u32 fg_idx = cursor->image.fg_color;
1592 u32 s_pitch = (cursor->image.width+7) >> 3;
1593 u32 d_pitch = MAX_CURS/8;
1594 u8 *dat = (u8 *) cursor->image.data;
1595 u8 *msk = (u8 *) cursor->mask;
1596 u8 *src;
1597
1598 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1599
1600 if (src) {
1601 switch (cursor->rop) {
1602 case ROP_XOR:
1603 for (i = 0; i < s_pitch * cursor->image.height; i++)
1604 src[i] = dat[i] ^ msk[i];
1605 break;
1606 case ROP_COPY:
1607 default:
1608 for (i = 0; i < s_pitch * cursor->image.height; i++)
1609 src[i] = dat[i] & msk[i];
1610 break;
1611 }
1612
1613 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1614 cursor->image.height);
1615
1616 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1617 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1618 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1619 1 << 15;
1620
1621 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1622 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1623 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1624 1 << 15;
1625
1626 par->riva.LockUnlock(&par->riva, 0);
1627
1628 rivafb_load_cursor_image(par, data, bg, fg,
1629 cursor->image.width,
1630 cursor->image.height);
1631 kfree(src);
1632 }
1633 }
1634
1635 if (cursor->enable)
1636 par->riva.ShowHideCursor(&par->riva, 1);
1637
1638 return 0;
1639}
1640
1641static int rivafb_sync(struct fb_info *info)
1642{
1643 struct riva_par *par = info->par;
1644
1645 wait_for_idle(par);
1646 return 0;
1647}
1648
1649/* ------------------------------------------------------------------------- *
1650 *
1651 * initialization helper functions
1652 *
1653 * ------------------------------------------------------------------------- */
1654
1655/* kernel interface */
1656static struct fb_ops riva_fb_ops = {
1657 .owner = THIS_MODULE,
1658 .fb_open = rivafb_open,
1659 .fb_release = rivafb_release,
1660 .fb_check_var = rivafb_check_var,
1661 .fb_set_par = rivafb_set_par,
1662 .fb_setcolreg = rivafb_setcolreg,
1663 .fb_pan_display = rivafb_pan_display,
1664 .fb_blank = rivafb_blank,
1665 .fb_fillrect = rivafb_fillrect,
1666 .fb_copyarea = rivafb_copyarea,
1667 .fb_imageblit = rivafb_imageblit,
1668 .fb_cursor = rivafb_cursor,
1669 .fb_sync = rivafb_sync,
1670};
1671
1672static int __devinit riva_set_fbinfo(struct fb_info *info)
1673{
1674 unsigned int cmap_len;
1675 struct riva_par *par = info->par;
1676
1677 NVTRACE_ENTER();
1678 info->flags = FBINFO_DEFAULT
1679 | FBINFO_HWACCEL_XPAN
1680 | FBINFO_HWACCEL_YPAN
1681 | FBINFO_HWACCEL_COPYAREA
1682 | FBINFO_HWACCEL_FILLRECT
1683 | FBINFO_HWACCEL_IMAGEBLIT;
1684
1685 /* Accel seems to not work properly on NV30 yet...*/
1686 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1687 printk(KERN_DEBUG PFX "disabling acceleration\n");
1688 info->flags |= FBINFO_HWACCEL_DISABLED;
1689 }
1690
1691 info->var = rivafb_default_var;
1692 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1693 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1694
1695 info->pseudo_palette = par->pseudo_palette;
1696
1697 cmap_len = riva_get_cmap_len(&info->var);
1698 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1699
1700 info->pixmap.size = 8 * 1024;
1701 info->pixmap.buf_align = 4;
1702 info->pixmap.access_align = 32;
1703 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1704 info->var.yres_virtual = -1;
1705 NVTRACE_LEAVE();
1706 return (rivafb_check_var(&info->var, info));
1707}
1708
1709#ifdef CONFIG_PPC_OF
1710static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1711{
1712 struct riva_par *par = info->par;
1713 struct device_node *dp;
1714 unsigned char *pedid = NULL;
1715 unsigned char *disptype = NULL;
1716 static char *propnames[] = {
1717 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1718 int i;
1719
1720 NVTRACE_ENTER();
1721 dp = pci_device_to_OF_node(pd);
1722 for (; dp != NULL; dp = dp->child) {
1723 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1724 if (disptype == NULL)
1725 continue;
1726 if (strncmp(disptype, "LCD", 3) != 0)
1727 continue;
1728 for (i = 0; propnames[i] != NULL; ++i) {
1729 pedid = (unsigned char *)
1730 get_property(dp, propnames[i], NULL);
1731 if (pedid != NULL) {
1732 par->EDID = pedid;
1733 NVTRACE("LCD found.\n");
1734 return 1;
1735 }
1736 }
1737 }
1738 NVTRACE_LEAVE();
1739 return 0;
1740}
1741#endif /* CONFIG_PPC_OF */
1742
1743#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1744static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1745{
1746 struct riva_par *par = info->par;
1747 struct fb_var_screeninfo var;
1748 int i;
1749
1750 NVTRACE_ENTER();
1751 riva_create_i2c_busses(par);
1752 for (i = 0; i < par->bus; i++) {
1753 riva_probe_i2c_connector(par, i+1, &par->EDID);
1754 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1755 printk(PFX "Found EDID Block from BUS %i\n", i);
1756 break;
1757 }
1758 }
1759
1760 NVTRACE_LEAVE();
1761 return (par->EDID) ? 1 : 0;
1762}
1763#endif /* CONFIG_FB_RIVA_I2C */
1764
1765static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1766 struct fb_info *info)
1767{
1768 struct fb_monspecs *specs = &info->monspecs;
1769 struct fb_videomode modedb;
1770
1771 NVTRACE_ENTER();
1772 /* respect mode options */
1773 if (mode_option) {
1774 fb_find_mode(var, info, mode_option,
1775 specs->modedb, specs->modedb_len,
1776 NULL, 8);
1777 } else if (specs->modedb != NULL) {
1778 /* get preferred timing */
1779 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1780 int i;
1781
1782 for (i = 0; i < specs->modedb_len; i++) {
1783 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1784 modedb = specs->modedb[i];
1785 break;
1786 }
1787 }
1788 } else {
1789 /* otherwise, get first mode in database */
1790 modedb = specs->modedb[0];
1791 }
1792 var->bits_per_pixel = 8;
1793 riva_update_var(var, &modedb);
1794 }
1795 NVTRACE_LEAVE();
1796}
1797
1798
1799static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1800{
1801 NVTRACE_ENTER();
1802#ifdef CONFIG_PPC_OF
1803 if (!riva_get_EDID_OF(info, pdev))
1804 printk(PFX "could not retrieve EDID from OF\n");
1805#elif defined(CONFIG_FB_RIVA_I2C)
1806 if (!riva_get_EDID_i2c(info))
1807 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1808#endif
1809 NVTRACE_LEAVE();
1810}
1811
1812
1813static void __devinit riva_get_edidinfo(struct fb_info *info)
1814{
1815 struct fb_var_screeninfo *var = &rivafb_default_var;
1816 struct riva_par *par = info->par;
1817
1818 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1819 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1820 &info->modelist);
1821 riva_update_default_var(var, info);
1822
1823 /* if user specified flatpanel, we respect that */
1824 if (info->monspecs.input & FB_DISP_DDI)
1825 par->FlatPanel = 1;
1826}
1827
1828/* ------------------------------------------------------------------------- *
1829 *
1830 * PCI bus
1831 *
1832 * ------------------------------------------------------------------------- */
1833
1834static u32 __devinit riva_get_arch(struct pci_dev *pd)
1835{
1836 u32 arch = 0;
1837
1838 switch (pd->device & 0x0ff0) {
1839 case 0x0100: /* GeForce 256 */
1840 case 0x0110: /* GeForce2 MX */
1841 case 0x0150: /* GeForce2 */
1842 case 0x0170: /* GeForce4 MX */
1843 case 0x0180: /* GeForce4 MX (8x AGP) */
1844 case 0x01A0: /* nForce */
1845 case 0x01F0: /* nForce2 */
1846 arch = NV_ARCH_10;
1847 break;
1848 case 0x0200: /* GeForce3 */
1849 case 0x0250: /* GeForce4 Ti */
1850 case 0x0280: /* GeForce4 Ti (8x AGP) */
1851 arch = NV_ARCH_20;
1852 break;
1853 case 0x0300: /* GeForceFX 5800 */
1854 case 0x0310: /* GeForceFX 5600 */
1855 case 0x0320: /* GeForceFX 5200 */
1856 case 0x0330: /* GeForceFX 5900 */
1857 case 0x0340: /* GeForceFX 5700 */
1858 arch = NV_ARCH_30;
1859 break;
1860 case 0x0020: /* TNT, TNT2 */
1861 arch = NV_ARCH_04;
1862 break;
1863 case 0x0010: /* Riva128 */
1864 arch = NV_ARCH_03;
1865 break;
1866 default: /* unknown architecture */
1867 break;
1868 }
1869 return arch;
1870}
1871
1872static int __devinit rivafb_probe(struct pci_dev *pd,
1873 const struct pci_device_id *ent)
1874{
1875 struct riva_par *default_par;
1876 struct fb_info *info;
1877 int ret;
1878
1879 NVTRACE_ENTER();
1880 assert(pd != NULL);
1881
1882 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1883 if (!info) {
1884 printk (KERN_ERR PFX "could not allocate memory\n");
1885 ret = -ENOMEM;
1886 goto err_ret;
1887 }
1888 default_par = info->par;
1889 default_par->pdev = pd;
1890
1891 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1892 if (info->pixmap.addr == NULL) {
1893 ret = -ENOMEM;
1894 goto err_framebuffer_release;
1895 }
1896 memset(info->pixmap.addr, 0, 8 * 1024);
1897
1898 ret = pci_enable_device(pd);
1899 if (ret < 0) {
1900 printk(KERN_ERR PFX "cannot enable PCI device\n");
1901 goto err_free_pixmap;
1902 }
1903
1904 ret = pci_request_regions(pd, "rivafb");
1905 if (ret < 0) {
1906 printk(KERN_ERR PFX "cannot request PCI regions\n");
1907 goto err_disable_device;
1908 }
1909
1910 default_par->riva.Architecture = riva_get_arch(pd);
1911
1912 default_par->Chipset = (pd->vendor << 16) | pd->device;
1913 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1914
1915 if(default_par->riva.Architecture == 0) {
1916 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1917 ret=-ENODEV;
1918 goto err_release_region;
1919 }
1920 if(default_par->riva.Architecture == NV_ARCH_10 ||
1921 default_par->riva.Architecture == NV_ARCH_20 ||
1922 default_par->riva.Architecture == NV_ARCH_30) {
1923 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1924 } else {
1925 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1926 }
1927
1928 default_par->FlatPanel = flatpanel;
1929 if (flatpanel == 1)
1930 printk(KERN_INFO PFX "flatpanel support enabled\n");
1931 default_par->forceCRTC = forceCRTC;
1932
1933 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1934 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1935
1936 {
1937 /* enable IO and mem if not already done */
1938 unsigned short cmd;
1939
1940 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1941 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1942 pci_write_config_word(pd, PCI_COMMAND, cmd);
1943 }
1944
1945 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1946 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1947
1948 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1949 rivafb_fix.mmio_len);
1950 if (!default_par->ctrl_base) {
1951 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1952 ret = -EIO;
1953 goto err_release_region;
1954 }
1955
1956 switch (default_par->riva.Architecture) {
1957 case NV_ARCH_03:
1958 /* Riva128's PRAMIN is in the "framebuffer" space
1959 * Since these cards were never made with more than 8 megabytes
1960 * we can safely allocate this separately.
1961 */
1962 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1963 if (!default_par->riva.PRAMIN) {
1964 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1965 ret = -EIO;
1966 goto err_iounmap_ctrl_base;
1967 }
1968 break;
1969 case NV_ARCH_04:
1970 case NV_ARCH_10:
1971 case NV_ARCH_20:
1972 case NV_ARCH_30:
1973 default_par->riva.PCRTC0 =
1974 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1975 default_par->riva.PRAMIN =
1976 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
1977 break;
1978 }
1979 riva_common_setup(default_par);
1980
1981 if (default_par->riva.Architecture == NV_ARCH_03) {
1982 default_par->riva.PCRTC = default_par->riva.PCRTC0
1983 = default_par->riva.PGRAPH;
1984 }
1985
1986 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
1987 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
1988 info->screen_base = ioremap(rivafb_fix.smem_start,
1989 rivafb_fix.smem_len);
1990 if (!info->screen_base) {
1991 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1992 ret = -EIO;
1993 goto err_iounmap_pramin;
1994 }
1995
1996#ifdef CONFIG_MTRR
1997 if (!nomtrr) {
1998 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
1999 rivafb_fix.smem_len,
2000 MTRR_TYPE_WRCOMB, 1);
2001 if (default_par->mtrr.vram < 0) {
2002 printk(KERN_ERR PFX "unable to setup MTRR\n");
2003 } else {
2004 default_par->mtrr.vram_valid = 1;
2005 /* let there be speed */
2006 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2007 }
2008 }
2009#endif /* CONFIG_MTRR */
2010
2011 info->fbops = &riva_fb_ops;
2012 info->fix = rivafb_fix;
2013 riva_get_EDID(info, pd);
2014 riva_get_edidinfo(info);
2015
2016 ret=riva_set_fbinfo(info);
2017 if (ret < 0) {
2018 printk(KERN_ERR PFX "error setting initial video mode\n");
2019 goto err_iounmap_screen_base;
2020 }
2021
2022 fb_destroy_modedb(info->monspecs.modedb);
2023 info->monspecs.modedb = NULL;
2024 ret = register_framebuffer(info);
2025 if (ret < 0) {
2026 printk(KERN_ERR PFX
2027 "error registering riva framebuffer\n");
2028 goto err_iounmap_screen_base;
2029 }
2030
2031 pci_set_drvdata(pd, info);
2032
2033 printk(KERN_INFO PFX
2034 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2035 info->fix.id,
2036 RIVAFB_VERSION,
2037 info->fix.smem_len / (1024 * 1024),
2038 info->fix.smem_start);
2039#ifdef CONFIG_PMAC_BACKLIGHT
2040 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2041 register_backlight_controller(&riva_backlight_controller,
2042 default_par, "mnca");
2043#endif
2044 NVTRACE_LEAVE();
2045 return 0;
2046
2047err_iounmap_screen_base:
2048#ifdef CONFIG_FB_RIVA_I2C
2049 riva_delete_i2c_busses(info->par);
2050#endif
2051 iounmap(info->screen_base);
2052err_iounmap_pramin:
2053 if (default_par->riva.Architecture == NV_ARCH_03)
2054 iounmap(default_par->riva.PRAMIN);
2055err_iounmap_ctrl_base:
2056 iounmap(default_par->ctrl_base);
2057err_release_region:
2058 pci_release_regions(pd);
2059err_disable_device:
2060 pci_disable_device(pd);
2061err_free_pixmap:
2062 kfree(info->pixmap.addr);
2063err_framebuffer_release:
2064 framebuffer_release(info);
2065err_ret:
2066 return ret;
2067}
2068
2069static void __exit rivafb_remove(struct pci_dev *pd)
2070{
2071 struct fb_info *info = pci_get_drvdata(pd);
2072 struct riva_par *par = info->par;
2073
2074 NVTRACE_ENTER();
2075 if (!info)
2076 return;
2077
2078#ifdef CONFIG_FB_RIVA_I2C
2079 riva_delete_i2c_busses(par);
2080 kfree(par->EDID);
2081#endif
2082
2083 unregister_framebuffer(info);
2084#ifdef CONFIG_MTRR
2085 if (par->mtrr.vram_valid)
2086 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2087 info->fix.smem_len);
2088#endif /* CONFIG_MTRR */
2089
2090 iounmap(par->ctrl_base);
2091 iounmap(info->screen_base);
2092 if (par->riva.Architecture == NV_ARCH_03)
2093 iounmap(par->riva.PRAMIN);
2094 pci_release_regions(pd);
2095 pci_disable_device(pd);
2096 kfree(info->pixmap.addr);
2097 framebuffer_release(info);
2098 pci_set_drvdata(pd, NULL);
2099 NVTRACE_LEAVE();
2100}
2101
2102/* ------------------------------------------------------------------------- *
2103 *
2104 * initialization
2105 *
2106 * ------------------------------------------------------------------------- */
2107
2108#ifndef MODULE
2109static int __init rivafb_setup(char *options)
2110{
2111 char *this_opt;
2112
2113 NVTRACE_ENTER();
2114 if (!options || !*options)
2115 return 0;
2116
2117 while ((this_opt = strsep(&options, ",")) != NULL) {
2118 if (!strncmp(this_opt, "forceCRTC", 9)) {
2119 char *p;
2120
2121 p = this_opt + 9;
2122 if (!*p || !*(++p)) continue;
2123 forceCRTC = *p - '0';
2124 if (forceCRTC < 0 || forceCRTC > 1)
2125 forceCRTC = -1;
2126 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2127 flatpanel = 1;
2128#ifdef CONFIG_MTRR
2129 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2130 nomtrr = 1;
2131#endif
2132 } else if (!strncmp(this_opt, "strictmode", 10)) {
2133 strictmode = 1;
2134 } else if (!strncmp(this_opt, "noaccel", 7)) {
2135 noaccel = 1;
2136 } else
2137 mode_option = this_opt;
2138 }
2139 NVTRACE_LEAVE();
2140 return 0;
2141}
2142#endif /* !MODULE */
2143
2144static struct pci_driver rivafb_driver = {
2145 .name = "rivafb",
2146 .id_table = rivafb_pci_tbl,
2147 .probe = rivafb_probe,
2148 .remove = __exit_p(rivafb_remove),
2149};
2150
2151
2152
2153/* ------------------------------------------------------------------------- *
2154 *
2155 * modularization
2156 *
2157 * ------------------------------------------------------------------------- */
2158
2159static int __devinit rivafb_init(void)
2160{
2161#ifndef MODULE
2162 char *option = NULL;
2163
2164 if (fb_get_options("rivafb", &option))
2165 return -ENODEV;
2166 rivafb_setup(option);
2167#endif
2168 return pci_register_driver(&rivafb_driver);
2169}
2170
2171
2172module_init(rivafb_init);
2173
2174#ifdef MODULE
2175static void __exit rivafb_exit(void)
2176{
2177 pci_unregister_driver(&rivafb_driver);
2178}
2179
2180module_exit(rivafb_exit);
2181#endif /* MODULE */
2182
2183module_param(noaccel, bool, 0);
2184MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2185module_param(flatpanel, int, 0);
2186MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2187module_param(forceCRTC, int, 0);
2188MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2189#ifdef CONFIG_MTRR
2190module_param(nomtrr, bool, 0);
2191MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2192#endif
2193module_param(strictmode, bool, 0);
2194MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2195
2196MODULE_AUTHOR("Ani Joshi, maintainer");
2197MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2198MODULE_LICENSE("GPL");