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1/* 2 * drivers/serial/mpc52xx_uart.c 3 * 4 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. 5 * 6 * FIXME According to the usermanual the status bits in the status register 7 * are only updated when the peripherals access the FIFO and not when the 8 * CPU access them. So since we use this bits to know when we stop writing 9 * and reading, they may not be updated in-time and a race condition may 10 * exists. But I haven't be able to prove this and I don't care. But if 11 * any problem arises, it might worth checking. The TX/RX FIFO Stats 12 * registers should be used in addition. 13 * Update: Actually, they seem updated ... At least the bits we use. 14 * 15 * 16 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 17 * 18 * Some of the code has been inspired/copied from the 2.4 code written 19 * by Dale Farnsworth <dfarnsworth@mvista.com>. 20 * 21 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> 22 * Copyright (C) 2003 MontaVista, Software, Inc. 23 * 24 * This file is licensed under the terms of the GNU General Public License 25 * version 2. This program is licensed "as is" without any warranty of any 26 * kind, whether express or implied. 27 */ 28 29/* Platform device Usage : 30 * 31 * Since PSCs can have multiple function, the correct driver for each one 32 * is selected by calling mpc52xx_match_psc_function(...). The function 33 * handled by this driver is "uart". 34 * 35 * The driver init all necessary registers to place the PSC in uart mode without 36 * DCD. However, the pin multiplexing aren't changed and should be set either 37 * by the bootloader or in the platform init code. 38 * 39 * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2, 40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and 41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly 42 * fpr the console code : without this 1:1 mapping, at early boot time, when we 43 * are parsing the kernel args console=ttyPSC?, we wouldn't know wich PSC it 44 * will be mapped to. 45 */ 46 47#include <linux/config.h> 48#include <linux/platform_device.h> 49#include <linux/module.h> 50#include <linux/tty.h> 51#include <linux/serial.h> 52#include <linux/sysrq.h> 53#include <linux/console.h> 54 55#include <asm/delay.h> 56#include <asm/io.h> 57 58#include <asm/mpc52xx.h> 59#include <asm/mpc52xx_psc.h> 60 61#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 62#define SUPPORT_SYSRQ 63#endif 64 65#include <linux/serial_core.h> 66 67 68/* We've been assigned a range on the "Low-density serial ports" major */ 69#define SERIAL_PSC_MAJOR 204 70#define SERIAL_PSC_MINOR 148 71 72 73#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ 74 75 76static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; 77 /* Rem: - We use the read_status_mask as a shadow of 78 * psc->mpc52xx_psc_imr 79 * - It's important that is array is all zero on start as we 80 * use it to know if it's initialized or not ! If it's not sure 81 * it's cleared, then a memset(...,0,...) should be added to 82 * the console_init 83 */ 84 85#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) 86 87 88/* Forward declaration of the interruption handling routine */ 89static irqreturn_t mpc52xx_uart_int(int irq,void *dev_id,struct pt_regs *regs); 90 91 92/* Simple macro to test if a port is console or not. This one is taken 93 * for serial_core.c and maybe should be moved to serial_core.h ? */ 94#ifdef CONFIG_SERIAL_CORE_CONSOLE 95#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line) 96#else 97#define uart_console(port) (0) 98#endif 99 100 101/* ======================================================================== */ 102/* UART operations */ 103/* ======================================================================== */ 104 105static unsigned int 106mpc52xx_uart_tx_empty(struct uart_port *port) 107{ 108 int status = in_be16(&PSC(port)->mpc52xx_psc_status); 109 return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; 110} 111 112static void 113mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 114{ 115 /* Not implemented */ 116} 117 118static unsigned int 119mpc52xx_uart_get_mctrl(struct uart_port *port) 120{ 121 /* Not implemented */ 122 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 123} 124 125static void 126mpc52xx_uart_stop_tx(struct uart_port *port) 127{ 128 /* port->lock taken by caller */ 129 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; 130 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); 131} 132 133static void 134mpc52xx_uart_start_tx(struct uart_port *port) 135{ 136 /* port->lock taken by caller */ 137 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 138 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); 139} 140 141static void 142mpc52xx_uart_send_xchar(struct uart_port *port, char ch) 143{ 144 unsigned long flags; 145 spin_lock_irqsave(&port->lock, flags); 146 147 port->x_char = ch; 148 if (ch) { 149 /* Make sure tx interrupts are on */ 150 /* Truly necessary ??? They should be anyway */ 151 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 152 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); 153 } 154 155 spin_unlock_irqrestore(&port->lock, flags); 156} 157 158static void 159mpc52xx_uart_stop_rx(struct uart_port *port) 160{ 161 /* port->lock taken by caller */ 162 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; 163 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); 164} 165 166static void 167mpc52xx_uart_enable_ms(struct uart_port *port) 168{ 169 /* Not implemented */ 170} 171 172static void 173mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 174{ 175 unsigned long flags; 176 spin_lock_irqsave(&port->lock, flags); 177 178 if ( ctl == -1 ) 179 out_8(&PSC(port)->command,MPC52xx_PSC_START_BRK); 180 else 181 out_8(&PSC(port)->command,MPC52xx_PSC_STOP_BRK); 182 183 spin_unlock_irqrestore(&port->lock, flags); 184} 185 186static int 187mpc52xx_uart_startup(struct uart_port *port) 188{ 189 struct mpc52xx_psc __iomem *psc = PSC(port); 190 int ret; 191 192 /* Request IRQ */ 193 ret = request_irq(port->irq, mpc52xx_uart_int, 194 SA_INTERRUPT | SA_SAMPLE_RANDOM, "mpc52xx_psc_uart", port); 195 if (ret) 196 return ret; 197 198 /* Reset/activate the port, clear and enable interrupts */ 199 out_8(&psc->command,MPC52xx_PSC_RST_RX); 200 out_8(&psc->command,MPC52xx_PSC_RST_TX); 201 202 out_be32(&psc->sicr,0); /* UART mode DCD ignored */ 203 204 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */ 205 206 out_8(&psc->rfcntl, 0x00); 207 out_be16(&psc->rfalarm, 0x1ff); 208 out_8(&psc->tfcntl, 0x07); 209 out_be16(&psc->tfalarm, 0x80); 210 211 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; 212 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask); 213 214 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE); 215 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE); 216 217 return 0; 218} 219 220static void 221mpc52xx_uart_shutdown(struct uart_port *port) 222{ 223 struct mpc52xx_psc __iomem *psc = PSC(port); 224 225 /* Shut down the port, interrupt and all */ 226 out_8(&psc->command,MPC52xx_PSC_RST_RX); 227 out_8(&psc->command,MPC52xx_PSC_RST_TX); 228 229 port->read_status_mask = 0; 230 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask); 231 232 /* Release interrupt */ 233 free_irq(port->irq, port); 234} 235 236static void 237mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new, 238 struct termios *old) 239{ 240 struct mpc52xx_psc __iomem *psc = PSC(port); 241 unsigned long flags; 242 unsigned char mr1, mr2; 243 unsigned short ctr; 244 unsigned int j, baud, quot; 245 246 /* Prepare what we're gonna write */ 247 mr1 = 0; 248 249 switch (new->c_cflag & CSIZE) { 250 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; 251 break; 252 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; 253 break; 254 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; 255 break; 256 case CS8: 257 default: mr1 |= MPC52xx_PSC_MODE_8_BITS; 258 } 259 260 if (new->c_cflag & PARENB) { 261 mr1 |= (new->c_cflag & PARODD) ? 262 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 263 } else 264 mr1 |= MPC52xx_PSC_MODE_PARNONE; 265 266 267 mr2 = 0; 268 269 if (new->c_cflag & CSTOPB) 270 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; 271 else 272 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? 273 MPC52xx_PSC_MODE_ONE_STOP_5_BITS : 274 MPC52xx_PSC_MODE_ONE_STOP; 275 276 277 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); 278 quot = uart_get_divisor(port, baud); 279 ctr = quot & 0xffff; 280 281 /* Get the lock */ 282 spin_lock_irqsave(&port->lock, flags); 283 284 /* Update the per-port timeout */ 285 uart_update_timeout(port, new->c_cflag, baud); 286 287 /* Do our best to flush TX & RX, so we don't loose anything */ 288 /* But we don't wait indefinitly ! */ 289 j = 5000000; /* Maximum wait */ 290 /* FIXME Can't receive chars since set_termios might be called at early 291 * boot for the console, all stuff is not yet ready to receive at that 292 * time and that just makes the kernel oops */ 293 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ 294 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && 295 --j) 296 udelay(1); 297 298 if (!j) 299 printk( KERN_ERR "mpc52xx_uart.c: " 300 "Unable to flush RX & TX fifos in-time in set_termios." 301 "Some chars may have been lost.\n" ); 302 303 /* Reset the TX & RX */ 304 out_8(&psc->command,MPC52xx_PSC_RST_RX); 305 out_8(&psc->command,MPC52xx_PSC_RST_TX); 306 307 /* Send new mode settings */ 308 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1); 309 out_8(&psc->mode,mr1); 310 out_8(&psc->mode,mr2); 311 out_8(&psc->ctur,ctr >> 8); 312 out_8(&psc->ctlr,ctr & 0xff); 313 314 /* Reenable TX & RX */ 315 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE); 316 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE); 317 318 /* We're all set, release the lock */ 319 spin_unlock_irqrestore(&port->lock, flags); 320} 321 322static const char * 323mpc52xx_uart_type(struct uart_port *port) 324{ 325 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL; 326} 327 328static void 329mpc52xx_uart_release_port(struct uart_port *port) 330{ 331 if (port->flags & UPF_IOREMAP) { /* remapped by us ? */ 332 iounmap(port->membase); 333 port->membase = NULL; 334 } 335 336 release_mem_region(port->mapbase, MPC52xx_PSC_SIZE); 337} 338 339static int 340mpc52xx_uart_request_port(struct uart_port *port) 341{ 342 if (port->flags & UPF_IOREMAP) /* Need to remap ? */ 343 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE); 344 345 if (!port->membase) 346 return -EINVAL; 347 348 return request_mem_region(port->mapbase, MPC52xx_PSC_SIZE, 349 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; 350} 351 352static void 353mpc52xx_uart_config_port(struct uart_port *port, int flags) 354{ 355 if ( (flags & UART_CONFIG_TYPE) && 356 (mpc52xx_uart_request_port(port) == 0) ) 357 port->type = PORT_MPC52xx; 358} 359 360static int 361mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 362{ 363 if ( ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx ) 364 return -EINVAL; 365 366 if ( (ser->irq != port->irq) || 367 (ser->io_type != SERIAL_IO_MEM) || 368 (ser->baud_base != port->uartclk) || 369 (ser->iomem_base != (void*)port->mapbase) || 370 (ser->hub6 != 0 ) ) 371 return -EINVAL; 372 373 return 0; 374} 375 376 377static struct uart_ops mpc52xx_uart_ops = { 378 .tx_empty = mpc52xx_uart_tx_empty, 379 .set_mctrl = mpc52xx_uart_set_mctrl, 380 .get_mctrl = mpc52xx_uart_get_mctrl, 381 .stop_tx = mpc52xx_uart_stop_tx, 382 .start_tx = mpc52xx_uart_start_tx, 383 .send_xchar = mpc52xx_uart_send_xchar, 384 .stop_rx = mpc52xx_uart_stop_rx, 385 .enable_ms = mpc52xx_uart_enable_ms, 386 .break_ctl = mpc52xx_uart_break_ctl, 387 .startup = mpc52xx_uart_startup, 388 .shutdown = mpc52xx_uart_shutdown, 389 .set_termios = mpc52xx_uart_set_termios, 390/* .pm = mpc52xx_uart_pm, Not supported yet */ 391/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ 392 .type = mpc52xx_uart_type, 393 .release_port = mpc52xx_uart_release_port, 394 .request_port = mpc52xx_uart_request_port, 395 .config_port = mpc52xx_uart_config_port, 396 .verify_port = mpc52xx_uart_verify_port 397}; 398 399 400/* ======================================================================== */ 401/* Interrupt handling */ 402/* ======================================================================== */ 403 404static inline int 405mpc52xx_uart_int_rx_chars(struct uart_port *port, struct pt_regs *regs) 406{ 407 struct tty_struct *tty = port->info->tty; 408 unsigned char ch, flag; 409 unsigned short status; 410 411 /* While we can read, do so ! */ 412 while ( (status = in_be16(&PSC(port)->mpc52xx_psc_status)) & 413 MPC52xx_PSC_SR_RXRDY) { 414 415 /* Get the char */ 416 ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8); 417 418 /* Handle sysreq char */ 419#ifdef SUPPORT_SYSRQ 420 if (uart_handle_sysrq_char(port, ch, regs)) { 421 port->sysrq = 0; 422 continue; 423 } 424#endif 425 426 /* Store it */ 427 428 flag = TTY_NORMAL; 429 port->icount.rx++; 430 431 if ( status & (MPC52xx_PSC_SR_PE | 432 MPC52xx_PSC_SR_FE | 433 MPC52xx_PSC_SR_RB) ) { 434 435 if (status & MPC52xx_PSC_SR_RB) { 436 flag = TTY_BREAK; 437 uart_handle_break(port); 438 } else if (status & MPC52xx_PSC_SR_PE) 439 flag = TTY_PARITY; 440 else if (status & MPC52xx_PSC_SR_FE) 441 flag = TTY_FRAME; 442 443 /* Clear error condition */ 444 out_8(&PSC(port)->command,MPC52xx_PSC_RST_ERR_STAT); 445 446 } 447 tty_insert_flip_char(tty, ch, flag); 448 if (status & MPC52xx_PSC_SR_OE) { 449 /* 450 * Overrun is special, since it's 451 * reported immediately, and doesn't 452 * affect the current character 453 */ 454 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 455 } 456 } 457 458 tty_flip_buffer_push(tty); 459 460 return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY; 461} 462 463static inline int 464mpc52xx_uart_int_tx_chars(struct uart_port *port) 465{ 466 struct circ_buf *xmit = &port->info->xmit; 467 468 /* Process out of band chars */ 469 if (port->x_char) { 470 out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char); 471 port->icount.tx++; 472 port->x_char = 0; 473 return 1; 474 } 475 476 /* Nothing to do ? */ 477 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 478 mpc52xx_uart_stop_tx(port); 479 return 0; 480 } 481 482 /* Send chars */ 483 while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) { 484 out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]); 485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 486 port->icount.tx++; 487 if (uart_circ_empty(xmit)) 488 break; 489 } 490 491 /* Wake up */ 492 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 493 uart_write_wakeup(port); 494 495 /* Maybe we're done after all */ 496 if (uart_circ_empty(xmit)) { 497 mpc52xx_uart_stop_tx(port); 498 return 0; 499 } 500 501 return 1; 502} 503 504static irqreturn_t 505mpc52xx_uart_int(int irq, void *dev_id, struct pt_regs *regs) 506{ 507 struct uart_port *port = (struct uart_port *) dev_id; 508 unsigned long pass = ISR_PASS_LIMIT; 509 unsigned int keepgoing; 510 unsigned short status; 511 512 if ( irq != port->irq ) { 513 printk( KERN_WARNING 514 "mpc52xx_uart_int : " \ 515 "Received wrong int %d. Waiting for %d\n", 516 irq, port->irq); 517 return IRQ_NONE; 518 } 519 520 spin_lock(&port->lock); 521 522 /* While we have stuff to do, we continue */ 523 do { 524 /* If we don't find anything to do, we stop */ 525 keepgoing = 0; 526 527 /* Read status */ 528 status = in_be16(&PSC(port)->mpc52xx_psc_isr); 529 status &= port->read_status_mask; 530 531 /* Do we need to receive chars ? */ 532 /* For this RX interrupts must be on and some chars waiting */ 533 if ( status & MPC52xx_PSC_IMR_RXRDY ) 534 keepgoing |= mpc52xx_uart_int_rx_chars(port, regs); 535 536 /* Do we need to send chars ? */ 537 /* For this, TX must be ready and TX interrupt enabled */ 538 if ( status & MPC52xx_PSC_IMR_TXRDY ) 539 keepgoing |= mpc52xx_uart_int_tx_chars(port); 540 541 /* Limit number of iteration */ 542 if ( !(--pass) ) 543 keepgoing = 0; 544 545 } while (keepgoing); 546 547 spin_unlock(&port->lock); 548 549 return IRQ_HANDLED; 550} 551 552 553/* ======================================================================== */ 554/* Console ( if applicable ) */ 555/* ======================================================================== */ 556 557#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE 558 559static void __init 560mpc52xx_console_get_options(struct uart_port *port, 561 int *baud, int *parity, int *bits, int *flow) 562{ 563 struct mpc52xx_psc __iomem *psc = PSC(port); 564 unsigned char mr1; 565 566 /* Read the mode registers */ 567 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1); 568 mr1 = in_8(&psc->mode); 569 570 /* CT{U,L}R are write-only ! */ 571 *baud = __res.bi_baudrate ? 572 __res.bi_baudrate : CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 573 574 /* Parse them */ 575 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { 576 case MPC52xx_PSC_MODE_5_BITS: *bits = 5; break; 577 case MPC52xx_PSC_MODE_6_BITS: *bits = 6; break; 578 case MPC52xx_PSC_MODE_7_BITS: *bits = 7; break; 579 case MPC52xx_PSC_MODE_8_BITS: 580 default: *bits = 8; 581 } 582 583 if (mr1 & MPC52xx_PSC_MODE_PARNONE) 584 *parity = 'n'; 585 else 586 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; 587} 588 589static void 590mpc52xx_console_write(struct console *co, const char *s, unsigned int count) 591{ 592 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 593 struct mpc52xx_psc __iomem *psc = PSC(port); 594 unsigned int i, j; 595 596 /* Disable interrupts */ 597 out_be16(&psc->mpc52xx_psc_imr, 0); 598 599 /* Wait the TX buffer to be empty */ 600 j = 5000000; /* Maximum wait */ 601 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && 602 --j) 603 udelay(1); 604 605 /* Write all the chars */ 606 for ( i=0 ; i<count ; i++ ) { 607 608 /* Send the char */ 609 out_8(&psc->mpc52xx_psc_buffer_8, *s); 610 611 /* Line return handling */ 612 if ( *s++ == '\n' ) 613 out_8(&psc->mpc52xx_psc_buffer_8, '\r'); 614 615 /* Wait the TX buffer to be empty */ 616 j = 20000; /* Maximum wait */ 617 while (!(in_be16(&psc->mpc52xx_psc_status) & 618 MPC52xx_PSC_SR_TXEMP) && --j) 619 udelay(1); 620 } 621 622 /* Restore interrupt state */ 623 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 624} 625 626static int __init 627mpc52xx_console_setup(struct console *co, char *options) 628{ 629 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 630 631 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 632 int bits = 8; 633 int parity = 'n'; 634 int flow = 'n'; 635 636 if (co->index < 0 || co->index >= MPC52xx_PSC_MAXNUM) 637 return -EINVAL; 638 639 /* Basic port init. Needed since we use some uart_??? func before 640 * real init for early access */ 641 spin_lock_init(&port->lock); 642 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */ 643 port->ops = &mpc52xx_uart_ops; 644 port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1)); 645 646 /* We ioremap ourself */ 647 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE); 648 if (port->membase == NULL) 649 return -EINVAL; 650 651 /* Setup the port parameters accoding to options */ 652 if (options) 653 uart_parse_options(options, &baud, &parity, &bits, &flow); 654 else 655 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); 656 657 return uart_set_options(port, co, baud, parity, bits, flow); 658} 659 660 661static struct uart_driver mpc52xx_uart_driver; 662 663static struct console mpc52xx_console = { 664 .name = "ttyPSC", 665 .write = mpc52xx_console_write, 666 .device = uart_console_device, 667 .setup = mpc52xx_console_setup, 668 .flags = CON_PRINTBUFFER, 669 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0 ) */ 670 .data = &mpc52xx_uart_driver, 671}; 672 673 674static int __init 675mpc52xx_console_init(void) 676{ 677 register_console(&mpc52xx_console); 678 return 0; 679} 680 681console_initcall(mpc52xx_console_init); 682 683#define MPC52xx_PSC_CONSOLE &mpc52xx_console 684#else 685#define MPC52xx_PSC_CONSOLE NULL 686#endif 687 688 689/* ======================================================================== */ 690/* UART Driver */ 691/* ======================================================================== */ 692 693static struct uart_driver mpc52xx_uart_driver = { 694 .owner = THIS_MODULE, 695 .driver_name = "mpc52xx_psc_uart", 696 .dev_name = "ttyPSC", 697 .devfs_name = "ttyPSC", 698 .major = SERIAL_PSC_MAJOR, 699 .minor = SERIAL_PSC_MINOR, 700 .nr = MPC52xx_PSC_MAXNUM, 701 .cons = MPC52xx_PSC_CONSOLE, 702}; 703 704 705/* ======================================================================== */ 706/* Platform Driver */ 707/* ======================================================================== */ 708 709static int __devinit 710mpc52xx_uart_probe(struct platform_device *dev) 711{ 712 struct resource *res = dev->resource; 713 714 struct uart_port *port = NULL; 715 int i, idx, ret; 716 717 /* Check validity & presence */ 718 idx = dev->id; 719 if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM) 720 return -EINVAL; 721 722 if (!mpc52xx_match_psc_function(idx,"uart")) 723 return -ENODEV; 724 725 /* Init the port structure */ 726 port = &mpc52xx_uart_ports[idx]; 727 728 memset(port, 0x00, sizeof(struct uart_port)); 729 730 spin_lock_init(&port->lock); 731 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */ 732 port->fifosize = 255; /* Should be 512 ! But it can't be */ 733 /* stored in a unsigned char */ 734 port->iotype = UPIO_MEM; 735 port->flags = UPF_BOOT_AUTOCONF | 736 ( uart_console(port) ? 0 : UPF_IOREMAP ); 737 port->line = idx; 738 port->ops = &mpc52xx_uart_ops; 739 740 /* Search for IRQ and mapbase */ 741 for (i=0 ; i<dev->num_resources ; i++, res++) { 742 if (res->flags & IORESOURCE_MEM) 743 port->mapbase = res->start; 744 else if (res->flags & IORESOURCE_IRQ) 745 port->irq = res->start; 746 } 747 if (!port->irq || !port->mapbase) 748 return -EINVAL; 749 750 /* Add the port to the uart sub-system */ 751 ret = uart_add_one_port(&mpc52xx_uart_driver, port); 752 if (!ret) 753 platform_set_drvdata(dev, (void*)port); 754 755 return ret; 756} 757 758static int 759mpc52xx_uart_remove(struct platform_device *dev) 760{ 761 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); 762 763 platform_set_drvdata(dev, NULL); 764 765 if (port) 766 uart_remove_one_port(&mpc52xx_uart_driver, port); 767 768 return 0; 769} 770 771#ifdef CONFIG_PM 772static int 773mpc52xx_uart_suspend(struct platform_device *dev, pm_message_t state) 774{ 775 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); 776 777 if (sport) 778 uart_suspend_port(&mpc52xx_uart_driver, port); 779 780 return 0; 781} 782 783static int 784mpc52xx_uart_resume(struct platform_device *dev) 785{ 786 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); 787 788 if (port) 789 uart_resume_port(&mpc52xx_uart_driver, port); 790 791 return 0; 792} 793#endif 794 795static struct platform_driver mpc52xx_uart_platform_driver = { 796 .probe = mpc52xx_uart_probe, 797 .remove = mpc52xx_uart_remove, 798#ifdef CONFIG_PM 799 .suspend = mpc52xx_uart_suspend, 800 .resume = mpc52xx_uart_resume, 801#endif 802 .driver = { 803 .name = "mpc52xx-psc", 804 }, 805}; 806 807 808/* ======================================================================== */ 809/* Module */ 810/* ======================================================================== */ 811 812static int __init 813mpc52xx_uart_init(void) 814{ 815 int ret; 816 817 printk(KERN_INFO "Serial: MPC52xx PSC driver\n"); 818 819 ret = uart_register_driver(&mpc52xx_uart_driver); 820 if (ret == 0) { 821 ret = platform_driver_register(&mpc52xx_uart_platform_driver); 822 if (ret) 823 uart_unregister_driver(&mpc52xx_uart_driver); 824 } 825 826 return ret; 827} 828 829static void __exit 830mpc52xx_uart_exit(void) 831{ 832 platform_driver_unregister(&mpc52xx_uart_platform_driver); 833 uart_unregister_driver(&mpc52xx_uart_driver); 834} 835 836 837module_init(mpc52xx_uart_init); 838module_exit(mpc52xx_uart_exit); 839 840MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 841MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); 842MODULE_LICENSE("GPL");