tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * A collection of structures, addresses, and values associated with
3 * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 */
7#ifdef __KERNEL__
8#ifndef __MACH_RPX_DEFS
9#define __MACH_RPX_DEFS
10
11#include <linux/config.h>
12
13#ifndef __ASSEMBLY__
14/* A Board Information structure that is given to a program when
15 * prom starts it up.
16 */
17typedef struct bd_info {
18 unsigned int bi_memstart; /* Memory start address */
19 unsigned int bi_memsize; /* Memory (end) size in bytes */
20 unsigned int bi_intfreq; /* Internal Freq, in Hz */
21 unsigned int bi_busfreq; /* Bus Freq, in Hz */
22 unsigned char bi_enetaddr[6];
23 unsigned int bi_baudrate;
24} bd_t;
25
26extern bd_t m8xx_board_info;
27
28/* Memory map is configured by the PROM startup.
29 * We just map a few things we need. The CSR is actually 4 byte-wide
30 * registers that can be accessed as 8-, 16-, or 32-bit values.
31 */
32#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
33#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
34#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
35#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
36#define RPX_CSR_ADDR ((uint)0xfa400000)
37#define RPX_CSR_SIZE ((uint)(4 * 1024))
38#define IMAP_ADDR ((uint)0xfa200000)
39#define IMAP_SIZE ((uint)(64 * 1024))
40#define PCI_CSR_ADDR ((uint)0x80000000)
41#define PCI_CSR_SIZE ((uint)(64 * 1024))
42#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
43#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
44#define PCMCIA_IO_ADDR ((uint)0xe4000000)
45#define PCMCIA_IO_SIZE ((uint)(4 * 1024))
46#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
47#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024))
48
49/* Things of interest in the CSR.
50*/
51#define BCSR0_ETHEN ((uint)0x80000000)
52#define BCSR0_ETHLPBK ((uint)0x40000000)
53#define BCSR0_COLTESTDIS ((uint)0x20000000)
54#define BCSR0_FULLDPLXDIS ((uint)0x10000000)
55#define BCSR0_ENFLSHSEL ((uint)0x04000000)
56#define BCSR0_FLASH_SEL ((uint)0x02000000)
57#define BCSR0_ENMONXCVR ((uint)0x01000000)
58
59#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */
60#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */
61#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */
62
63#define BCSR1_IPB5SEL ((uint)0x00100000)
64#define BCSR1_PCVCTL4 ((uint)0x00080000)
65#define BCSR1_PCVCTL5 ((uint)0x00040000)
66#define BCSR1_PCVCTL6 ((uint)0x00020000)
67#define BCSR1_PCVCTL7 ((uint)0x00010000)
68
69#define BCSR2_EN232XCVR ((uint)0x00008000)
70#define BCSR2_QSPACESEL ((uint)0x00004000)
71#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */
72
73#if defined(CONFIG_HTDMSOUND)
74#include <platforms/rpxhiox.h>
75#endif
76
77/* define IO_BASE for pcmcia, CLLF only */
78#if !defined(CONFIG_PCI)
79#define _IO_BASE 0x80000000
80#define _IO_BASE_SIZE 0x1000
81
82/* for pcmcia sandisk */
83#ifdef CONFIG_IDE
84# define MAX_HWIFS 1
85#endif
86#endif
87
88/* Interrupt level assignments.
89*/
90#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
91
92
93/* CPM Ethernet through SCCx.
94 *
95 * Bits in parallel I/O port registers that have to be set/cleared
96 * to configure the pins for SCC1 use.
97 */
98#define PA_ENET_RXD ((ushort)0x0001)
99#define PA_ENET_TXD ((ushort)0x0002)
100#define PA_ENET_TCLK ((ushort)0x0200)
101#define PA_ENET_RCLK ((ushort)0x0800)
102#define PB_ENET_TENA ((uint)0x00001000)
103#define PC_ENET_CLSN ((ushort)0x0010)
104#define PC_ENET_RENA ((ushort)0x0020)
105
106/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
107 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
108 */
109#define SICR_ENET_MASK ((uint)0x000000ff)
110#define SICR_ENET_CLKRT ((uint)0x0000003d)
111
112/* We don't use the 8259.
113*/
114
115#define NR_8259_INTS 0
116
117#endif /* !__ASSEMBLY__ */
118#endif /* __MACH_RPX_DEFS */
119#endif /* __KERNEL__ */