tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/ppc/platforms/hdpu.h
3 *
4 * Definitions for Sky Computers HDPU board.
5 *
6 * Brian Waite <waite@skycomputers.com>
7 *
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by Mark A. Greer <mgreer@mvista.com>
10 * Based on code done by Tim Montgomery <timm@artesyncp.com>
11 *
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/*
20 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
21 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
22 * We'll only use one PCI MEM window on each PCI bus.
23 *
24 * This is the CPU physical memory map (windows must be at least 64K and start
25 * on a boundary that is a multiple of the window size):
26 *
27 * 0x80000000-0x8fffffff - PCI 0 MEM
28 * 0xa0000000-0xafffffff - PCI 1 MEM
29 * 0xc0000000-0xc0ffffff - PCI 0 I/O
30 * 0xc1000000-0xc1ffffff - PCI 1 I/O
31
32 * 0xf1000000-0xf100ffff - MV64360 Registers
33 * 0xf1010000-0xfb9fffff - HOLE
34 * 0xfbfa0000-0xfbfaffff - TBEN
35 * 0xfbf00000-0xfbfbffff - NEXUS
36 * 0xfbfc0000-0xfbffffff - Internal SRAM
37 * 0xfc000000-0xffffffff - Boot window
38 */
39
40#ifndef __PPC_PLATFORMS_HDPU_H
41#define __PPC_PLATFORMS_HDPU_H
42
43/* CPU Physical Memory Map setup. */
44#define HDPU_BRIDGE_REG_BASE 0xf1000000
45
46#define HDPU_TBEN_BASE 0xfbfa0000
47#define HDPU_TBEN_SIZE 0x00010000
48#define HDPU_NEXUS_ID_BASE 0xfbfb0000
49#define HDPU_NEXUS_ID_SIZE 0x00010000
50#define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000
51#define HDPU_INTERNAL_SRAM_SIZE 0x00040000
52#define HDPU_EMB_FLASH_BASE 0xfc000000
53#define HDPU_EMB_FLASH_SIZE 0x04000000
54
55/* PCI Mappings */
56
57#define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000
58#define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
59#define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR
60#define HDPU_PCI0_MEM_SIZE 0x10000000
61
62#define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000
63#define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
64#define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR
65#define HDPU_PCI1_MEM_SIZE 0x20000000
66
67#define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000
68#define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000
69#define HDPU_PCI0_IO_SIZE 0x01000000
70
71#define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000
72#define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000
73#define HDPU_PCI1_IO_SIZE 0x01000000
74
75#define HDPU_DEFAULT_BAUD 115200
76#define HDPU_MPSC_CLK_SRC 8 /* TCLK */
77#define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */
78
79#define HDPU_PCI_0_IRQ (8+64)
80#define HDPU_PCI_1_IRQ (13+64)
81
82#endif /* __PPC_PLATFORMS_HDPU_H */