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1/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $
2 * cache.h: Cache specific code for the Sparc. These include flushing
3 * and direct tag/data line access.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_CACHE_H
9#define _SPARC_CACHE_H
10
11#include <asm/asi.h>
12
13#define L1_CACHE_SHIFT 5
14#define L1_CACHE_BYTES 32
15#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
16#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
17
18#define SMP_CACHE_BYTES 32
19
20/* Direct access to the instruction cache is provided through and
21 * alternate address space. The IDC bit must be off in the ICCR on
22 * HyperSparcs for these accesses to work. The code below does not do
23 * any checking, the caller must do so. These routines are for
24 * diagnostics only, but could end up being useful. Use with care.
25 * Also, you are asking for trouble if you execute these in one of the
26 * three instructions following a %asr/%psr access or modification.
27 */
28
29/* First, cache-tag access. */
30static inline unsigned int get_icache_tag(int setnum, int tagnum)
31{
32 unsigned int vaddr, retval;
33
34 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
35 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
36 "=r" (retval) :
37 "r" (vaddr), "i" (ASI_M_TXTC_TAG));
38 return retval;
39}
40
41static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
42{
43 unsigned int vaddr;
44
45 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
46 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
47 "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
48 "memory");
49}
50
51/* Second cache-data access. The data is returned two-32bit quantities
52 * at a time.
53 */
54static inline void get_icache_data(int setnum, int tagnum, int subblock,
55 unsigned int *data)
56{
57 unsigned int value1, value2, vaddr;
58
59 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
60 ((subblock&0x3) << 3);
61 __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
62 "or %%g0, %%g2, %0\n\t"
63 "or %%g0, %%g3, %1\n\t" :
64 "=r" (value1), "=r" (value2) :
65 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
66 "g2", "g3");
67 data[0] = value1; data[1] = value2;
68}
69
70static inline void put_icache_data(int setnum, int tagnum, int subblock,
71 unsigned int *data)
72{
73 unsigned int value1, value2, vaddr;
74
75 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
76 ((subblock&0x3) << 3);
77 value1 = data[0]; value2 = data[1];
78 __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
79 "or %%g0, %1, %%g3\n\t"
80 "stda %%g2, [%2] %3\n\t" : :
81 "r" (value1), "r" (value2),
82 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
83 "g2", "g3", "memory" /* no joke */);
84}
85
86/* Different types of flushes with the ICACHE. Some of the flushes
87 * affect both the ICACHE and the external cache. Others only clear
88 * the ICACHE entries on the cpu itself. V8's (most) allow
89 * granularity of flushes on the packet (element in line), whole line,
90 * and entire cache (ie. all lines) level. The ICACHE only flushes are
91 * ROSS HyperSparc specific and are in ross.h
92 */
93
94/* Flushes which clear out both the on-chip and external caches */
95static inline void flush_ei_page(unsigned int addr)
96{
97 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
98 "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
99 "memory");
100}
101
102static inline void flush_ei_seg(unsigned int addr)
103{
104 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
105 "r" (addr), "i" (ASI_M_FLUSH_SEG) :
106 "memory");
107}
108
109static inline void flush_ei_region(unsigned int addr)
110{
111 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
112 "r" (addr), "i" (ASI_M_FLUSH_REGION) :
113 "memory");
114}
115
116static inline void flush_ei_ctx(unsigned int addr)
117{
118 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
119 "r" (addr), "i" (ASI_M_FLUSH_CTX) :
120 "memory");
121}
122
123static inline void flush_ei_user(unsigned int addr)
124{
125 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
126 "r" (addr), "i" (ASI_M_FLUSH_USER) :
127 "memory");
128}
129
130#endif /* !(_SPARC_CACHE_H) */