tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/****************************************************************************/
2
3/*
4 * m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
5 *
6 * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m528xsim_h
11#define m528xsim_h
12/****************************************************************************/
13
14#include <linux/config.h>
15
16/*
17 * Define the 5280/5282 SIM register set addresses.
18 */
19#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
20#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
21#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
22#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
23#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
24#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
25#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
26#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
27#define MCFINTC_IRLR 0x18 /* */
28#define MCFINTC_IACKL 0x19 /* */
29#define MCFINTC_ICR0 0x40 /* Base ICR register */
30
31#define MCFINT_VECBASE 64 /* Vector base number */
32#define MCFINT_UART0 13 /* Interrupt number for UART0 */
33#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
34
35/*
36 * SDRAM configuration registers.
37 */
38#define MCFSIM_DCR 0x44 /* SDRAM control */
39#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
40#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
41#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
42#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
43
44/*
45 * Derek Cheung - 6 Feb 2005
46 * add I2C and QSPI register definition using Freescale's MCF5282
47 */
48/* set Port AS pin for I2C or UART */
49#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
50
51/* Interrupt Mask Register Register Low */
52#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
53/* Interrupt Control Register 7 */
54#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
55
56
57
58/*********************************************************************
59*
60* Inter-IC (I2C) Module
61*
62*********************************************************************/
63/* Read/Write access macros for general use */
64#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
65#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
66#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
67#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
68#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
69
70/* Bit level definitions and macros */
71#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
72
73#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
74
75#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
76#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
77#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
78#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
79#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
80#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
81
82#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
83#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
84#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
85#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
86#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
87#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
88#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
89
90
91
92/*********************************************************************
93*
94* Queued Serial Peripheral Interface (QSPI) Module
95*
96*********************************************************************/
97/* Derek - 21 Feb 2005 */
98/* change to the format used in I2C */
99/* Read/Write access macros for general use */
100#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
101#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
102#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
103#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
104#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
105#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
106#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
107
108/* Bit level definitions and macros */
109#define MCF5282_QSPI_QMR_MSTR (0x8000)
110#define MCF5282_QSPI_QMR_DOHIE (0x4000)
111#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
112#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
113#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
114#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
115#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
116#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
117#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
118#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
119#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
120#define MCF5282_QSPI_QMR_CPOL (0x0200)
121#define MCF5282_QSPI_QMR_CPHA (0x0100)
122#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
123
124#define MCF5282_QSPI_QDLYR_SPE (0x80)
125#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
126#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
127
128#define MCF5282_QSPI_QWR_HALT (0x8000)
129#define MCF5282_QSPI_QWR_WREN (0x4000)
130#define MCF5282_QSPI_QWR_WRTO (0x2000)
131#define MCF5282_QSPI_QWR_CSIV (0x1000)
132#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
133#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
134#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
135
136#define MCF5282_QSPI_QIR_WCEFB (0x8000)
137#define MCF5282_QSPI_QIR_ABRTB (0x4000)
138#define MCF5282_QSPI_QIR_ABRTL (0x1000)
139#define MCF5282_QSPI_QIR_WCEFE (0x0800)
140#define MCF5282_QSPI_QIR_ABRTE (0x0400)
141#define MCF5282_QSPI_QIR_SPIFE (0x0100)
142#define MCF5282_QSPI_QIR_WCEF (0x0008)
143#define MCF5282_QSPI_QIR_ABRT (0x0004)
144#define MCF5282_QSPI_QIR_SPIF (0x0001)
145
146#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
147
148#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
149#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
150#define MCF5282_QSPI_QCR_CONT (0x8000)
151#define MCF5282_QSPI_QCR_BITSE (0x4000)
152#define MCF5282_QSPI_QCR_DT (0x2000)
153#define MCF5282_QSPI_QCR_DSCK (0x1000)
154#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
155
156/****************************************************************************/
157#endif /* m528xsim_h */