Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/config.h>
21#include <linux/threads.h>
22#include <asm/percpu.h>
23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 int fdiv_bug;
65 int f00f_bug;
66 int coma_bug;
67 unsigned long loops_per_jiffy;
68 unsigned char x86_max_cores; /* cpuid returned max cores value */
69 unsigned char booted_cores; /* number of cores as seen by OS */
70 unsigned char apicid;
71} __attribute__((__aligned__(SMP_CACHE_BYTES)));
72
73#define X86_VENDOR_INTEL 0
74#define X86_VENDOR_CYRIX 1
75#define X86_VENDOR_AMD 2
76#define X86_VENDOR_UMC 3
77#define X86_VENDOR_NEXGEN 4
78#define X86_VENDOR_CENTAUR 5
79#define X86_VENDOR_RISE 6
80#define X86_VENDOR_TRANSMETA 7
81#define X86_VENDOR_NSC 8
82#define X86_VENDOR_NUM 9
83#define X86_VENDOR_UNKNOWN 0xff
84
85/*
86 * capabilities of CPUs
87 */
88
89extern struct cpuinfo_x86 boot_cpu_data;
90extern struct cpuinfo_x86 new_cpu_data;
91extern struct tss_struct doublefault_tss;
92DECLARE_PER_CPU(struct tss_struct, init_tss);
93
94#ifdef CONFIG_SMP
95extern struct cpuinfo_x86 cpu_data[];
96#define current_cpu_data cpu_data[smp_processor_id()]
97#else
98#define cpu_data (&boot_cpu_data)
99#define current_cpu_data boot_cpu_data
100#endif
101
102extern int phys_proc_id[NR_CPUS];
103extern int cpu_core_id[NR_CPUS];
104extern char ignore_fpu_irq;
105
106extern void identify_cpu(struct cpuinfo_x86 *);
107extern void print_cpu_info(struct cpuinfo_x86 *);
108extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
109
110#ifdef CONFIG_X86_HT
111extern void detect_ht(struct cpuinfo_x86 *c);
112#else
113static inline void detect_ht(struct cpuinfo_x86 *c) {}
114#endif
115
116/*
117 * EFLAGS bits
118 */
119#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
120#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
121#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
122#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
123#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
124#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
125#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
126#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
127#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
128#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
129#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
130#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
131#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
132#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
133#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
134#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
135#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
136
137/*
138 * Generic CPUID function
139 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
140 * resulting in stale register contents being returned.
141 */
142static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
143{
144 __asm__("cpuid"
145 : "=a" (*eax),
146 "=b" (*ebx),
147 "=c" (*ecx),
148 "=d" (*edx)
149 : "0" (op), "c"(0));
150}
151
152/* Some CPUID calls want 'count' to be placed in ecx */
153static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
154 int *edx)
155{
156 __asm__("cpuid"
157 : "=a" (*eax),
158 "=b" (*ebx),
159 "=c" (*ecx),
160 "=d" (*edx)
161 : "0" (op), "c" (count));
162}
163
164/*
165 * CPUID functions returning a single datum
166 */
167static inline unsigned int cpuid_eax(unsigned int op)
168{
169 unsigned int eax;
170
171 __asm__("cpuid"
172 : "=a" (eax)
173 : "0" (op)
174 : "bx", "cx", "dx");
175 return eax;
176}
177static inline unsigned int cpuid_ebx(unsigned int op)
178{
179 unsigned int eax, ebx;
180
181 __asm__("cpuid"
182 : "=a" (eax), "=b" (ebx)
183 : "0" (op)
184 : "cx", "dx" );
185 return ebx;
186}
187static inline unsigned int cpuid_ecx(unsigned int op)
188{
189 unsigned int eax, ecx;
190
191 __asm__("cpuid"
192 : "=a" (eax), "=c" (ecx)
193 : "0" (op)
194 : "bx", "dx" );
195 return ecx;
196}
197static inline unsigned int cpuid_edx(unsigned int op)
198{
199 unsigned int eax, edx;
200
201 __asm__("cpuid"
202 : "=a" (eax), "=d" (edx)
203 : "0" (op)
204 : "bx", "cx");
205 return edx;
206}
207
208#define load_cr3(pgdir) write_cr3(__pa(pgdir))
209
210/*
211 * Intel CPU features in CR4
212 */
213#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
214#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
215#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
216#define X86_CR4_DE 0x0008 /* enable debugging extensions */
217#define X86_CR4_PSE 0x0010 /* enable page size extensions */
218#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
219#define X86_CR4_MCE 0x0040 /* Machine check enable */
220#define X86_CR4_PGE 0x0080 /* enable global pages */
221#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
222#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
223#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
224
225/*
226 * Save the cr4 feature set we're using (ie
227 * Pentium 4MB enable and PPro Global page
228 * enable), so that any CPU's that boot up
229 * after us can get the correct flags.
230 */
231extern unsigned long mmu_cr4_features;
232
233static inline void set_in_cr4 (unsigned long mask)
234{
235 unsigned cr4;
236 mmu_cr4_features |= mask;
237 cr4 = read_cr4();
238 cr4 |= mask;
239 write_cr4(cr4);
240}
241
242static inline void clear_in_cr4 (unsigned long mask)
243{
244 unsigned cr4;
245 mmu_cr4_features &= ~mask;
246 cr4 = read_cr4();
247 cr4 &= ~mask;
248 write_cr4(cr4);
249}
250
251/*
252 * NSC/Cyrix CPU configuration register indexes
253 */
254
255#define CX86_PCR0 0x20
256#define CX86_GCR 0xb8
257#define CX86_CCR0 0xc0
258#define CX86_CCR1 0xc1
259#define CX86_CCR2 0xc2
260#define CX86_CCR3 0xc3
261#define CX86_CCR4 0xe8
262#define CX86_CCR5 0xe9
263#define CX86_CCR6 0xea
264#define CX86_CCR7 0xeb
265#define CX86_PCR1 0xf0
266#define CX86_DIR0 0xfe
267#define CX86_DIR1 0xff
268#define CX86_ARR_BASE 0xc4
269#define CX86_RCR_BASE 0xdc
270
271/*
272 * NSC/Cyrix CPU indexed register access macros
273 */
274
275#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
276
277#define setCx86(reg, data) do { \
278 outb((reg), 0x22); \
279 outb((data), 0x23); \
280} while (0)
281
282static inline void serialize_cpu(void)
283{
284 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
285}
286
287static inline void __monitor(const void *eax, unsigned long ecx,
288 unsigned long edx)
289{
290 /* "monitor %eax,%ecx,%edx;" */
291 asm volatile(
292 ".byte 0x0f,0x01,0xc8;"
293 : :"a" (eax), "c" (ecx), "d"(edx));
294}
295
296static inline void __mwait(unsigned long eax, unsigned long ecx)
297{
298 /* "mwait %eax,%ecx;" */
299 asm volatile(
300 ".byte 0x0f,0x01,0xc9;"
301 : :"a" (eax), "c" (ecx));
302}
303
304/* from system description table in BIOS. Mostly for MCA use, but
305others may find it useful. */
306extern unsigned int machine_id;
307extern unsigned int machine_submodel_id;
308extern unsigned int BIOS_revision;
309extern unsigned int mca_pentium_flag;
310
311/* Boot loader type from the setup header */
312extern int bootloader_type;
313
314/*
315 * User space process size: 3GB (default).
316 */
317#define TASK_SIZE (PAGE_OFFSET)
318
319/* This decides where the kernel will search for a free chunk of vm
320 * space during mmap's.
321 */
322#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
323
324#define HAVE_ARCH_PICK_MMAP_LAYOUT
325
326/*
327 * Size of io_bitmap.
328 */
329#define IO_BITMAP_BITS 65536
330#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
331#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
332#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
333#define INVALID_IO_BITMAP_OFFSET 0x8000
334#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
335
336struct i387_fsave_struct {
337 long cwd;
338 long swd;
339 long twd;
340 long fip;
341 long fcs;
342 long foo;
343 long fos;
344 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
345 long status; /* software status information */
346};
347
348struct i387_fxsave_struct {
349 unsigned short cwd;
350 unsigned short swd;
351 unsigned short twd;
352 unsigned short fop;
353 long fip;
354 long fcs;
355 long foo;
356 long fos;
357 long mxcsr;
358 long mxcsr_mask;
359 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
360 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
361 long padding[56];
362} __attribute__ ((aligned (16)));
363
364struct i387_soft_struct {
365 long cwd;
366 long swd;
367 long twd;
368 long fip;
369 long fcs;
370 long foo;
371 long fos;
372 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
373 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
374 struct info *info;
375 unsigned long entry_eip;
376};
377
378union i387_union {
379 struct i387_fsave_struct fsave;
380 struct i387_fxsave_struct fxsave;
381 struct i387_soft_struct soft;
382};
383
384typedef struct {
385 unsigned long seg;
386} mm_segment_t;
387
388struct thread_struct;
389
390struct tss_struct {
391 unsigned short back_link,__blh;
392 unsigned long esp0;
393 unsigned short ss0,__ss0h;
394 unsigned long esp1;
395 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
396 unsigned long esp2;
397 unsigned short ss2,__ss2h;
398 unsigned long __cr3;
399 unsigned long eip;
400 unsigned long eflags;
401 unsigned long eax,ecx,edx,ebx;
402 unsigned long esp;
403 unsigned long ebp;
404 unsigned long esi;
405 unsigned long edi;
406 unsigned short es, __esh;
407 unsigned short cs, __csh;
408 unsigned short ss, __ssh;
409 unsigned short ds, __dsh;
410 unsigned short fs, __fsh;
411 unsigned short gs, __gsh;
412 unsigned short ldt, __ldth;
413 unsigned short trace, io_bitmap_base;
414 /*
415 * The extra 1 is there because the CPU will access an
416 * additional byte beyond the end of the IO permission
417 * bitmap. The extra byte must be all 1 bits, and must
418 * be within the limit.
419 */
420 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
421 /*
422 * Cache the current maximum and the last task that used the bitmap:
423 */
424 unsigned long io_bitmap_max;
425 struct thread_struct *io_bitmap_owner;
426 /*
427 * pads the TSS to be cacheline-aligned (size is 0x100)
428 */
429 unsigned long __cacheline_filler[35];
430 /*
431 * .. and then another 0x100 bytes for emergency kernel stack
432 */
433 unsigned long stack[64];
434} __attribute__((packed));
435
436#define ARCH_MIN_TASKALIGN 16
437
438struct thread_struct {
439/* cached TLS descriptors. */
440 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
441 unsigned long esp0;
442 unsigned long sysenter_cs;
443 unsigned long eip;
444 unsigned long esp;
445 unsigned long fs;
446 unsigned long gs;
447/* Hardware debugging registers */
448 unsigned long debugreg[8]; /* %%db0-7 debug registers */
449/* fault info */
450 unsigned long cr2, trap_no, error_code;
451/* floating point info */
452 union i387_union i387;
453/* virtual 86 mode info */
454 struct vm86_struct __user * vm86_info;
455 unsigned long screen_bitmap;
456 unsigned long v86flags, v86mask, saved_esp0;
457 unsigned int saved_fs, saved_gs;
458/* IO permissions */
459 unsigned long *io_bitmap_ptr;
460 unsigned long iopl;
461/* max allowed port in the bitmap, in bytes: */
462 unsigned long io_bitmap_max;
463};
464
465#define INIT_THREAD { \
466 .vm86_info = NULL, \
467 .sysenter_cs = __KERNEL_CS, \
468 .io_bitmap_ptr = NULL, \
469}
470
471/*
472 * Note that the .io_bitmap member must be extra-big. This is because
473 * the CPU will access an additional byte beyond the end of the IO
474 * permission bitmap. The extra byte must be all 1 bits, and must
475 * be within the limit.
476 */
477#define INIT_TSS { \
478 .esp0 = sizeof(init_stack) + (long)&init_stack, \
479 .ss0 = __KERNEL_DS, \
480 .ss1 = __KERNEL_CS, \
481 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
482 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
483}
484
485static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
486{
487 tss->esp0 = thread->esp0;
488 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
489 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
490 tss->ss1 = thread->sysenter_cs;
491 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
492 }
493}
494
495#define start_thread(regs, new_eip, new_esp) do { \
496 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
497 set_fs(USER_DS); \
498 regs->xds = __USER_DS; \
499 regs->xes = __USER_DS; \
500 regs->xss = __USER_DS; \
501 regs->xcs = __USER_CS; \
502 regs->eip = new_eip; \
503 regs->esp = new_esp; \
504} while (0)
505
506/*
507 * These special macros can be used to get or set a debugging register
508 */
509#define get_debugreg(var, register) \
510 __asm__("movl %%db" #register ", %0" \
511 :"=r" (var))
512#define set_debugreg(value, register) \
513 __asm__("movl %0,%%db" #register \
514 : /* no output */ \
515 :"r" (value))
516
517/*
518 * Set IOPL bits in EFLAGS from given mask
519 */
520static inline void set_iopl_mask(unsigned mask)
521{
522 unsigned int reg;
523 __asm__ __volatile__ ("pushfl;"
524 "popl %0;"
525 "andl %1, %0;"
526 "orl %2, %0;"
527 "pushl %0;"
528 "popfl"
529 : "=&r" (reg)
530 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
531}
532
533/* Forward declaration, a strange C thing */
534struct task_struct;
535struct mm_struct;
536
537/* Free all resources held by a thread. */
538extern void release_thread(struct task_struct *);
539
540/* Prepare to copy thread state - unlazy all lazy status */
541extern void prepare_to_copy(struct task_struct *tsk);
542
543/*
544 * create a kernel thread without removing it from tasklists
545 */
546extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
547
548extern unsigned long thread_saved_pc(struct task_struct *tsk);
549void show_trace(struct task_struct *task, unsigned long *stack);
550
551unsigned long get_wchan(struct task_struct *p);
552
553#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
554#define KSTK_TOP(info) \
555({ \
556 unsigned long *__ptr = (unsigned long *)(info); \
557 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
558})
559
560#define task_pt_regs(task) \
561({ \
562 struct pt_regs *__regs__; \
563 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
564 __regs__ - 1; \
565})
566
567#define KSTK_EIP(task) (task_pt_regs(task)->eip)
568#define KSTK_ESP(task) (task_pt_regs(task)->esp)
569
570
571struct microcode_header {
572 unsigned int hdrver;
573 unsigned int rev;
574 unsigned int date;
575 unsigned int sig;
576 unsigned int cksum;
577 unsigned int ldrver;
578 unsigned int pf;
579 unsigned int datasize;
580 unsigned int totalsize;
581 unsigned int reserved[3];
582};
583
584struct microcode {
585 struct microcode_header hdr;
586 unsigned int bits[0];
587};
588
589typedef struct microcode microcode_t;
590typedef struct microcode_header microcode_header_t;
591
592/* microcode format is extended from prescott processors */
593struct extended_signature {
594 unsigned int sig;
595 unsigned int pf;
596 unsigned int cksum;
597};
598
599struct extended_sigtable {
600 unsigned int count;
601 unsigned int cksum;
602 unsigned int reserved[3];
603 struct extended_signature sigs[0];
604};
605/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
606#define MICROCODE_IOCFREE _IO('6',0)
607
608/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
609static inline void rep_nop(void)
610{
611 __asm__ __volatile__("rep;nop": : :"memory");
612}
613
614#define cpu_relax() rep_nop()
615
616/* generic versions from gas */
617#define GENERIC_NOP1 ".byte 0x90\n"
618#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
619#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
620#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
621#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
622#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
623#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
624#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
625
626/* Opteron nops */
627#define K8_NOP1 GENERIC_NOP1
628#define K8_NOP2 ".byte 0x66,0x90\n"
629#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
630#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
631#define K8_NOP5 K8_NOP3 K8_NOP2
632#define K8_NOP6 K8_NOP3 K8_NOP3
633#define K8_NOP7 K8_NOP4 K8_NOP3
634#define K8_NOP8 K8_NOP4 K8_NOP4
635
636/* K7 nops */
637/* uses eax dependencies (arbitary choice) */
638#define K7_NOP1 GENERIC_NOP1
639#define K7_NOP2 ".byte 0x8b,0xc0\n"
640#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
641#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
642#define K7_NOP5 K7_NOP4 ASM_NOP1
643#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
644#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
645#define K7_NOP8 K7_NOP7 ASM_NOP1
646
647#ifdef CONFIG_MK8
648#define ASM_NOP1 K8_NOP1
649#define ASM_NOP2 K8_NOP2
650#define ASM_NOP3 K8_NOP3
651#define ASM_NOP4 K8_NOP4
652#define ASM_NOP5 K8_NOP5
653#define ASM_NOP6 K8_NOP6
654#define ASM_NOP7 K8_NOP7
655#define ASM_NOP8 K8_NOP8
656#elif defined(CONFIG_MK7)
657#define ASM_NOP1 K7_NOP1
658#define ASM_NOP2 K7_NOP2
659#define ASM_NOP3 K7_NOP3
660#define ASM_NOP4 K7_NOP4
661#define ASM_NOP5 K7_NOP5
662#define ASM_NOP6 K7_NOP6
663#define ASM_NOP7 K7_NOP7
664#define ASM_NOP8 K7_NOP8
665#else
666#define ASM_NOP1 GENERIC_NOP1
667#define ASM_NOP2 GENERIC_NOP2
668#define ASM_NOP3 GENERIC_NOP3
669#define ASM_NOP4 GENERIC_NOP4
670#define ASM_NOP5 GENERIC_NOP5
671#define ASM_NOP6 GENERIC_NOP6
672#define ASM_NOP7 GENERIC_NOP7
673#define ASM_NOP8 GENERIC_NOP8
674#endif
675
676#define ASM_NOP_MAX 8
677
678/* Prefetch instructions for Pentium III and AMD Athlon */
679/* It's not worth to care about 3dnow! prefetches for the K6
680 because they are microcoded there and very slow.
681 However we don't do prefetches for pre XP Athlons currently
682 That should be fixed. */
683#define ARCH_HAS_PREFETCH
684static inline void prefetch(const void *x)
685{
686 alternative_input(ASM_NOP4,
687 "prefetchnta (%1)",
688 X86_FEATURE_XMM,
689 "r" (x));
690}
691
692#define ARCH_HAS_PREFETCH
693#define ARCH_HAS_PREFETCHW
694#define ARCH_HAS_SPINLOCK_PREFETCH
695
696/* 3dnow! prefetch to get an exclusive cache line. Useful for
697 spinlocks to avoid one state transition in the cache coherency protocol. */
698static inline void prefetchw(const void *x)
699{
700 alternative_input(ASM_NOP4,
701 "prefetchw (%1)",
702 X86_FEATURE_3DNOW,
703 "r" (x));
704}
705#define spin_lock_prefetch(x) prefetchw(x)
706
707extern void select_idle_routine(const struct cpuinfo_x86 *c);
708
709#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
710
711extern unsigned long boot_option_idle_override;
712extern void enable_sep_cpu(void);
713extern int sysenter_setup(void);
714
715#ifdef CONFIG_MTRR
716extern void mtrr_ap_init(void);
717extern void mtrr_bp_init(void);
718#else
719#define mtrr_ap_init() do {} while (0)
720#define mtrr_bp_init() do {} while (0)
721#endif
722
723#ifdef CONFIG_X86_MCE
724extern void mcheck_init(struct cpuinfo_x86 *c);
725#else
726#define mcheck_init(c) do {} while(0)
727#endif
728
729#endif /* __ASM_I386_PROCESSOR_H */