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1/******************************************************************************
2** High Performance device driver for the Symbios 53C896 controller.
3**
4** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
5**
6** This driver also supports all the Symbios 53C8XX controller family,
7** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8** revisions of 53C815 controllers.
9**
10** This driver is based on the Linux port of the FreeBSD ncr driver.
11**
12** Copyright (C) 1994 Wolfgang Stanglmeier
13**
14**-----------------------------------------------------------------------------
15**
16** This program is free software; you can redistribute it and/or modify
17** it under the terms of the GNU General Public License as published by
18** the Free Software Foundation; either version 2 of the License, or
19** (at your option) any later version.
20**
21** This program is distributed in the hope that it will be useful,
22** but WITHOUT ANY WARRANTY; without even the implied warranty of
23** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24** GNU General Public License for more details.
25**
26** You should have received a copy of the GNU General Public License
27** along with this program; if not, write to the Free Software
28** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29**
30**-----------------------------------------------------------------------------
31**
32** The Linux port of the FreeBSD ncr driver has been achieved in
33** november 1995 by:
34**
35** Gerard Roudier <groudier@free.fr>
36**
37** Being given that this driver originates from the FreeBSD version, and
38** in order to keep synergy on both, any suggested enhancements and corrections
39** received on Linux are automatically a potential candidate for the FreeBSD
40** version.
41**
42** The original driver has been written for 386bsd and FreeBSD by
43** Wolfgang Stanglmeier <wolf@cologne.de>
44** Stefan Esser <se@mi.Uni-Koeln.de>
45**
46**-----------------------------------------------------------------------------
47**
48** Major contributions:
49** --------------------
50**
51** NVRAM detection and reading.
52** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53**
54** Added support for MIPS big endian systems.
55** Carsten Langgaard, carstenl@mips.com
56** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
57**
58** Added support for HP PARISC big endian systems.
59** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
60**
61*******************************************************************************
62*/
63
64#ifndef SYM53C8XX_DEFS_H
65#define SYM53C8XX_DEFS_H
66
67#include <linux/config.h>
68
69/*
70** If you want a driver as small as possible, donnot define the
71** following options.
72*/
73#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
74#define SCSI_NCR_DEBUG_INFO_SUPPORT
75
76/*
77** To disable integrity checking, do not define the
78** following option.
79*/
80#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
81# define SCSI_NCR_ENABLE_INTEGRITY_CHECK
82#endif
83
84/* ---------------------------------------------------------------------
85** Take into account kernel configured parameters.
86** Most of these options can be overridden at startup by a command line.
87** ---------------------------------------------------------------------
88*/
89
90/*
91 * For Ultra2 and Ultra3 SCSI support option, use special features.
92 *
93 * Value (default) means:
94 * bit 0 : all features enabled, except:
95 * bit 1 : PCI Write And Invalidate.
96 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
97 *
98 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
99 * enabled by the driver.
100 */
101#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
102
103#define SCSI_NCR_MAX_SYNC (80)
104
105/*
106 * Allow tags from 2 to 256, default 8
107 */
108#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
109#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
110#define SCSI_NCR_MAX_TAGS (2)
111#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
112#define SCSI_NCR_MAX_TAGS (256)
113#else
114#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
115#endif
116#else
117#define SCSI_NCR_MAX_TAGS (8)
118#endif
119
120/*
121 * Allow tagged command queuing support if configured with default number
122 * of tags set to max (see above).
123 */
124#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
125#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
126#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
127#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
128#else
129#define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
130#endif
131
132/*
133 * Immediate arbitration
134 */
135#if defined(CONFIG_SCSI_NCR53C8XX_IARB)
136#define SCSI_NCR_IARB_SUPPORT
137#endif
138
139/*
140 * Sync transfer frequency at startup.
141 * Allow from 5Mhz to 80Mhz default 20 Mhz.
142 */
143#ifndef CONFIG_SCSI_NCR53C8XX_SYNC
144#define CONFIG_SCSI_NCR53C8XX_SYNC (20)
145#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
146#undef CONFIG_SCSI_NCR53C8XX_SYNC
147#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
148#endif
149
150#if CONFIG_SCSI_NCR53C8XX_SYNC == 0
151#define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
152#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
153#define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
154#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
155#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
156#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
157#define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
158#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
159#define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
160#else
161#define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
162#endif
163
164/*
165 * Disallow disconnections at boot-up
166 */
167#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
168#define SCSI_NCR_SETUP_DISCONNECTION (0)
169#else
170#define SCSI_NCR_SETUP_DISCONNECTION (1)
171#endif
172
173/*
174 * Force synchronous negotiation for all targets
175 */
176#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
177#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
178#else
179#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
180#endif
181
182/*
183 * Disable master parity checking (flawed hardwares need that)
184 */
185#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
186#define SCSI_NCR_SETUP_MASTER_PARITY (0)
187#else
188#define SCSI_NCR_SETUP_MASTER_PARITY (1)
189#endif
190
191/*
192 * Disable scsi parity checking (flawed devices may need that)
193 */
194#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
195#define SCSI_NCR_SETUP_SCSI_PARITY (0)
196#else
197#define SCSI_NCR_SETUP_SCSI_PARITY (1)
198#endif
199
200/*
201 * Settle time after reset at boot-up
202 */
203#define SCSI_NCR_SETUP_SETTLE_TIME (2)
204
205/*
206** Bridge quirks work-around option defaulted to 1.
207*/
208#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
209#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
210#endif
211
212/*
213** Work-around common bridge misbehaviour.
214**
215** - Do not flush posted writes in the opposite
216** direction on read.
217** - May reorder DMA writes to memory.
218**
219** This option should not affect performances
220** significantly, so it is the default.
221*/
222#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
223#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
224#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
225#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
226
227/*
228** Same as option 1, but also deal with
229** misconfigured interrupts.
230**
231** - Edge triggerred instead of level sensitive.
232** - No interrupt line connected.
233** - IRQ number misconfigured.
234**
235** If no interrupt is delivered, the driver will
236** catch the interrupt conditions 10 times per
237** second. No need to say that this option is
238** not recommended.
239*/
240#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
241#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
242#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
243#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
244#define SCSI_NCR_PCIQ_BROKEN_INTR
245
246/*
247** Some bridge designers decided to flush
248** everything prior to deliver the interrupt.
249** This option tries to deal with such a
250** behaviour.
251*/
252#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
253#define SCSI_NCR_PCIQ_SYNC_ON_INTR
254#endif
255
256/*
257** Other parameters not configurable with "make config"
258** Avoid to change these constants, unless you know what you are doing.
259*/
260
261#define SCSI_NCR_ALWAYS_SIMPLE_TAG
262#define SCSI_NCR_MAX_SCATTER (127)
263#define SCSI_NCR_MAX_TARGET (16)
264
265/*
266** Compute some desirable value for CAN_QUEUE
267** and CMD_PER_LUN.
268** The driver will use lower values if these
269** ones appear to be too large.
270*/
271#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
272#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
273
274#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
275#define SCSI_NCR_TIMER_INTERVAL (HZ)
276
277#if 1 /* defined CONFIG_SCSI_MULTI_LUN */
278#define SCSI_NCR_MAX_LUN (16)
279#else
280#define SCSI_NCR_MAX_LUN (1)
281#endif
282
283/*
284 * IO functions definition for big/little endian CPU support.
285 * For now, the NCR is only supported in little endian addressing mode,
286 */
287
288#ifdef __BIG_ENDIAN
289
290#define inw_l2b inw
291#define inl_l2b inl
292#define outw_b2l outw
293#define outl_b2l outl
294
295#define readb_raw readb
296#define writeb_raw writeb
297
298#if defined(SCSI_NCR_BIG_ENDIAN)
299#define readw_l2b __raw_readw
300#define readl_l2b __raw_readl
301#define writew_b2l __raw_writew
302#define writel_b2l __raw_writel
303#define readw_raw __raw_readw
304#define readl_raw __raw_readl
305#define writew_raw __raw_writew
306#define writel_raw __raw_writel
307#else /* Other big-endian */
308#define readw_l2b readw
309#define readl_l2b readl
310#define writew_b2l writew
311#define writel_b2l writel
312#define readw_raw readw
313#define readl_raw readl
314#define writew_raw writew
315#define writel_raw writel
316#endif
317
318#else /* little endian */
319
320#define inw_raw inw
321#define inl_raw inl
322#define outw_raw outw
323#define outl_raw outl
324
325#define readb_raw readb
326#define readw_raw readw
327#define readl_raw readl
328#define writeb_raw writeb
329#define writew_raw writew
330#define writel_raw writel
331
332#endif
333
334#if !defined(__hppa__) && !defined(__mips__)
335#ifdef SCSI_NCR_BIG_ENDIAN
336#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
337#endif
338#endif
339
340#define MEMORY_BARRIER() mb()
341
342
343/*
344 * If the NCR uses big endian addressing mode over the
345 * PCI, actual io register addresses for byte and word
346 * accesses must be changed according to lane routing.
347 * Btw, ncr_offb() and ncr_offw() macros only apply to
348 * constants and so donnot generate bloated code.
349 */
350
351#if defined(SCSI_NCR_BIG_ENDIAN)
352
353#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
354#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
355
356#else
357
358#define ncr_offb(o) (o)
359#define ncr_offw(o) (o)
360
361#endif
362
363/*
364 * If the CPU and the NCR use same endian-ness addressing,
365 * no byte reordering is needed for script patching.
366 * Macro cpu_to_scr() is to be used for script patching.
367 * Macro scr_to_cpu() is to be used for getting a DWORD
368 * from the script.
369 */
370
371#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
372
373#define cpu_to_scr(dw) cpu_to_le32(dw)
374#define scr_to_cpu(dw) le32_to_cpu(dw)
375
376#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
377
378#define cpu_to_scr(dw) cpu_to_be32(dw)
379#define scr_to_cpu(dw) be32_to_cpu(dw)
380
381#else
382
383#define cpu_to_scr(dw) (dw)
384#define scr_to_cpu(dw) (dw)
385
386#endif
387
388/*
389 * Access to the controller chip.
390 *
391 * If the CPU and the NCR use same endian-ness addressing,
392 * no byte reordering is needed for accessing chip io
393 * registers. Functions suffixed by '_raw' are assumed
394 * to access the chip over the PCI without doing byte
395 * reordering. Functions suffixed by '_l2b' are
396 * assumed to perform little-endian to big-endian byte
397 * reordering, those suffixed by '_b2l' blah, blah,
398 * blah, ...
399 */
400
401/*
402 * MEMORY mapped IO input / output
403 */
404
405#define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
406#define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
407
408#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
409
410#define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
411#define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
412
413#define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
414#define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
415
416#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
417
418#define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
419#define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
420
421#define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
422#define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
423
424#else
425
426#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
427/* Only 8 or 32 bit transfers allowed */
428#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
429#else
430#define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
431#endif
432#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
433
434#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
435/* Only 8 or 32 bit transfers allowed */
436#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
437#else
438#define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
439#endif
440#define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
441
442#endif
443
444#define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
445#define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
446#define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
447
448#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
449#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
450#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
451
452/*
453 * Set bit field ON, OFF
454 */
455
456#define OUTONB(r, m) OUTB(r, INB(r) | (m))
457#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
458#define OUTONW(r, m) OUTW(r, INW(r) | (m))
459#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
460#define OUTONL(r, m) OUTL(r, INL(r) | (m))
461#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
462
463/*
464 * We normally want the chip to have a consistent view
465 * of driver internal data structures when we restart it.
466 * Thus these macros.
467 */
468#define OUTL_DSP(v) \
469 do { \
470 MEMORY_BARRIER(); \
471 OUTL (nc_dsp, (v)); \
472 } while (0)
473
474#define OUTONB_STD() \
475 do { \
476 MEMORY_BARRIER(); \
477 OUTONB (nc_dcntl, (STD|NOCOM)); \
478 } while (0)
479
480
481/*
482** NCR53C8XX devices features table.
483*/
484struct ncr_chip {
485 unsigned short revision_id;
486 unsigned char burst_max; /* log-base-2 of max burst */
487 unsigned char offset_max;
488 unsigned char nr_divisor;
489 unsigned int features;
490#define FE_LED0 (1<<0)
491#define FE_WIDE (1<<1) /* Wide data transfers */
492#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
493#define FE_DBLR (1<<4) /* Clock doubler present */
494#define FE_QUAD (1<<5) /* Clock quadrupler present */
495#define FE_ERL (1<<6) /* Enable read line */
496#define FE_CLSE (1<<7) /* Cache line size enable */
497#define FE_WRIE (1<<8) /* Write & Invalidate enable */
498#define FE_ERMP (1<<9) /* Enable read multiple */
499#define FE_BOF (1<<10) /* Burst opcode fetch */
500#define FE_DFS (1<<11) /* DMA fifo size */
501#define FE_PFEN (1<<12) /* Prefetch enable */
502#define FE_LDSTR (1<<13) /* Load/Store supported */
503#define FE_RAM (1<<14) /* On chip RAM present */
504#define FE_VARCLK (1<<15) /* SCSI clock may vary */
505#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
506#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
507#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
508#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
509#define FE_LEDC (1<<20) /* Hardware control of LED */
510#define FE_DIFF (1<<21) /* Support Differential SCSI */
511#define FE_66MHZ (1<<23) /* 66MHz PCI Support */
512#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
513#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
514#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
515#define FE_EHP (1<<27) /* 720: Even host parity */
516#define FE_MUX (1<<28) /* 720: Multiplexed bus */
517#define FE_EA (1<<29) /* 720: Enable Ack */
518
519#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
520#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
521#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
522};
523
524
525/*
526** Driver setup structure.
527**
528** This structure is initialized from linux config options.
529** It can be overridden at boot-up by the boot command line.
530*/
531#define SCSI_NCR_MAX_EXCLUDES 8
532struct ncr_driver_setup {
533 u8 master_parity;
534 u8 scsi_parity;
535 u8 disconnection;
536 u8 special_features;
537 u8 force_sync_nego;
538 u8 reverse_probe;
539 u8 pci_fix_up;
540 u8 use_nvram;
541 u8 verbose;
542 u8 default_tags;
543 u16 default_sync;
544 u16 debug;
545 u8 burst_max;
546 u8 led_pin;
547 u8 max_wide;
548 u8 settle_delay;
549 u8 diff_support;
550 u8 irqm;
551 u8 bus_check;
552 u8 optimize;
553 u8 recovery;
554 u8 host_id;
555 u16 iarb;
556 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
557 char tag_ctrl[100];
558};
559
560/*
561** Initial setup.
562** Can be overriden at startup by a command line.
563*/
564#define SCSI_NCR_DRIVER_SETUP \
565{ \
566 SCSI_NCR_SETUP_MASTER_PARITY, \
567 SCSI_NCR_SETUP_SCSI_PARITY, \
568 SCSI_NCR_SETUP_DISCONNECTION, \
569 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
570 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
571 0, \
572 0, \
573 1, \
574 0, \
575 SCSI_NCR_SETUP_DEFAULT_TAGS, \
576 SCSI_NCR_SETUP_DEFAULT_SYNC, \
577 0x00, \
578 7, \
579 0, \
580 1, \
581 SCSI_NCR_SETUP_SETTLE_TIME, \
582 0, \
583 0, \
584 1, \
585 0, \
586 0, \
587 255, \
588 0x00 \
589}
590
591/*
592** Boot fail safe setup.
593** Override initial setup from boot command line:
594** ncr53c8xx=safe:y
595*/
596#define SCSI_NCR_DRIVER_SAFE_SETUP \
597{ \
598 0, \
599 1, \
600 0, \
601 0, \
602 0, \
603 0, \
604 0, \
605 1, \
606 2, \
607 0, \
608 255, \
609 0x00, \
610 255, \
611 0, \
612 0, \
613 10, \
614 1, \
615 1, \
616 1, \
617 0, \
618 0, \
619 255 \
620}
621
622/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
623
624/*-----------------------------------------------------------------
625**
626** The ncr 53c810 register structure.
627**
628**-----------------------------------------------------------------
629*/
630
631struct ncr_reg {
632/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
633
634/*01*/ u8 nc_scntl1; /* no reset */
635 #define ISCON 0x10 /* connected to scsi */
636 #define CRST 0x08 /* force reset */
637 #define IARB 0x02 /* immediate arbitration */
638
639/*02*/ u8 nc_scntl2; /* no disconnect expected */
640 #define SDU 0x80 /* cmd: disconnect will raise error */
641 #define CHM 0x40 /* sta: chained mode */
642 #define WSS 0x08 /* sta: wide scsi send [W]*/
643 #define WSR 0x01 /* sta: wide scsi received [W]*/
644
645/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
646 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
647 #define ULTRA 0x80 /* cmd: ULTRA enable */
648 /* bits 0-2, 7 rsvd for C1010 */
649
650/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
651 #define RRE 0x40 /* r/w:e enable response to resel. */
652 #define SRE 0x20 /* r/w:e enable response to select */
653
654/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
655 /* bits 6-7 rsvd for C1010 */
656
657/*06*/ u8 nc_sdid; /* ### Destination-ID */
658
659/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
660
661/*08*/ u8 nc_sfbr; /* ### First byte in phase */
662
663/*09*/ u8 nc_socl;
664 #define CREQ 0x80 /* r/w: SCSI-REQ */
665 #define CACK 0x40 /* r/w: SCSI-ACK */
666 #define CBSY 0x20 /* r/w: SCSI-BSY */
667 #define CSEL 0x10 /* r/w: SCSI-SEL */
668 #define CATN 0x08 /* r/w: SCSI-ATN */
669 #define CMSG 0x04 /* r/w: SCSI-MSG */
670 #define CC_D 0x02 /* r/w: SCSI-C_D */
671 #define CI_O 0x01 /* r/w: SCSI-I_O */
672
673/*0a*/ u8 nc_ssid;
674
675/*0b*/ u8 nc_sbcl;
676
677/*0c*/ u8 nc_dstat;
678 #define DFE 0x80 /* sta: dma fifo empty */
679 #define MDPE 0x40 /* int: master data parity error */
680 #define BF 0x20 /* int: script: bus fault */
681 #define ABRT 0x10 /* int: script: command aborted */
682 #define SSI 0x08 /* int: script: single step */
683 #define SIR 0x04 /* int: script: interrupt instruct. */
684 #define IID 0x01 /* int: script: illegal instruct. */
685
686/*0d*/ u8 nc_sstat0;
687 #define ILF 0x80 /* sta: data in SIDL register lsb */
688 #define ORF 0x40 /* sta: data in SODR register lsb */
689 #define OLF 0x20 /* sta: data in SODL register lsb */
690 #define AIP 0x10 /* sta: arbitration in progress */
691 #define LOA 0x08 /* sta: arbitration lost */
692 #define WOA 0x04 /* sta: arbitration won */
693 #define IRST 0x02 /* sta: scsi reset signal */
694 #define SDP 0x01 /* sta: scsi parity signal */
695
696/*0e*/ u8 nc_sstat1;
697 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
698
699/*0f*/ u8 nc_sstat2;
700 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
701 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
702 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
703 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
704 #define LDSC 0x02 /* sta: disconnect & reconnect */
705
706/*10*/ u8 nc_dsa; /* --> Base page */
707/*11*/ u8 nc_dsa1;
708/*12*/ u8 nc_dsa2;
709/*13*/ u8 nc_dsa3;
710
711/*14*/ u8 nc_istat; /* --> Main Command and status */
712 #define CABRT 0x80 /* cmd: abort current operation */
713 #define SRST 0x40 /* mod: reset chip */
714 #define SIGP 0x20 /* r/w: message from host to ncr */
715 #define SEM 0x10 /* r/w: message between host + ncr */
716 #define CON 0x08 /* sta: connected to scsi */
717 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
718 #define SIP 0x02 /* sta: scsi-interrupt */
719 #define DIP 0x01 /* sta: host/script interrupt */
720
721/*15*/ u8 nc_istat1; /* 896 and later cores only */
722 #define FLSH 0x04 /* sta: chip is flushing */
723 #define SRUN 0x02 /* sta: scripts are running */
724 #define SIRQD 0x01 /* r/w: disable INT pin */
725
726/*16*/ u8 nc_mbox0; /* 896 and later cores only */
727/*17*/ u8 nc_mbox1; /* 896 and later cores only */
728
729/*18*/ u8 nc_ctest0;
730 #define EHP 0x04 /* 720 even host parity */
731/*19*/ u8 nc_ctest1;
732
733/*1a*/ u8 nc_ctest2;
734 #define CSIGP 0x40
735 /* bits 0-2,7 rsvd for C1010 */
736
737/*1b*/ u8 nc_ctest3;
738 #define FLF 0x08 /* cmd: flush dma fifo */
739 #define CLF 0x04 /* cmd: clear dma fifo */
740 #define FM 0x02 /* mod: fetch pin mode */
741 #define WRIE 0x01 /* mod: write and invalidate enable */
742 /* bits 4-7 rsvd for C1010 */
743
744/*1c*/ u32 nc_temp; /* ### Temporary stack */
745
746/*20*/ u8 nc_dfifo;
747/*21*/ u8 nc_ctest4;
748 #define MUX 0x80 /* 720 host bus multiplex mode */
749 #define BDIS 0x80 /* mod: burst disable */
750 #define MPEE 0x08 /* mod: master parity error enable */
751
752/*22*/ u8 nc_ctest5;
753 #define DFS 0x20 /* mod: dma fifo size */
754 /* bits 0-1, 3-7 rsvd for C1010 */
755/*23*/ u8 nc_ctest6;
756
757/*24*/ u32 nc_dbc; /* ### Byte count and command */
758/*28*/ u32 nc_dnad; /* ### Next command register */
759/*2c*/ u32 nc_dsp; /* --> Script Pointer */
760/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
761
762/*34*/ u8 nc_scratcha; /* Temporary register a */
763/*35*/ u8 nc_scratcha1;
764/*36*/ u8 nc_scratcha2;
765/*37*/ u8 nc_scratcha3;
766
767/*38*/ u8 nc_dmode;
768 #define BL_2 0x80 /* mod: burst length shift value +2 */
769 #define BL_1 0x40 /* mod: burst length shift value +1 */
770 #define ERL 0x08 /* mod: enable read line */
771 #define ERMP 0x04 /* mod: enable read multiple */
772 #define BOF 0x02 /* mod: burst op code fetch */
773
774/*39*/ u8 nc_dien;
775/*3a*/ u8 nc_sbr;
776
777/*3b*/ u8 nc_dcntl; /* --> Script execution control */
778 #define CLSE 0x80 /* mod: cache line size enable */
779 #define PFF 0x40 /* cmd: pre-fetch flush */
780 #define PFEN 0x20 /* mod: pre-fetch enable */
781 #define EA 0x20 /* mod: 720 enable-ack */
782 #define SSM 0x10 /* mod: single step mode */
783 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
784 #define STD 0x04 /* cmd: start dma mode */
785 #define IRQD 0x02 /* mod: irq disable */
786 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
787 /* bits 0-1 rsvd for C1010 */
788
789/*3c*/ u32 nc_adder;
790
791/*40*/ u16 nc_sien; /* -->: interrupt enable */
792/*42*/ u16 nc_sist; /* <--: interrupt status */
793 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
794 #define STO 0x0400/* sta: timeout (select) */
795 #define GEN 0x0200/* sta: timeout (general) */
796 #define HTH 0x0100/* sta: timeout (handshake) */
797 #define MA 0x80 /* sta: phase mismatch */
798 #define CMP 0x40 /* sta: arbitration complete */
799 #define SEL 0x20 /* sta: selected by another device */
800 #define RSL 0x10 /* sta: reselected by another device*/
801 #define SGE 0x08 /* sta: gross error (over/underflow)*/
802 #define UDC 0x04 /* sta: unexpected disconnect */
803 #define RST 0x02 /* sta: scsi bus reset detected */
804 #define PAR 0x01 /* sta: scsi parity error */
805
806/*44*/ u8 nc_slpar;
807/*45*/ u8 nc_swide;
808/*46*/ u8 nc_macntl;
809/*47*/ u8 nc_gpcntl;
810/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
811/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
812/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
813
814/*4c*/ u8 nc_stest0;
815
816/*4d*/ u8 nc_stest1;
817 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
818 #define DBLEN 0x08 /* clock doubler running */
819 #define DBLSEL 0x04 /* clock doubler selected */
820
821
822/*4e*/ u8 nc_stest2;
823 #define ROF 0x40 /* reset scsi offset (after gross error!) */
824 #define DIF 0x20 /* 720 SCSI differential mode */
825 #define EXT 0x02 /* extended filtering */
826
827/*4f*/ u8 nc_stest3;
828 #define TE 0x80 /* c: tolerAnt enable */
829 #define HSC 0x20 /* c: Halt SCSI Clock */
830 #define CSF 0x02 /* c: clear scsi fifo */
831
832/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
833/*52*/ u8 nc_stest4;
834 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
835 #define SMODE_HVD 0x40 /* High Voltage Differential */
836 #define SMODE_SE 0x80 /* Single Ended */
837 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
838 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
839 /* bits 0-5 rsvd for C1010 */
840
841/*53*/ u8 nc_53_;
842/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
843/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
844 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
845 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
846 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
847 #define DISFC 0x10 /* Disable Auto FIFO Clear */
848 #define DILS 0x02 /* Disable Internal Load/Store */
849 #define DPR 0x01 /* Disable Pipe Req */
850
851/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
852 #define ZMOD 0x80 /* High Impedance Mode */
853 #define DIC 0x10 /* Disable Internal Cycles */
854 #define DDAC 0x08 /* Disable Dual Address Cycle */
855 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
856 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
857 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
858
859/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
860/*5a*/ u16 nc_5a_;
861
862/*5c*/ u8 nc_scr0; /* Working register B */
863/*5d*/ u8 nc_scr1; /* */
864/*5e*/ u8 nc_scr2; /* */
865/*5f*/ u8 nc_scr3; /* */
866
867/*60*/ u8 nc_scrx[64]; /* Working register C-R */
868/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
869/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
870/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
871/*ac*/ u32 nc_drs; /* DSA Relative Selector */
872/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
873/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
874/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
875/*bc*/ u16 nc_scntl4; /* C1010 only */
876 #define U3EN 0x80 /* Enable Ultra 3 */
877 #define AIPEN 0x40 /* Allow check upper byte lanes */
878 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
879 transfer edge */
880 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
881 transfer edge */
882
883/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
884/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
885
886/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
887/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
888/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
889/*c9*/ u8 nc_rbc1; /* */
890/*ca*/ u8 nc_rbc2; /* */
891/*cb*/ u8 nc_rbc3; /* */
892
893/*cc*/ u8 nc_ua; /* Updated Address */
894/*cd*/ u8 nc_ua1; /* */
895/*ce*/ u8 nc_ua2; /* */
896/*cf*/ u8 nc_ua3; /* */
897/*d0*/ u32 nc_esa; /* Entry Storage Address */
898/*d4*/ u8 nc_ia; /* Instruction Address */
899/*d5*/ u8 nc_ia1;
900/*d6*/ u8 nc_ia2;
901/*d7*/ u8 nc_ia3;
902/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
903/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
904
905 /* Following for C1010 only */
906/*e0*/ u16 nc_crcpad; /* CRC Value */
907/*e2*/ u8 nc_crccntl0; /* CRC control register */
908 #define SNDCRC 0x10 /* Send CRC Request */
909/*e3*/ u8 nc_crccntl1; /* CRC control register */
910/*e4*/ u32 nc_crcdata; /* CRC data register */
911/*e8*/ u32 nc_e8_; /* rsvd */
912/*ec*/ u32 nc_ec_; /* rsvd */
913/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
914
915};
916
917/*-----------------------------------------------------------
918**
919** Utility macros for the script.
920**
921**-----------------------------------------------------------
922*/
923
924#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
925#define REG(r) REGJ (nc_, r)
926
927typedef u32 ncrcmd;
928
929/*-----------------------------------------------------------
930**
931** SCSI phases
932**
933** DT phases illegal for ncr driver.
934**
935**-----------------------------------------------------------
936*/
937
938#define SCR_DATA_OUT 0x00000000
939#define SCR_DATA_IN 0x01000000
940#define SCR_COMMAND 0x02000000
941#define SCR_STATUS 0x03000000
942#define SCR_DT_DATA_OUT 0x04000000
943#define SCR_DT_DATA_IN 0x05000000
944#define SCR_MSG_OUT 0x06000000
945#define SCR_MSG_IN 0x07000000
946
947#define SCR_ILG_OUT 0x04000000
948#define SCR_ILG_IN 0x05000000
949
950/*-----------------------------------------------------------
951**
952** Data transfer via SCSI.
953**
954**-----------------------------------------------------------
955**
956** MOVE_ABS (LEN)
957** <<start address>>
958**
959** MOVE_IND (LEN)
960** <<dnad_offset>>
961**
962** MOVE_TBL
963** <<dnad_offset>>
964**
965**-----------------------------------------------------------
966*/
967
968#define OPC_MOVE 0x08000000
969
970#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
971#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
972#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
973
974#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
975#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
976#define SCR_CHMOV_TBL (0x10000000)
977
978struct scr_tblmove {
979 u32 size;
980 u32 addr;
981};
982
983/*-----------------------------------------------------------
984**
985** Selection
986**
987**-----------------------------------------------------------
988**
989** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
990** <<alternate_address>>
991**
992** SEL_TBL | << dnad_offset>> [ | REL_JMP]
993** <<alternate_address>>
994**
995**-----------------------------------------------------------
996*/
997
998#define SCR_SEL_ABS 0x40000000
999#define SCR_SEL_ABS_ATN 0x41000000
1000#define SCR_SEL_TBL 0x42000000
1001#define SCR_SEL_TBL_ATN 0x43000000
1002
1003
1004#ifdef SCSI_NCR_BIG_ENDIAN
1005struct scr_tblsel {
1006 u8 sel_scntl3;
1007 u8 sel_id;
1008 u8 sel_sxfer;
1009 u8 sel_scntl4;
1010};
1011#else
1012struct scr_tblsel {
1013 u8 sel_scntl4;
1014 u8 sel_sxfer;
1015 u8 sel_id;
1016 u8 sel_scntl3;
1017};
1018#endif
1019
1020#define SCR_JMP_REL 0x04000000
1021#define SCR_ID(id) (((u32)(id)) << 16)
1022
1023/*-----------------------------------------------------------
1024**
1025** Waiting for Disconnect or Reselect
1026**
1027**-----------------------------------------------------------
1028**
1029** WAIT_DISC
1030** dummy: <<alternate_address>>
1031**
1032** WAIT_RESEL
1033** <<alternate_address>>
1034**
1035**-----------------------------------------------------------
1036*/
1037
1038#define SCR_WAIT_DISC 0x48000000
1039#define SCR_WAIT_RESEL 0x50000000
1040
1041/*-----------------------------------------------------------
1042**
1043** Bit Set / Reset
1044**
1045**-----------------------------------------------------------
1046**
1047** SET (flags {|.. })
1048**
1049** CLR (flags {|.. })
1050**
1051**-----------------------------------------------------------
1052*/
1053
1054#define SCR_SET(f) (0x58000000 | (f))
1055#define SCR_CLR(f) (0x60000000 | (f))
1056
1057#define SCR_CARRY 0x00000400
1058#define SCR_TRG 0x00000200
1059#define SCR_ACK 0x00000040
1060#define SCR_ATN 0x00000008
1061
1062
1063
1064
1065/*-----------------------------------------------------------
1066**
1067** Memory to memory move
1068**
1069**-----------------------------------------------------------
1070**
1071** COPY (bytecount)
1072** << source_address >>
1073** << destination_address >>
1074**
1075** SCR_COPY sets the NO FLUSH option by default.
1076** SCR_COPY_F does not set this option.
1077**
1078** For chips which do not support this option,
1079** ncr_copy_and_bind() will remove this bit.
1080**-----------------------------------------------------------
1081*/
1082
1083#define SCR_NO_FLUSH 0x01000000
1084
1085#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1086#define SCR_COPY_F(n) (0xc0000000 | (n))
1087
1088/*-----------------------------------------------------------
1089**
1090** Register move and binary operations
1091**
1092**-----------------------------------------------------------
1093**
1094** SFBR_REG (reg, op, data) reg = SFBR op data
1095** << 0 >>
1096**
1097** REG_SFBR (reg, op, data) SFBR = reg op data
1098** << 0 >>
1099**
1100** REG_REG (reg, op, data) reg = reg op data
1101** << 0 >>
1102**
1103**-----------------------------------------------------------
1104** On 810A, 860, 825A, 875, 895 and 896 chips the content
1105** of SFBR register can be used as data (SCR_SFBR_DATA).
1106** The 896 has additionnal IO registers starting at
1107** offset 0x80. Bit 7 of register offset is stored in
1108** bit 7 of the SCRIPTS instruction first DWORD.
1109**-----------------------------------------------------------
1110*/
1111
1112#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1113
1114#define SCR_SFBR_REG(reg,op,data) \
1115 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1116
1117#define SCR_REG_SFBR(reg,op,data) \
1118 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1119
1120#define SCR_REG_REG(reg,op,data) \
1121 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1122
1123
1124#define SCR_LOAD 0x00000000
1125#define SCR_SHL 0x01000000
1126#define SCR_OR 0x02000000
1127#define SCR_XOR 0x03000000
1128#define SCR_AND 0x04000000
1129#define SCR_SHR 0x05000000
1130#define SCR_ADD 0x06000000
1131#define SCR_ADDC 0x07000000
1132
1133#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1134
1135/*-----------------------------------------------------------
1136**
1137** FROM_REG (reg) SFBR = reg
1138** << 0 >>
1139**
1140** TO_REG (reg) reg = SFBR
1141** << 0 >>
1142**
1143** LOAD_REG (reg, data) reg = <data>
1144** << 0 >>
1145**
1146** LOAD_SFBR(data) SFBR = <data>
1147** << 0 >>
1148**
1149**-----------------------------------------------------------
1150*/
1151
1152#define SCR_FROM_REG(reg) \
1153 SCR_REG_SFBR(reg,SCR_OR,0)
1154
1155#define SCR_TO_REG(reg) \
1156 SCR_SFBR_REG(reg,SCR_OR,0)
1157
1158#define SCR_LOAD_REG(reg,data) \
1159 SCR_REG_REG(reg,SCR_LOAD,data)
1160
1161#define SCR_LOAD_SFBR(data) \
1162 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1163
1164/*-----------------------------------------------------------
1165**
1166** LOAD from memory to register.
1167** STORE from register to memory.
1168**
1169** Only supported by 810A, 860, 825A, 875, 895 and 896.
1170**
1171**-----------------------------------------------------------
1172**
1173** LOAD_ABS (LEN)
1174** <<start address>>
1175**
1176** LOAD_REL (LEN) (DSA relative)
1177** <<dsa_offset>>
1178**
1179**-----------------------------------------------------------
1180*/
1181
1182#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1183#define SCR_NO_FLUSH2 0x02000000
1184#define SCR_DSA_REL2 0x10000000
1185
1186#define SCR_LOAD_R(reg, how, n) \
1187 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1188
1189#define SCR_STORE_R(reg, how, n) \
1190 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1191
1192#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1193#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1194#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1195#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1196
1197#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1198#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1199#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1200#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1201
1202
1203/*-----------------------------------------------------------
1204**
1205** Waiting for Disconnect or Reselect
1206**
1207**-----------------------------------------------------------
1208**
1209** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1210** <<address>>
1211**
1212** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1213** <<distance>>
1214**
1215** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1216** <<address>>
1217**
1218** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1219** <<distance>>
1220**
1221** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1222** <<dummy>>
1223**
1224** INT [ | IFTRUE/IFFALSE ( ... ) ]
1225** <<ident>>
1226**
1227** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1228** <<ident>>
1229**
1230** Conditions:
1231** WHEN (phase)
1232** IF (phase)
1233** CARRYSET
1234** DATA (data, mask)
1235**
1236**-----------------------------------------------------------
1237*/
1238
1239#define SCR_NO_OP 0x80000000
1240#define SCR_JUMP 0x80080000
1241#define SCR_JUMP64 0x80480000
1242#define SCR_JUMPR 0x80880000
1243#define SCR_CALL 0x88080000
1244#define SCR_CALLR 0x88880000
1245#define SCR_RETURN 0x90080000
1246#define SCR_INT 0x98080000
1247#define SCR_INT_FLY 0x98180000
1248
1249#define IFFALSE(arg) (0x00080000 | (arg))
1250#define IFTRUE(arg) (0x00000000 | (arg))
1251
1252#define WHEN(phase) (0x00030000 | (phase))
1253#define IF(phase) (0x00020000 | (phase))
1254
1255#define DATA(D) (0x00040000 | ((D) & 0xff))
1256#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1257
1258#define CARRYSET (0x00200000)
1259
1260/*-----------------------------------------------------------
1261**
1262** SCSI constants.
1263**
1264**-----------------------------------------------------------
1265*/
1266
1267/*
1268** Messages
1269*/
1270
1271#define M_COMPLETE COMMAND_COMPLETE
1272#define M_EXTENDED EXTENDED_MESSAGE
1273#define M_SAVE_DP SAVE_POINTERS
1274#define M_RESTORE_DP RESTORE_POINTERS
1275#define M_DISCONNECT DISCONNECT
1276#define M_ID_ERROR INITIATOR_ERROR
1277#define M_ABORT ABORT_TASK_SET
1278#define M_REJECT MESSAGE_REJECT
1279#define M_NOOP NOP
1280#define M_PARITY MSG_PARITY_ERROR
1281#define M_LCOMPLETE LINKED_CMD_COMPLETE
1282#define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
1283#define M_RESET TARGET_RESET
1284#define M_ABORT_TAG ABORT_TASK
1285#define M_CLEAR_QUEUE CLEAR_TASK_SET
1286#define M_INIT_REC INITIATE_RECOVERY
1287#define M_REL_REC RELEASE_RECOVERY
1288#define M_TERMINATE (0x11)
1289#define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
1290#define M_HEAD_TAG HEAD_OF_QUEUE_TAG
1291#define M_ORDERED_TAG ORDERED_QUEUE_TAG
1292#define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
1293#define M_IDENTIFY (0x80)
1294
1295#define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
1296#define M_X_SYNC_REQ EXTENDED_SDTR
1297#define M_X_WIDE_REQ EXTENDED_WDTR
1298#define M_X_PPR_REQ EXTENDED_PPR
1299
1300/*
1301** Status
1302*/
1303
1304#define S_GOOD (0x00)
1305#define S_CHECK_COND (0x02)
1306#define S_COND_MET (0x04)
1307#define S_BUSY (0x08)
1308#define S_INT (0x10)
1309#define S_INT_COND_MET (0x14)
1310#define S_CONFLICT (0x18)
1311#define S_TERMINATED (0x20)
1312#define S_QUEUE_FULL (0x28)
1313#define S_ILLEGAL (0xff)
1314#define S_SENSE (0x80)
1315
1316/*
1317 * End of ncrreg from FreeBSD
1318 */
1319
1320#endif /* defined SYM53C8XX_DEFS_H */