tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/ppc/boot/simple/mv64x60_tty.c
3 *
4 * Bootloader version of the embedded MPSC/UART driver for the Marvell 64x60.
5 * Note: Due to a GT64260A erratum, DMA will be used for UART input (via SDMA).
6 *
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * 2001 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15/* This code assumes that the data cache has been disabled (L1, L2, L3). */
16
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/serial_reg.h>
20#include <asm/serial.h>
21#include <asm/io.h>
22#include <asm/mv64x60_defs.h>
23#include <mpsc_defs.h>
24
25#ifdef CONFIG_EV64360
26#include <platforms/ev64360.h>
27u32 mv64x60_console_baud = EV64360_DEFAULT_BAUD;
28u32 mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; /* TCLK */
29u32 mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ;
30#else
31u32 mv64x60_console_baud = 9600;
32u32 mv64x60_mpsc_clk_src = 8; /* TCLK */
33u32 mv64x60_mpsc_clk_freq = 100000000;
34#endif
35
36extern void udelay(long);
37static void stop_dma(int chan);
38
39static void __iomem *mv64x60_base = (void __iomem *)CONFIG_MV64X60_NEW_BASE;
40
41struct sdma_regs {
42 u32 sdc;
43 u32 sdcm;
44 u32 rx_desc;
45 u32 rx_buf_ptr;
46 u32 scrdp;
47 u32 tx_desc;
48 u32 sctdp;
49 u32 sftdp;
50};
51
52static struct sdma_regs sdma_regs[2];
53
54#define SDMA_REGS_INIT(s, reg_base) { \
55 (s)->sdc = (reg_base) + SDMA_SDC; \
56 (s)->sdcm = (reg_base) + SDMA_SDCM; \
57 (s)->rx_desc = (reg_base) + SDMA_RX_DESC; \
58 (s)->rx_buf_ptr = (reg_base) + SDMA_RX_BUF_PTR; \
59 (s)->scrdp = (reg_base) + SDMA_SCRDP; \
60 (s)->tx_desc = (reg_base) + SDMA_TX_DESC; \
61 (s)->sctdp = (reg_base) + SDMA_SCTDP; \
62 (s)->sftdp = (reg_base) + SDMA_SFTDP; \
63}
64
65static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET };
66
67struct mv64x60_rx_desc {
68 u16 bufsize;
69 u16 bytecnt;
70 u32 cmd_stat;
71 u32 next_desc_ptr;
72 u32 buffer;
73};
74
75struct mv64x60_tx_desc {
76 u16 bytecnt;
77 u16 shadow;
78 u32 cmd_stat;
79 u32 next_desc_ptr;
80 u32 buffer;
81};
82
83#define MAX_RESET_WAIT 10000
84#define MAX_TX_WAIT 10000
85
86#define RX_NUM_DESC 2
87#define TX_NUM_DESC 2
88
89#define RX_BUF_SIZE 32
90#define TX_BUF_SIZE 32
91
92static struct mv64x60_rx_desc rd[2][RX_NUM_DESC] __attribute__ ((aligned(32)));
93static struct mv64x60_tx_desc td[2][TX_NUM_DESC] __attribute__ ((aligned(32)));
94
95static char rx_buf[2][RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
96static char tx_buf[2][TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
97
98static int cur_rd[2] = { 0, 0 };
99static int cur_td[2] = { 0, 0 };
100
101static char chan_initialized[2] = { 0, 0 };
102
103
104#define RX_INIT_RDP(rdp) { \
105 (rdp)->bufsize = 2; \
106 (rdp)->bytecnt = 0; \
107 (rdp)->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F | \
108 SDMA_DESC_CMDSTAT_O; \
109}
110
111#ifdef CONFIG_MV64360
112static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
113 { MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
114 { MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
115 { MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
116 { MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
117};
118
119static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
120 { MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
121 { MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
122 { MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
123 { MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
124};
125
126static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
127#endif
128
129unsigned long
130serial_init(int chan, void *ignored)
131{
132 u32 mpsc_routing_base, sdma_base, brg_bcr, cdv;
133 int i;
134
135 chan = (chan == 1); /* default to chan 0 if anything but 1 */
136
137 if (chan_initialized[chan])
138 return chan;
139
140 chan_initialized[chan] = 1;
141
142 if (chan == 0) {
143 sdma_base = MV64x60_SDMA_0_OFFSET;
144 brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR;
145 SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET);
146 } else {
147 sdma_base = MV64x60_SDMA_1_OFFSET;
148 brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR;
149 SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET);
150 }
151
152 mpsc_routing_base = MV64x60_MPSC_ROUTING_OFFSET;
153
154 stop_dma(chan);
155
156 /* Set up ring buffers */
157 for (i=0; i<RX_NUM_DESC; i++) {
158 RX_INIT_RDP(&rd[chan][i]);
159 rd[chan][i].buffer = (u32)&rx_buf[chan][i * RX_BUF_SIZE];
160 rd[chan][i].next_desc_ptr = (u32)&rd[chan][i+1];
161 }
162 rd[chan][RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[chan][0];
163
164 for (i=0; i<TX_NUM_DESC; i++) {
165 td[chan][i].bytecnt = 0;
166 td[chan][i].shadow = 0;
167 td[chan][i].buffer = (u32)&tx_buf[chan][i * TX_BUF_SIZE];
168 td[chan][i].cmd_stat = SDMA_DESC_CMDSTAT_F|SDMA_DESC_CMDSTAT_L;
169 td[chan][i].next_desc_ptr = (u32)&td[chan][i+1];
170 }
171 td[chan][TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[chan][0];
172
173 /* Set MPSC Routing */
174 out_le32(mv64x60_base + mpsc_routing_base + MPSC_MRR, 0x3ffffe38);
175
176#ifdef CONFIG_GT64260
177 out_le32(mv64x60_base + GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
178#else /* Must be MV64360 or MV64460 */
179 {
180 u32 enables, prot_bits, v;
181
182 /* Set up comm unit to memory mapping windows */
183 /* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */
184
185 enables = in_le32(mv64x60_base + MV64360_CPU_BAR_ENABLE) & 0xf;
186 prot_bits = 0;
187
188 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
189 if (!(enables & (1 << i))) {
190 v = in_le32(mv64x60_base + cpu2mem_tab[i][0]);
191 v = ((v & 0xffff) << 16) | (dram_selects[i] << 8);
192 out_le32(mv64x60_base + com2mem_tab[i][0], v);
193
194 v = in_le32(mv64x60_base + cpu2mem_tab[i][1]);
195 v = (v & 0xffff) << 16;
196 out_le32(mv64x60_base + com2mem_tab[i][1], v);
197
198 prot_bits |= (0x3 << (i << 1)); /* r/w access */
199 }
200 }
201
202 out_le32(mv64x60_base + MV64360_MPSC_0_REMAP, 0);
203 out_le32(mv64x60_base + MV64360_MPSC_1_REMAP, 0);
204 out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
205 out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
206 out_le32(mv64x60_base + MV64360_MPSC2MEM_BAR_ENABLE, enables);
207 }
208#endif
209
210 /* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
211 out_le32(mv64x60_base + mpsc_routing_base + MPSC_RCRR, 0x00000100);
212 out_le32(mv64x60_base + mpsc_routing_base + MPSC_TCRR, 0x00000100);
213
214 /* clear pending interrupts */
215 out_le32(mv64x60_base + MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);
216
217 out_le32(mv64x60_base + SDMA_SCRDP + sdma_base, (int)&rd[chan][0]);
218 out_le32(mv64x60_base + SDMA_SCTDP + sdma_base,
219 (int)&td[chan][TX_NUM_DESC - 1]);
220 out_le32(mv64x60_base + SDMA_SFTDP + sdma_base,
221 (int)&td[chan][TX_NUM_DESC - 1]);
222
223 out_le32(mv64x60_base + SDMA_SDC + sdma_base,
224 SDMA_SDC_RFT | SDMA_SDC_SFM | SDMA_SDC_BLMR | SDMA_SDC_BLMT |
225 (3 << 12));
226
227 cdv = ((mv64x60_mpsc_clk_freq/(32*mv64x60_console_baud))-1);
228 out_le32(mv64x60_base + brg_bcr,
229 ((mv64x60_mpsc_clk_src << 18) | (1 << 16) | cdv));
230
231 /* Put MPSC into UART mode, no null modem, 16x clock mode */
232 out_le32(mv64x60_base + MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
233 out_le32(mv64x60_base + MPSC_MMCRH + mpsc_base[chan], 0x04400400);
234
235 out_le32(mv64x60_base + MPSC_CHR_1 + mpsc_base[chan], 0);
236 out_le32(mv64x60_base + MPSC_CHR_9 + mpsc_base[chan], 0);
237 out_le32(mv64x60_base + MPSC_CHR_10 + mpsc_base[chan], 0);
238 out_le32(mv64x60_base + MPSC_CHR_3 + mpsc_base[chan], 4);
239 out_le32(mv64x60_base + MPSC_CHR_4 + mpsc_base[chan], 0);
240 out_le32(mv64x60_base + MPSC_CHR_5 + mpsc_base[chan], 0);
241 out_le32(mv64x60_base + MPSC_CHR_6 + mpsc_base[chan], 0);
242 out_le32(mv64x60_base + MPSC_CHR_7 + mpsc_base[chan], 0);
243 out_le32(mv64x60_base + MPSC_CHR_8 + mpsc_base[chan], 0);
244
245 /* 8 data bits, 1 stop bit */
246 out_le32(mv64x60_base + MPSC_MPCR + mpsc_base[chan], (3 << 12));
247 out_le32(mv64x60_base + SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
248 out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);
249
250 udelay(100);
251
252 return chan;
253}
254
255static void
256stop_dma(int chan)
257{
258 int i;
259
260 /* Abort MPSC Rx (aborting Tx messes things up) */
261 out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);
262
263 /* Abort SDMA Rx, Tx */
264 out_le32(mv64x60_base + sdma_regs[chan].sdcm,
265 SDMA_SDCM_AR | SDMA_SDCM_STD);
266
267 for (i=0; i<MAX_RESET_WAIT; i++) {
268 if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
269 (SDMA_SDCM_AR | SDMA_SDCM_AT)) == 0)
270 break;
271
272 udelay(100);
273 }
274}
275
276static int
277wait_for_ownership(int chan)
278{
279 int i;
280
281 for (i=0; i<MAX_TX_WAIT; i++) {
282 if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
283 SDMA_SDCM_TXD) == 0)
284 break;
285
286 udelay(1000);
287 }
288
289 return (i < MAX_TX_WAIT);
290}
291
292void
293serial_putc(unsigned long com_port, unsigned char c)
294{
295 struct mv64x60_tx_desc *tdp;
296
297 if (wait_for_ownership(com_port) == 0)
298 return;
299
300 tdp = &td[com_port][cur_td[com_port]];
301 if (++cur_td[com_port] >= TX_NUM_DESC)
302 cur_td[com_port] = 0;
303
304 *(unchar *)(tdp->buffer ^ 7) = c;
305 tdp->bytecnt = 1;
306 tdp->shadow = 1;
307 tdp->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F |
308 SDMA_DESC_CMDSTAT_O;
309
310 out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp);
311 out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp);
312 out_le32(mv64x60_base + sdma_regs[com_port].sdcm,
313 in_le32(mv64x60_base + sdma_regs[com_port].sdcm) |
314 SDMA_SDCM_TXD);
315}
316
317unsigned char
318serial_getc(unsigned long com_port)
319{
320 struct mv64x60_rx_desc *rdp;
321 unchar c = '\0';
322
323 rdp = &rd[com_port][cur_rd[com_port]];
324
325 if ((rdp->cmd_stat & (SDMA_DESC_CMDSTAT_O|SDMA_DESC_CMDSTAT_ES)) == 0) {
326 c = *(unchar *)(rdp->buffer ^ 7);
327 RX_INIT_RDP(rdp);
328 if (++cur_rd[com_port] >= RX_NUM_DESC)
329 cur_rd[com_port] = 0;
330 }
331
332 return c;
333}
334
335int
336serial_tstc(unsigned long com_port)
337{
338 struct mv64x60_rx_desc *rdp;
339 int loop_count = 0;
340 int rc = 0;
341
342 rdp = &rd[com_port][cur_rd[com_port]];
343
344 /* Go thru rcv desc's until empty looking for one with data (no error)*/
345 while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
346 (loop_count++ < RX_NUM_DESC)) {
347
348 /* If there was an error, reinit the desc & continue */
349 if ((rdp->cmd_stat & SDMA_DESC_CMDSTAT_ES) != 0) {
350 RX_INIT_RDP(rdp);
351 if (++cur_rd[com_port] >= RX_NUM_DESC)
352 cur_rd[com_port] = 0;
353 rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr;
354 } else {
355 rc = 1;
356 break;
357 }
358 }
359
360 return rc;
361}
362
363void
364serial_close(unsigned long com_port)
365{
366 stop_dma(com_port);
367}