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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004 by Ralf Baechle
7 */
8#ifndef _ASM_WAR_H
9#define _ASM_WAR_H
10
11#include <linux/config.h>
12
13/*
14 * Another R4600 erratum. Due to the lack of errata information the exact
15 * technical details aren't known. I've experimentally found that disabling
16 * interrupts during indexed I-cache flushes seems to be sufficient to deal
17 * with the issue.
18 *
19 * #define R4600_V1_INDEX_ICACHEOP_WAR 1
20 */
21
22/*
23 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
24 *
25 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
26 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
27 * executed if there is no other dcache activity. If the dcache is
28 * accessed for another instruction immeidately preceding when these
29 * cache instructions are executing, it is possible that the dcache
30 * tag match outputs used by these cache instructions will be
31 * incorrect. These cache instructions should be preceded by at least
32 * four instructions that are not any kind of load or store
33 * instruction.
34 *
35 * This is not allowed: lw
36 * nop
37 * nop
38 * nop
39 * cache Hit_Writeback_Invalidate_D
40 *
41 * This is allowed: lw
42 * nop
43 * nop
44 * nop
45 * nop
46 * cache Hit_Writeback_Invalidate_D
47 *
48 * #define R4600_V1_HIT_CACHEOP_WAR 1
49 */
50
51
52/*
53 * Writeback and invalidate the primary cache dcache before DMA.
54 *
55 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
56 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
57 * operate correctly if the internal data cache refill buffer is empty. These
58 * CACHE instructions should be separated from any potential data cache miss
59 * by a load instruction to an uncached address to empty the response buffer."
60 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
61 * in .pdf format.)
62 *
63 * #define R4600_V2_HIT_CACHEOP_WAR 1
64 */
65
66/*
67 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
68 */
69#ifdef CONFIG_SGI_IP22
70
71#define R4600_V1_INDEX_ICACHEOP_WAR 1
72#define R4600_V1_HIT_CACHEOP_WAR 1
73#define R4600_V2_HIT_CACHEOP_WAR 1
74
75#endif
76
77/*
78 * But the RM200C seems to have been shipped only with V2.0 R4600s
79 */
80#ifdef CONFIG_SNI_RM200_PCI
81
82#define R4600_V2_HIT_CACHEOP_WAR 1
83
84#endif
85
86#ifdef CONFIG_CPU_R5432
87
88/*
89 * When an interrupt happens on a CP0 register read instruction, CPU may
90 * lock up or read corrupted values of CP0 registers after it enters
91 * the exception handler.
92 *
93 * This workaround makes sure that we read a "safe" CP0 register as the
94 * first thing in the exception handler, which breaks one of the
95 * pre-conditions for this problem.
96 */
97#define R5432_CP0_INTERRUPT_WAR 1
98
99#endif
100
101#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
102 defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
103
104/*
105 * Workaround for the Sibyte M3 errata the text of which can be found at
106 *
107 * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
108 *
109 * This will enable the use of a special TLB refill handler which does a
110 * consistency check on the information in c0_badvaddr and c0_entryhi and
111 * will just return and take the exception again if the information was
112 * found to be inconsistent.
113 */
114#define BCM1250_M3_WAR 1
115
116/*
117 * This is a DUART workaround related to glitches around register accesses
118 */
119#define SIBYTE_1956_WAR 1
120
121#endif
122
123/*
124 * Fill buffers not flushed on CACHE instructions
125 *
126 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
127 * for that line can get stale data from the fill buffer instead of
128 * accessing memory if the previous icache miss was also to that line.
129 *
130 * Workaround: generate an icache refill from a different line
131 *
132 * Affects:
133 * MIPS 4K RTL revision <3.0, PRID revision <4
134 */
135#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
136 defined(CONFIG_MIPS_SEAD)
137#define MIPS4K_ICACHE_REFILL_WAR 1
138#endif
139
140/*
141 * Missing implicit forced flush of evictions caused by CACHE
142 * instruction
143 *
144 * Evictions caused by a CACHE instructions are not forced on to the
145 * bus. The BIU gives higher priority to fetches than to the data from
146 * the eviction buffer and no collision detection is performed between
147 * fetches and pending data from the eviction buffer.
148 *
149 * Workaround: Execute a SYNC instruction after the cache instruction
150 *
151 * Affects:
152 * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
153 * MIPS 20Kc RTL revision <4.0, PRID revision <?
154 */
155#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
156 defined(CONFIG_MIPS_SEAD)
157#define MIPS_CACHE_SYNC_WAR 1
158#endif
159
160/*
161 * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
162 * the line which this instruction itself exists, the following
163 * operation is not guaranteed."
164 *
165 * Workaround: do two phase flushing for Index_Invalidate_I
166 */
167#ifdef CONFIG_CPU_TX49XX
168#define TX49XX_ICACHE_INDEX_INV_WAR 1
169#endif
170
171/*
172 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
173 * cache operation unusable on SMP systems.
174 */
175#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
176#define RM9000_CDEX_SMP_WAR 1
177#endif
178
179/*
180 * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
181 * where invalid instructions in the same I-cache line worth of instructions
182 * being fetched may case spurious exceptions.
183 */
184#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
185 defined(CONFIG_PMC_YOSEMITE)
186#define ICACHE_REFILLS_WORKAROUND_WAR 1
187#endif
188
189
190/*
191 * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
192 * may cause ll / sc and lld / scd sequences to execute non-atomically.
193 */
194#ifdef CONFIG_SGI_IP27
195#define R10000_LLSC_WAR 1
196#endif
197
198/*
199 * Workarounds default to off
200 */
201#ifndef ICACHE_REFILLS_WORKAROUND_WAR
202#define ICACHE_REFILLS_WORKAROUND_WAR 0
203#endif
204#ifndef R4600_V1_INDEX_ICACHEOP_WAR
205#define R4600_V1_INDEX_ICACHEOP_WAR 0
206#endif
207#ifndef R4600_V1_HIT_CACHEOP_WAR
208#define R4600_V1_HIT_CACHEOP_WAR 0
209#endif
210#ifndef R4600_V2_HIT_CACHEOP_WAR
211#define R4600_V2_HIT_CACHEOP_WAR 0
212#endif
213#ifndef R5432_CP0_INTERRUPT_WAR
214#define R5432_CP0_INTERRUPT_WAR 0
215#endif
216#ifndef BCM1250_M3_WAR
217#define BCM1250_M3_WAR 0
218#endif
219#ifndef SIBYTE_1956_WAR
220#define SIBYTE_1956_WAR 0
221#endif
222#ifndef MIPS4K_ICACHE_REFILL_WAR
223#define MIPS4K_ICACHE_REFILL_WAR 0
224#endif
225#ifndef MIPS_CACHE_SYNC_WAR
226#define MIPS_CACHE_SYNC_WAR 0
227#endif
228#ifndef TX49XX_ICACHE_INDEX_INV_WAR
229#define TX49XX_ICACHE_INDEX_INV_WAR 0
230#endif
231#ifndef RM9000_CDEX_SMP_WAR
232#define RM9000_CDEX_SMP_WAR 0
233#endif
234#ifndef R10000_LLSC_WAR
235#define R10000_LLSC_WAR 0
236#endif
237
238#endif /* _ASM_WAR_H */