Linux kernel mirror (for testing)
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linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12#include <linux/config.h>
13
14/*
15 * This assumes you have a 1.8432 MHz clock for your UART.
16 *
17 * It'd be nice if someone built a serial card with a 24.576 MHz
18 * clock, since the 16550A is capable of handling a top speed of 1.5
19 * megabits/second; but this requires the faster clock.
20 */
21#define BASE_BAUD (1843200 / 16)
22
23/* Standard COM flags (except for COM4, because of the 8514 problem) */
24#ifdef CONFIG_SERIAL_DETECT_IRQ
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
26#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
27#else
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif
31
32#ifdef CONFIG_MACH_JAZZ
33#include <asm/jazz.h>
34
35#ifndef CONFIG_OLIVETTI_M700
36 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
37 exactly which ones ... XXX */
38#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
39#else
40/* but the M700 isn't such a strange beast */
41#define JAZZ_BASE_BAUD BASE_BAUD
42#endif
43
44#define _JAZZ_SERIAL_INIT(int, base) \
45 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
46 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
47 .io_type = SERIAL_IO_MEM }
48#define JAZZ_SERIAL_PORT_DEFNS \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
50 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
51#else
52#define JAZZ_SERIAL_PORT_DEFNS
53#endif
54
55/*
56 * Both Galileo boards have the same UART mappings.
57 */
58#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
59#include <asm/galileo-boards/ev96100.h>
60#include <asm/galileo-boards/ev96100int.h>
61#define EV96100_SERIAL_PORT_DEFNS \
62 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
63 .flags = STD_COM_FLAGS, \
64 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
65 .io_type = SERIAL_IO_MEM }, \
66 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
67 .flags = STD_COM_FLAGS, \
68 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
69 .io_type = SERIAL_IO_MEM },
70#else
71#define EV96100_SERIAL_PORT_DEFNS
72#endif
73
74#ifdef CONFIG_MIPS_ITE8172
75#include <asm/it8172/it8172.h>
76#include <asm/it8172/it8172_int.h>
77#include <asm/it8712.h>
78#define ITE_SERIAL_PORT_DEFNS \
79 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
80 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
81 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
82 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
83 /* Smart Card Reader 0 */ \
84 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
85 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
86 /* Smart Card Reader 1 */ \
87 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
88 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
89#else
90#define ITE_SERIAL_PORT_DEFNS
91#endif
92
93#ifdef CONFIG_MIPS_IVR
94#include <asm/it8172/it8172.h>
95#include <asm/it8172/it8172_int.h>
96#define IVR_SERIAL_PORT_DEFNS \
97 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
98 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
99 /* Smart Card Reader 1 */ \
100 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
101 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
102#else
103#define IVR_SERIAL_PORT_DEFNS
104#endif
105
106#ifdef CONFIG_SERIAL_AU1X00
107#include <asm/mach-au1x00/au1000.h>
108#ifdef CONFIG_SOC_AU1000
109#define AU1000_SERIAL_PORT_DEFNS \
110 { .baud_base = 0, .port = UART0_ADDR, \
111 .iomem_base = (unsigned char *)UART0_ADDR, \
112 .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
113 .iomem_reg_shift = 2 }, \
114 { .baud_base = 0, .port = UART1_ADDR, \
115 .iomem_base = (unsigned char *)UART1_ADDR, \
116 .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
117 .iomem_reg_shift = 2 }, \
118 { .baud_base = 0, .port = UART2_ADDR, \
119 .iomem_base = (unsigned char *)UART2_ADDR, \
120 .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
121 .iomem_reg_shift = 2 }, \
122 { .baud_base = 0, .port = UART3_ADDR, \
123 .iomem_base = (unsigned char *)UART3_ADDR, \
124 .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
125 .iomem_reg_shift = 2 },
126#endif
127
128#ifdef CONFIG_SOC_AU1500
129#define AU1000_SERIAL_PORT_DEFNS \
130 { .baud_base = 0, .port = UART0_ADDR, \
131 .iomem_base = (unsigned char *)UART0_ADDR, \
132 .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
133 .iomem_reg_shift = 2 }, \
134 { .baud_base = 0, .port = UART3_ADDR, \
135 .iomem_base = (unsigned char *)UART3_ADDR, \
136 .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
137 .iomem_reg_shift = 2 },
138#endif
139
140#ifdef CONFIG_SOC_AU1100
141#define AU1000_SERIAL_PORT_DEFNS \
142 { .baud_base = 0, .port = UART0_ADDR, \
143 .iomem_base = (unsigned char *)UART0_ADDR, \
144 .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
145 .iomem_reg_shift = 2 }, \
146 { .baud_base = 0, .port = UART1_ADDR, \
147 .iomem_base = (unsigned char *)UART1_ADDR, \
148 .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
149 .iomem_reg_shift = 2 }, \
150 { .baud_base = 0, .port = UART3_ADDR, \
151 .iomem_base = (unsigned char *)UART3_ADDR, \
152 .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
153 .iomem_reg_shift = 2 },
154#endif
155
156#ifdef CONFIG_SOC_AU1550
157#define AU1000_SERIAL_PORT_DEFNS \
158 { .baud_base = 0, .port = UART0_ADDR, \
159 .iomem_base = (unsigned char *)UART0_ADDR, \
160 .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
161 .iomem_reg_shift = 2 }, \
162 { .baud_base = 0, .port = UART1_ADDR, \
163 .iomem_base = (unsigned char *)UART1_ADDR, \
164 .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
165 .iomem_reg_shift = 2 }, \
166 { .baud_base = 0, .port = UART3_ADDR, \
167 .iomem_base = (unsigned char *)UART3_ADDR, \
168 .irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
169 .iomem_reg_shift = 2 },
170#endif
171
172#ifdef CONFIG_SOC_AU1200
173#define AU1000_SERIAL_PORT_DEFNS \
174 { .baud_base = 0, .port = UART0_ADDR, \
175 .iomem_base = (unsigned char *)UART0_ADDR, \
176 .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
177 .iomem_reg_shift = 2 }, \
178 { .baud_base = 0, .port = UART1_ADDR, \
179 .iomem_base = (unsigned char *)UART1_ADDR, \
180 .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
181 .iomem_reg_shift = 2 },
182#endif
183
184#else
185#define AU1000_SERIAL_PORT_DEFNS
186#endif
187
188#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
189#define STD_SERIAL_PORT_DEFNS \
190 /* UART CLK PORT IRQ FLAGS */ \
191 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
192 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
193 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
194 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
195
196#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
197#define STD_SERIAL_PORT_DEFNS
198#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
199
200#ifdef CONFIG_MOMENCO_JAGUAR_ATX
201/* Ordinary NS16552 duart with a 20MHz crystal. */
202#define JAGUAR_ATX_UART_CLK 20000000
203#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
204
205#define JAGUAR_ATX_SERIAL1_IRQ 6
206#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
207
208#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
209 { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
210 .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
211 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
212 io_type: SERIAL_IO_MEM }
213#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
214 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
215#else
216#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
217#endif
218
219#ifdef CONFIG_MOMENCO_OCELOT_3
220#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
221#define OCELOT_3_SERIAL_IRQ 6
222#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
223
224#define _OCELOT_3_SERIAL_INIT(int, base) \
225 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
226 .flags = STD_COM_FLAGS, \
227 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
228 io_type: SERIAL_IO_MEM }
229
230#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
231 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
232#else
233#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
234#endif
235
236#ifdef CONFIG_MOMENCO_OCELOT
237/* Ordinary NS16552 duart with a 20MHz crystal. */
238#define OCELOT_BASE_BAUD ( 20000000 / 16 )
239
240#define OCELOT_SERIAL1_IRQ 4
241#define OCELOT_SERIAL1_BASE 0xe0001020
242
243#define _OCELOT_SERIAL_INIT(int, base) \
244 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
245 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
246 .io_type = SERIAL_IO_MEM }
247#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
248 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
249#else
250#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
251#endif
252
253#ifdef CONFIG_MOMENCO_OCELOT_G
254/* Ordinary NS16552 duart with a 20MHz crystal. */
255#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
256
257#define OCELOT_G_SERIAL1_IRQ 4
258#if 0
259#define OCELOT_G_SERIAL1_BASE 0xe0001020
260#else
261#define OCELOT_G_SERIAL1_BASE 0xfd000020
262#endif
263
264#define _OCELOT_G_SERIAL_INIT(int, base) \
265 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
266 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
267 .io_type = SERIAL_IO_MEM }
268#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
269 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
270#else
271#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
272#endif
273
274#ifdef CONFIG_MOMENCO_OCELOT_C
275/* Ordinary NS16552 duart with a 20MHz crystal. */
276#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
277
278#define OCELOT_C_SERIAL1_IRQ 80
279#define OCELOT_C_SERIAL1_BASE 0xfd000020
280
281#define OCELOT_C_SERIAL2_IRQ 81
282#define OCELOT_C_SERIAL2_BASE 0xfd000000
283
284#define _OCELOT_C_SERIAL_INIT(int, base) \
285 { .baud_base = OCELOT_C_BASE_BAUD, \
286 .irq = (int), \
287 .flags = STD_COM_FLAGS, \
288 .iomem_base = (u8 *) base, \
289 .iomem_reg_shift = 2, \
290 .io_type = SERIAL_IO_MEM \
291 }
292#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
293 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
294 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
295#else
296#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
297#endif
298
299#ifdef CONFIG_DDB5477
300#include <asm/ddb5xxx/ddb5477.h>
301#define DDB5477_SERIAL_PORT_DEFNS \
302 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
303 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
304 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
305 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
306 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
307 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
308#else
309#define DDB5477_SERIAL_PORT_DEFNS
310#endif
311
312#ifdef CONFIG_SGI_IP32
313/*
314 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
315 * They are initialized in ip32_setup
316 */
317#define IP32_SERIAL_PORT_DEFNS \
318 {},{},
319#else
320#define IP32_SERIAL_PORT_DEFNS
321#endif /* CONFIG_SGI_IP32 */
322
323#define SERIAL_PORT_DFNS \
324 DDB5477_SERIAL_PORT_DEFNS \
325 EV96100_SERIAL_PORT_DEFNS \
326 IP32_SERIAL_PORT_DEFNS \
327 ITE_SERIAL_PORT_DEFNS \
328 IVR_SERIAL_PORT_DEFNS \
329 JAZZ_SERIAL_PORT_DEFNS \
330 STD_SERIAL_PORT_DEFNS \
331 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
332 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
333 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
334 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
335 AU1000_SERIAL_PORT_DEFNS
336
337#endif /* _ASM_SERIAL_H */