tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_8xx
22#include <asm/reg_8xx.h>
23#endif /* CONFIG_8xx */
24
25#define MSR_SF_LG 63 /* Enable 64 bit mode */
26#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
27#define MSR_HV_LG 60 /* Hypervisor state */
28#define MSR_VEC_LG 25 /* Enable AltiVec */
29#define MSR_POW_LG 18 /* Enable Power Management */
30#define MSR_WE_LG 18 /* Wait State Enable */
31#define MSR_TGPR_LG 17 /* TLB Update registers in use */
32#define MSR_CE_LG 17 /* Critical Interrupt Enable */
33#define MSR_ILE_LG 16 /* Interrupt Little Endian */
34#define MSR_EE_LG 15 /* External Interrupt Enable */
35#define MSR_PR_LG 14 /* Problem State / Privilege Level */
36#define MSR_FP_LG 13 /* Floating Point enable */
37#define MSR_ME_LG 12 /* Machine Check Enable */
38#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
39#define MSR_SE_LG 10 /* Single Step */
40#define MSR_BE_LG 9 /* Branch Trace */
41#define MSR_DE_LG 9 /* Debug Exception Enable */
42#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
43#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
44#define MSR_IR_LG 5 /* Instruction Relocate */
45#define MSR_DR_LG 4 /* Data Relocate */
46#define MSR_PE_LG 3 /* Protection Enable */
47#define MSR_PX_LG 2 /* Protection Exclusive Mode */
48#define MSR_PMM_LG 2 /* Performance monitor */
49#define MSR_RI_LG 1 /* Recoverable Exception */
50#define MSR_LE_LG 0 /* Little Endian */
51
52#ifdef __ASSEMBLY__
53#define __MASK(X) (1<<(X))
54#else
55#define __MASK(X) (1UL<<(X))
56#endif
57
58#ifdef CONFIG_PPC64
59#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
60#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
61#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
62#else
63/* so tests for these bits fail on 32-bit */
64#define MSR_SF 0
65#define MSR_ISF 0
66#define MSR_HV 0
67#endif
68
69#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
70#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
71#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
72#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
73#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
74#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
75#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
76#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
77#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
78#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
79#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
80#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
81#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
82#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
83#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
84#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
85#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
86#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
87#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
88#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
89#ifndef MSR_PMM
90#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
91#endif
92#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
93#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
94
95#ifdef CONFIG_PPC64
96#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
97#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV
98
99#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
100#define MSR_USER64 MSR_USER32 | MSR_SF
101
102#else /* 32-bit */
103/* Default MSR for kernel mode. */
104#ifndef MSR_KERNEL /* reg_booke.h also defines this */
105#ifdef CONFIG_APUS_FAST_EXCEPT
106#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
107#else
108#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
109#endif
110#endif
111
112#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
113#endif
114
115/* Floating Point Status and Control Register (FPSCR) Fields */
116#define FPSCR_FX 0x80000000 /* FPU exception summary */
117#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
118#define FPSCR_VX 0x20000000 /* Invalid operation summary */
119#define FPSCR_OX 0x10000000 /* Overflow exception summary */
120#define FPSCR_UX 0x08000000 /* Underflow exception summary */
121#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
122#define FPSCR_XX 0x02000000 /* Inexact exception summary */
123#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
124#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
125#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
126#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
127#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
128#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
129#define FPSCR_FR 0x00040000 /* Fraction rounded */
130#define FPSCR_FI 0x00020000 /* Fraction inexact */
131#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
132#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
133#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
134#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
135#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
136#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
137#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
138#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
139#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
140#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
141#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
142#define FPSCR_RN 0x00000003 /* FPU rounding control */
143
144/* Special Purpose Registers (SPRNs)*/
145#define SPRN_CTR 0x009 /* Count Register */
146#define SPRN_CTRLF 0x088
147#define SPRN_CTRLT 0x098
148#define CTRL_RUNLATCH 0x1
149#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
150#define DABR_TRANSLATION (1UL << 2)
151#define SPRN_DAR 0x013 /* Data Address Register */
152#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
153#define DSISR_NOHPTE 0x40000000 /* no translation found */
154#define DSISR_PROTFAULT 0x08000000 /* protection fault */
155#define DSISR_ISSTORE 0x02000000 /* access was a store */
156#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
157#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
158#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
159#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
160#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
161#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
162#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
163#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
164#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
165#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
166#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
167#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
168#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
169#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
170#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
171#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
172#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
173#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
174#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
175#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
176#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
177#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
178#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
179
180#define SPRN_DEC 0x016 /* Decrement Register */
181#define SPRN_DER 0x095 /* Debug Enable Regsiter */
182#define DER_RSTE 0x40000000 /* Reset Interrupt */
183#define DER_CHSTPE 0x20000000 /* Check Stop */
184#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
185#define DER_EXTIE 0x02000000 /* External Interrupt */
186#define DER_ALIE 0x01000000 /* Alignment Interrupt */
187#define DER_PRIE 0x00800000 /* Program Interrupt */
188#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
189#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
190#define DER_SYSIE 0x00040000 /* System Call Interrupt */
191#define DER_TRE 0x00020000 /* Trace Interrupt */
192#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
193#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
194#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
195#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
196#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
197#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
198#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
199#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
200#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
201#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
202#define SPRN_EAR 0x11A /* External Address Register */
203#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
204#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
205#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
206#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
207#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
208#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
209#define HID0_SBCLK (1<<27)
210#define HID0_EICE (1<<26)
211#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
212#define HID0_ECLK (1<<25)
213#define HID0_PAR (1<<24)
214#define HID0_STEN (1<<24) /* Software table search enable - 745x */
215#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
216#define HID0_DOZE (1<<23)
217#define HID0_NAP (1<<22)
218#define HID0_SLEEP (1<<21)
219#define HID0_DPM (1<<20)
220#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
221#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
222#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
223#define HID0_ICE (1<<15) /* Instruction Cache Enable */
224#define HID0_DCE (1<<14) /* Data Cache Enable */
225#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
226#define HID0_DLOCK (1<<12) /* Data Cache Lock */
227#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
228#define HID0_DCI (1<<10) /* Data Cache Invalidate */
229#define HID0_SPD (1<<9) /* Speculative disable */
230#define HID0_DAPUEN (1<<8) /* Debug APU enable */
231#define HID0_SGE (1<<7) /* Store Gathering Enable */
232#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
233#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
234#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
235#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
236#define HID0_ABE (1<<3) /* Address Broadcast Enable */
237#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
238#define HID0_BHTE (1<<2) /* Branch History Table Enable */
239#define HID0_BTCD (1<<1) /* Branch target cache disable */
240#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
241#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
242
243#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
244#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
245#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
246#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
247#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
248#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
249#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
250#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
251#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
252#define HID1_PS (1<<16) /* 750FX PLL selection */
253#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
254#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
255#define SPRN_HID4 0x3F4 /* 970 HID4 */
256#define SPRN_HID5 0x3F6 /* 970 HID5 */
257#define SPRN_HID6 0x3F9 /* BE HID 6 */
258#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
259#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
260#define SPRN_TSCR 0x399 /* Thread switch control on BE */
261#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
262#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
263#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
264#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
265#define SPRN_TSC 0x3FD /* Thread switch control on others */
266#define SPRN_TST 0x3FC /* Thread switch timeout on others */
267#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
268#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
269#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
270#endif
271#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
272#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
273#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
274#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
275#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
276#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
277#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
278#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
279#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
280#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
281#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
282#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
283#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
284#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
285#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
286#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
287#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
288#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
289#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
290#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
291#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
292#define ICTRL_EICP 0x00000100 /* enable icache par. check */
293#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
294#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
295#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
296#define SPRN_L2CR2 0x3f8
297#define L2CR_L2E 0x80000000 /* L2 enable */
298#define L2CR_L2PE 0x40000000 /* L2 parity enable */
299#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
300#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
301#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
302#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
303#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
304#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
305#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
306#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
307#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
308#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
309#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
310#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
311#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
312#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
313#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
314#define L2CR_L2DO 0x00400000 /* L2 data only */
315#define L2CR_L2I 0x00200000 /* L2 global invalidate */
316#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
317#define L2CR_L2WT 0x00080000 /* L2 write-through */
318#define L2CR_L2TS 0x00040000 /* L2 test support */
319#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
320#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
321#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
322#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
323#define L2CR_L2DF 0x00004000 /* L2 differential clock */
324#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
325#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
326#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
327#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
328#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
329#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
330#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
331#define L3CR_L3E 0x80000000 /* L3 enable */
332#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
333#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
334#define L3CR_L3SIZ 0x10000000 /* L3 size */
335#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
336#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
337#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
338#define L3CR_L3IO 0x00400000 /* L3 instruction only */
339#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
340#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
341#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
342#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
343#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
344#define L3CR_L3I 0x00000400 /* L3 global invalidate */
345#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
346#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
347#define L3CR_L3DO 0x00000040 /* L3 data only mode */
348#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
349#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
350
351#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
352#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
353#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
354#define SPRN_LDSTDB 0x3f4 /* */
355#define SPRN_LR 0x008 /* Link Register */
356#ifndef SPRN_PIR
357#define SPRN_PIR 0x3FF /* Processor Identification Register */
358#endif
359#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
360#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
361#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
362#define SPRN_PVR 0x11F /* Processor Version Register */
363#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
364#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
365#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
366#define SPRN_ASR 0x118 /* Address Space Register */
367#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
368#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
369#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
370#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
371#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
372#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
373#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
374#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
375#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
376#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
377#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
378#ifndef SPRN_SVR
379#define SPRN_SVR 0x11E /* System Version Register */
380#endif
381#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
382/* these bits were defined in inverted endian sense originally, ugh, confusing */
383#define THRM1_TIN (1 << 31)
384#define THRM1_TIV (1 << 30)
385#define THRM1_THRES(x) ((x&0x7f)<<23)
386#define THRM3_SITV(x) ((x&0x3fff)<<1)
387#define THRM1_TID (1<<2)
388#define THRM1_TIE (1<<1)
389#define THRM1_V (1<<0)
390#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
391#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
392#define THRM3_E (1<<0)
393#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
394#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
395#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
396#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
397#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
398#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
399#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
400#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
401#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
402#define SPRN_XER 0x001 /* Fixed Point Exception Register */
403
404#define SPRN_SCOMC 0x114 /* SCOM Access Control */
405#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
406
407/* Performance monitor SPRs */
408#ifdef CONFIG_PPC64
409#define SPRN_MMCR0 795
410#define MMCR0_FC 0x80000000UL /* freeze counters */
411#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
412#define MMCR0_KERNEL_DISABLE MMCR0_FCS
413#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
414#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
415#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
416#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
417#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
418#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
419#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
420#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
421#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
422#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
423#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
424#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
425#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
426#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
427#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
428#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
429#define SPRN_MMCR1 798
430#define SPRN_MMCRA 0x312
431#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
432#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
433#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
434#define SPRN_PMC1 787
435#define SPRN_PMC2 788
436#define SPRN_PMC3 789
437#define SPRN_PMC4 790
438#define SPRN_PMC5 791
439#define SPRN_PMC6 792
440#define SPRN_PMC7 793
441#define SPRN_PMC8 794
442#define SPRN_SIAR 780
443#define SPRN_SDAR 781
444
445#else /* 32-bit */
446#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
447#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
448#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
449#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
450#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
451#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
452
453/* Bit definitions for MMCR0 and PMC1 / PMC2. */
454#define MMCR0_PMC1_CYCLES (1 << 7)
455#define MMCR0_PMC1_ICACHEMISS (5 << 7)
456#define MMCR0_PMC1_DTLB (6 << 7)
457#define MMCR0_PMC2_DCACHEMISS 0x6
458#define MMCR0_PMC2_CYCLES 0x1
459#define MMCR0_PMC2_ITLB 0x7
460#define MMCR0_PMC2_LOADMISSTIME 0x5
461#define MMCR0_PMXE (1 << 26)
462#endif
463
464/* Processor Version Register (PVR) field extraction */
465
466#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
467#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
468
469#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
470
471/*
472 * IBM has further subdivided the standard PowerPC 16-bit version and
473 * revision subfields of the PVR for the PowerPC 403s into the following:
474 */
475
476#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
477#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
478#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
479#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
480#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
481#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
482
483/* Processor Version Numbers */
484
485#define PVR_403GA 0x00200000
486#define PVR_403GB 0x00200100
487#define PVR_403GC 0x00200200
488#define PVR_403GCX 0x00201400
489#define PVR_405GP 0x40110000
490#define PVR_STB03XXX 0x40310000
491#define PVR_NP405H 0x41410000
492#define PVR_NP405L 0x41610000
493#define PVR_601 0x00010000
494#define PVR_602 0x00050000
495#define PVR_603 0x00030000
496#define PVR_603e 0x00060000
497#define PVR_603ev 0x00070000
498#define PVR_603r 0x00071000
499#define PVR_604 0x00040000
500#define PVR_604e 0x00090000
501#define PVR_604r 0x000A0000
502#define PVR_620 0x00140000
503#define PVR_740 0x00080000
504#define PVR_750 PVR_740
505#define PVR_740P 0x10080000
506#define PVR_750P PVR_740P
507#define PVR_7400 0x000C0000
508#define PVR_7410 0x800C0000
509#define PVR_7450 0x80000000
510#define PVR_8540 0x80200000
511#define PVR_8560 0x80200000
512/*
513 * For the 8xx processors, all of them report the same PVR family for
514 * the PowerPC core. The various versions of these processors must be
515 * differentiated by the version number in the Communication Processor
516 * Module (CPM).
517 */
518#define PVR_821 0x00500000
519#define PVR_823 PVR_821
520#define PVR_850 PVR_821
521#define PVR_860 PVR_821
522#define PVR_8240 0x00810100
523#define PVR_8245 0x80811014
524#define PVR_8260 PVR_8240
525
526/* 64-bit processors */
527/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
528#define PV_NORTHSTAR 0x0033
529#define PV_PULSAR 0x0034
530#define PV_POWER4 0x0035
531#define PV_ICESTAR 0x0036
532#define PV_SSTAR 0x0037
533#define PV_POWER4p 0x0038
534#define PV_970 0x0039
535#define PV_POWER5 0x003A
536#define PV_POWER5p 0x003B
537#define PV_970FX 0x003C
538#define PV_630 0x0040
539#define PV_630p 0x0041
540#define PV_970MP 0x0044
541#define PV_BE 0x0070
542
543/*
544 * Number of entries in the SLB. If this ever changes we should handle
545 * it with a use a cpu feature fixup.
546 */
547#define SLB_NUM_ENTRIES 64
548
549/* Macros for setting and retrieving special purpose registers */
550#ifndef __ASSEMBLY__
551#define mfmsr() ({unsigned long rval; \
552 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
553#ifdef CONFIG_PPC64
554#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
555 : : "r" (v))
556#define mtmsrd(v) __mtmsrd((v), 0)
557#define mtmsr(v) mtmsrd(v)
558#else
559#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
560#endif
561
562#define mfspr(rn) ({unsigned long rval; \
563 asm volatile("mfspr %0," __stringify(rn) \
564 : "=r" (rval)); rval;})
565#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
566
567#define mftb() ({unsigned long rval; \
568 asm volatile("mftb %0" : "=r" (rval)); rval;})
569#define mftbl() ({unsigned long rval; \
570 asm volatile("mftbl %0" : "=r" (rval)); rval;})
571
572#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
573#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
574
575#ifdef CONFIG_PPC32
576#define mfsrin(v) ({unsigned int rval; \
577 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
578 rval;})
579#endif
580
581#define proc_trap() asm volatile("trap")
582
583#ifdef CONFIG_PPC64
584static inline void ppc64_runlatch_on(void)
585{
586 unsigned long ctrl;
587
588 if (cpu_has_feature(CPU_FTR_CTRL)) {
589 ctrl = mfspr(SPRN_CTRLF);
590 ctrl |= CTRL_RUNLATCH;
591 mtspr(SPRN_CTRLT, ctrl);
592 }
593}
594
595static inline void ppc64_runlatch_off(void)
596{
597 unsigned long ctrl;
598
599 if (cpu_has_feature(CPU_FTR_CTRL)) {
600 ctrl = mfspr(SPRN_CTRLF);
601 ctrl &= ~CTRL_RUNLATCH;
602 mtspr(SPRN_CTRLT, ctrl);
603 }
604}
605
606extern unsigned long scom970_read(unsigned int address);
607extern void scom970_write(unsigned int address, unsigned long value);
608
609#endif /* CONFIG_PPC64 */
610
611#define __get_SP() ({unsigned long sp; \
612 asm volatile("mr %0,1": "=r" (sp)); sp;})
613
614#else /* __ASSEMBLY__ */
615
616#define RUNLATCH_ON(REG) \
617BEGIN_FTR_SECTION \
618 mfspr (REG),SPRN_CTRLF; \
619 ori (REG),(REG),CTRL_RUNLATCH; \
620 mtspr SPRN_CTRLT,(REG); \
621END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
622
623#endif /* __ASSEMBLY__ */
624#endif /* __KERNEL__ */
625#endif /* _ASM_POWERPC_REG_H */