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linux
1/*
2 * include/asm-s390/system.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 *
8 * Derived from "include/asm-i386/system.h"
9 */
10
11#ifndef __ASM_SYSTEM_H
12#define __ASM_SYSTEM_H
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <asm/types.h>
17#include <asm/ptrace.h>
18#include <asm/setup.h>
19#include <asm/processor.h>
20
21#ifdef __KERNEL__
22
23struct task_struct;
24
25extern struct task_struct *__switch_to(void *, void *);
26
27#ifdef __s390x__
28#define __FLAG_SHIFT 56
29#else /* ! __s390x__ */
30#define __FLAG_SHIFT 24
31#endif /* ! __s390x__ */
32
33static inline void save_fp_regs(s390_fp_regs *fpregs)
34{
35 asm volatile (
36 " std 0,8(%1)\n"
37 " std 2,24(%1)\n"
38 " std 4,40(%1)\n"
39 " std 6,56(%1)"
40 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
41 if (!MACHINE_HAS_IEEE)
42 return;
43 asm volatile(
44 " stfpc 0(%1)\n"
45 " std 1,16(%1)\n"
46 " std 3,32(%1)\n"
47 " std 5,48(%1)\n"
48 " std 7,64(%1)\n"
49 " std 8,72(%1)\n"
50 " std 9,80(%1)\n"
51 " std 10,88(%1)\n"
52 " std 11,96(%1)\n"
53 " std 12,104(%1)\n"
54 " std 13,112(%1)\n"
55 " std 14,120(%1)\n"
56 " std 15,128(%1)\n"
57 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
58}
59
60static inline void restore_fp_regs(s390_fp_regs *fpregs)
61{
62 asm volatile (
63 " ld 0,8(%0)\n"
64 " ld 2,24(%0)\n"
65 " ld 4,40(%0)\n"
66 " ld 6,56(%0)"
67 : : "a" (fpregs), "m" (*fpregs) );
68 if (!MACHINE_HAS_IEEE)
69 return;
70 asm volatile(
71 " lfpc 0(%0)\n"
72 " ld 1,16(%0)\n"
73 " ld 3,32(%0)\n"
74 " ld 5,48(%0)\n"
75 " ld 7,64(%0)\n"
76 " ld 8,72(%0)\n"
77 " ld 9,80(%0)\n"
78 " ld 10,88(%0)\n"
79 " ld 11,96(%0)\n"
80 " ld 12,104(%0)\n"
81 " ld 13,112(%0)\n"
82 " ld 14,120(%0)\n"
83 " ld 15,128(%0)\n"
84 : : "a" (fpregs), "m" (*fpregs) );
85}
86
87static inline void save_access_regs(unsigned int *acrs)
88{
89 asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
90}
91
92static inline void restore_access_regs(unsigned int *acrs)
93{
94 asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
95}
96
97#define switch_to(prev,next,last) do { \
98 if (prev == next) \
99 break; \
100 save_fp_regs(&prev->thread.fp_regs); \
101 restore_fp_regs(&next->thread.fp_regs); \
102 save_access_regs(&prev->thread.acrs[0]); \
103 restore_access_regs(&next->thread.acrs[0]); \
104 prev = __switch_to(prev,next); \
105} while (0)
106
107#ifdef CONFIG_VIRT_CPU_ACCOUNTING
108extern void account_user_vtime(struct task_struct *);
109extern void account_system_vtime(struct task_struct *);
110#endif
111
112#define finish_arch_switch(prev) do { \
113 set_fs(current->thread.mm_segment); \
114 account_system_vtime(prev); \
115} while (0)
116
117#define nop() __asm__ __volatile__ ("nop")
118
119#define xchg(ptr,x) \
120 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
121
122static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
123{
124 unsigned long addr, old;
125 int shift;
126
127 switch (size) {
128 case 1:
129 addr = (unsigned long) ptr;
130 shift = (3 ^ (addr & 3)) << 3;
131 addr ^= addr & 3;
132 asm volatile(
133 " l %0,0(%4)\n"
134 "0: lr 0,%0\n"
135 " nr 0,%3\n"
136 " or 0,%2\n"
137 " cs %0,0,0(%4)\n"
138 " jl 0b\n"
139 : "=&d" (old), "=m" (*(int *) addr)
140 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
141 "m" (*(int *) addr) : "memory", "cc", "0" );
142 x = old >> shift;
143 break;
144 case 2:
145 addr = (unsigned long) ptr;
146 shift = (2 ^ (addr & 2)) << 3;
147 addr ^= addr & 2;
148 asm volatile(
149 " l %0,0(%4)\n"
150 "0: lr 0,%0\n"
151 " nr 0,%3\n"
152 " or 0,%2\n"
153 " cs %0,0,0(%4)\n"
154 " jl 0b\n"
155 : "=&d" (old), "=m" (*(int *) addr)
156 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
157 "m" (*(int *) addr) : "memory", "cc", "0" );
158 x = old >> shift;
159 break;
160 case 4:
161 asm volatile (
162 " l %0,0(%3)\n"
163 "0: cs %0,%2,0(%3)\n"
164 " jl 0b\n"
165 : "=&d" (old), "=m" (*(int *) ptr)
166 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
167 : "memory", "cc" );
168 x = old;
169 break;
170#ifdef __s390x__
171 case 8:
172 asm volatile (
173 " lg %0,0(%3)\n"
174 "0: csg %0,%2,0(%3)\n"
175 " jl 0b\n"
176 : "=&d" (old), "=m" (*(long *) ptr)
177 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
178 : "memory", "cc" );
179 x = old;
180 break;
181#endif /* __s390x__ */
182 }
183 return x;
184}
185
186/*
187 * Atomic compare and exchange. Compare OLD with MEM, if identical,
188 * store NEW in MEM. Return the initial value in MEM. Success is
189 * indicated by comparing RETURN with OLD.
190 */
191
192#define __HAVE_ARCH_CMPXCHG 1
193
194#define cmpxchg(ptr,o,n)\
195 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
196 (unsigned long)(n),sizeof(*(ptr))))
197
198static inline unsigned long
199__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
200{
201 unsigned long addr, prev, tmp;
202 int shift;
203
204 switch (size) {
205 case 1:
206 addr = (unsigned long) ptr;
207 shift = (3 ^ (addr & 3)) << 3;
208 addr ^= addr & 3;
209 asm volatile(
210 " l %0,0(%4)\n"
211 "0: nr %0,%5\n"
212 " lr %1,%0\n"
213 " or %0,%2\n"
214 " or %1,%3\n"
215 " cs %0,%1,0(%4)\n"
216 " jnl 1f\n"
217 " xr %1,%0\n"
218 " nr %1,%5\n"
219 " jnz 0b\n"
220 "1:"
221 : "=&d" (prev), "=&d" (tmp)
222 : "d" (old << shift), "d" (new << shift), "a" (ptr),
223 "d" (~(255 << shift))
224 : "memory", "cc" );
225 return prev >> shift;
226 case 2:
227 addr = (unsigned long) ptr;
228 shift = (2 ^ (addr & 2)) << 3;
229 addr ^= addr & 2;
230 asm volatile(
231 " l %0,0(%4)\n"
232 "0: nr %0,%5\n"
233 " lr %1,%0\n"
234 " or %0,%2\n"
235 " or %1,%3\n"
236 " cs %0,%1,0(%4)\n"
237 " jnl 1f\n"
238 " xr %1,%0\n"
239 " nr %1,%5\n"
240 " jnz 0b\n"
241 "1:"
242 : "=&d" (prev), "=&d" (tmp)
243 : "d" (old << shift), "d" (new << shift), "a" (ptr),
244 "d" (~(65535 << shift))
245 : "memory", "cc" );
246 return prev >> shift;
247 case 4:
248 asm volatile (
249 " cs %0,%2,0(%3)\n"
250 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
251 : "memory", "cc" );
252 return prev;
253#ifdef __s390x__
254 case 8:
255 asm volatile (
256 " csg %0,%2,0(%3)\n"
257 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
258 : "memory", "cc" );
259 return prev;
260#endif /* __s390x__ */
261 }
262 return old;
263}
264
265/*
266 * Force strict CPU ordering.
267 * And yes, this is required on UP too when we're talking
268 * to devices.
269 *
270 * This is very similar to the ppc eieio/sync instruction in that is
271 * does a checkpoint syncronisation & makes sure that
272 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
273 */
274
275#define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
276# define SYNC_OTHER_CORES(x) eieio()
277#define mb() eieio()
278#define rmb() eieio()
279#define wmb() eieio()
280#define read_barrier_depends() do { } while(0)
281#define smp_mb() mb()
282#define smp_rmb() rmb()
283#define smp_wmb() wmb()
284#define smp_read_barrier_depends() read_barrier_depends()
285#define smp_mb__before_clear_bit() smp_mb()
286#define smp_mb__after_clear_bit() smp_mb()
287
288
289#define set_mb(var, value) do { var = value; mb(); } while (0)
290#define set_wmb(var, value) do { var = value; wmb(); } while (0)
291
292/* interrupt control.. */
293#define local_irq_enable() ({ \
294 unsigned long __dummy; \
295 __asm__ __volatile__ ( \
296 "stosm 0(%1),0x03" \
297 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
298 })
299
300#define local_irq_disable() ({ \
301 unsigned long __flags; \
302 __asm__ __volatile__ ( \
303 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
304 __flags; \
305 })
306
307#define local_save_flags(x) \
308 __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
309
310#define local_irq_restore(x) \
311 __asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory")
312
313#define irqs_disabled() \
314({ \
315 unsigned long flags; \
316 local_save_flags(flags); \
317 !((flags >> __FLAG_SHIFT) & 3); \
318})
319
320#ifdef __s390x__
321
322#define __ctl_load(array, low, high) ({ \
323 typedef struct { char _[sizeof(array)]; } addrtype; \
324 __asm__ __volatile__ ( \
325 " bras 1,0f\n" \
326 " lctlg 0,0,0(%0)\n" \
327 "0: ex %1,0(1)" \
328 : : "a" (&array), "a" (((low)<<4)+(high)), \
329 "m" (*(addrtype *)(array)) : "1" ); \
330 })
331
332#define __ctl_store(array, low, high) ({ \
333 typedef struct { char _[sizeof(array)]; } addrtype; \
334 __asm__ __volatile__ ( \
335 " bras 1,0f\n" \
336 " stctg 0,0,0(%1)\n" \
337 "0: ex %2,0(1)" \
338 : "=m" (*(addrtype *)(array)) \
339 : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
340 })
341
342#define __ctl_set_bit(cr, bit) ({ \
343 __u8 __dummy[24]; \
344 __asm__ __volatile__ ( \
345 " bras 1,0f\n" /* skip indirect insns */ \
346 " stctg 0,0,0(%1)\n" \
347 " lctlg 0,0,0(%1)\n" \
348 "0: ex %2,0(1)\n" /* execute stctl */ \
349 " lg 0,0(%1)\n" \
350 " ogr 0,%3\n" /* set the bit */ \
351 " stg 0,0(%1)\n" \
352 "1: ex %2,6(1)" /* execute lctl */ \
353 : "=m" (__dummy) \
354 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
355 "a" (cr*17), "a" (1L<<(bit)) \
356 : "cc", "0", "1" ); \
357 })
358
359#define __ctl_clear_bit(cr, bit) ({ \
360 __u8 __dummy[16]; \
361 __asm__ __volatile__ ( \
362 " bras 1,0f\n" /* skip indirect insns */ \
363 " stctg 0,0,0(%1)\n" \
364 " lctlg 0,0,0(%1)\n" \
365 "0: ex %2,0(1)\n" /* execute stctl */ \
366 " lg 0,0(%1)\n" \
367 " ngr 0,%3\n" /* set the bit */ \
368 " stg 0,0(%1)\n" \
369 "1: ex %2,6(1)" /* execute lctl */ \
370 : "=m" (__dummy) \
371 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
372 "a" (cr*17), "a" (~(1L<<(bit))) \
373 : "cc", "0", "1" ); \
374 })
375
376#else /* __s390x__ */
377
378#define __ctl_load(array, low, high) ({ \
379 typedef struct { char _[sizeof(array)]; } addrtype; \
380 __asm__ __volatile__ ( \
381 " bras 1,0f\n" \
382 " lctl 0,0,0(%0)\n" \
383 "0: ex %1,0(1)" \
384 : : "a" (&array), "a" (((low)<<4)+(high)), \
385 "m" (*(addrtype *)(array)) : "1" ); \
386 })
387
388#define __ctl_store(array, low, high) ({ \
389 typedef struct { char _[sizeof(array)]; } addrtype; \
390 __asm__ __volatile__ ( \
391 " bras 1,0f\n" \
392 " stctl 0,0,0(%1)\n" \
393 "0: ex %2,0(1)" \
394 : "=m" (*(addrtype *)(array)) \
395 : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
396 })
397
398#define __ctl_set_bit(cr, bit) ({ \
399 __u8 __dummy[16]; \
400 __asm__ __volatile__ ( \
401 " bras 1,0f\n" /* skip indirect insns */ \
402 " stctl 0,0,0(%1)\n" \
403 " lctl 0,0,0(%1)\n" \
404 "0: ex %2,0(1)\n" /* execute stctl */ \
405 " l 0,0(%1)\n" \
406 " or 0,%3\n" /* set the bit */ \
407 " st 0,0(%1)\n" \
408 "1: ex %2,4(1)" /* execute lctl */ \
409 : "=m" (__dummy) \
410 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
411 "a" (cr*17), "a" (1<<(bit)) \
412 : "cc", "0", "1" ); \
413 })
414
415#define __ctl_clear_bit(cr, bit) ({ \
416 __u8 __dummy[16]; \
417 __asm__ __volatile__ ( \
418 " bras 1,0f\n" /* skip indirect insns */ \
419 " stctl 0,0,0(%1)\n" \
420 " lctl 0,0,0(%1)\n" \
421 "0: ex %2,0(1)\n" /* execute stctl */ \
422 " l 0,0(%1)\n" \
423 " nr 0,%3\n" /* set the bit */ \
424 " st 0,0(%1)\n" \
425 "1: ex %2,4(1)" /* execute lctl */ \
426 : "=m" (__dummy) \
427 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
428 "a" (cr*17), "a" (~(1<<(bit))) \
429 : "cc", "0", "1" ); \
430 })
431#endif /* __s390x__ */
432
433/* For spinlocks etc */
434#define local_irq_save(x) ((x) = local_irq_disable())
435
436/*
437 * Use to set psw mask except for the first byte which
438 * won't be changed by this function.
439 */
440static inline void
441__set_psw_mask(unsigned long mask)
442{
443 local_save_flags(mask);
444 __load_psw_mask(mask);
445}
446
447#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
448#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
449
450#ifdef CONFIG_SMP
451
452extern void smp_ctl_set_bit(int cr, int bit);
453extern void smp_ctl_clear_bit(int cr, int bit);
454#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
455#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
456
457#else
458
459#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
460#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
461
462#endif /* CONFIG_SMP */
463
464extern void (*_machine_restart)(char *command);
465extern void (*_machine_halt)(void);
466extern void (*_machine_power_off)(void);
467
468#define arch_align_stack(x) (x)
469
470#endif /* __KERNEL__ */
471
472#endif
473