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Linux kernel mirror (for testing)
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1/*
2 * File Name:
3 * defxx.h
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * Contains all definitions specified by port specification and required
13 * by the defxx.c driver.
14 *
15 * The original author:
16 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
17 *
18 * Maintainers:
19 * macro Maciej W. Rozycki <macro@linux-mips.org>
20 *
21 * Modification History:
22 * Date Name Description
23 * 16-Aug-96 LVS Created.
24 * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O
25 * macros to DEFXX.C.
26 * 12-Sep-96 LVS Removed packet request header pointers.
27 * 04 Aug 2003 macro Converted to the DMA API.
28 */
29
30#ifndef _DEFXX_H_
31#define _DEFXX_H_
32
33/* Define basic types for unsigned chars, shorts, longs */
34
35typedef u8 PI_UINT8;
36typedef u16 PI_UINT16;
37typedef u32 PI_UINT32;
38
39/* Define general structures */
40
41typedef struct /* 64-bit counter */
42 {
43 PI_UINT32 ms;
44 PI_UINT32 ls;
45 } PI_CNTR;
46
47typedef struct /* LAN address */
48 {
49 PI_UINT32 lwrd_0;
50 PI_UINT32 lwrd_1;
51 } PI_LAN_ADDR;
52
53typedef struct /* Station ID address */
54 {
55 PI_UINT32 octet_7_4;
56 PI_UINT32 octet_3_0;
57 } PI_STATION_ID;
58
59
60/* Define general constants */
61
62#define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */
63#define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */
64#define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */
65#define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */
66#define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */
67#define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
68#define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */
69
70/* Define PHY index values */
71
72#define PI_PHY_K_S 0 /* Index to S phy */
73#define PI_PHY_K_A 0 /* Index to A phy */
74#define PI_PHY_K_B 1 /* Index to B phy */
75#define PI_PHY_K_MAX 2 /* Max number of phys */
76
77/* Define FMC descriptor fields */
78
79#define PI_FMC_DESCR_V_SOP 31
80#define PI_FMC_DESCR_V_EOP 30
81#define PI_FMC_DESCR_V_FSC 27
82#define PI_FMC_DESCR_V_FSB_ERROR 26
83#define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25
84#define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24
85#define PI_FMC_DESCR_V_FSB 22
86#define PI_FMC_DESCR_V_RCC_FLUSH 21
87#define PI_FMC_DESCR_V_RCC_CRC 20
88#define PI_FMC_DESCR_V_RCC_RRR 17
89#define PI_FMC_DESCR_V_RCC_DD 15
90#define PI_FMC_DESCR_V_RCC_SS 13
91#define PI_FMC_DESCR_V_RCC 13
92#define PI_FMC_DESCR_V_LEN 0
93
94#define PI_FMC_DESCR_M_SOP 0x80000000
95#define PI_FMC_DESCR_M_EOP 0x40000000
96#define PI_FMC_DESCR_M_FSC 0x38000000
97#define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
98#define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
99#define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
100#define PI_FMC_DESCR_M_FSB 0x07C00000
101#define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000
102#define PI_FMC_DESCR_M_RCC_CRC 0x00100000
103#define PI_FMC_DESCR_M_RCC_RRR 0x000E0000
104#define PI_FMC_DESCR_M_RCC_DD 0x00018000
105#define PI_FMC_DESCR_M_RCC_SS 0x00006000
106#define PI_FMC_DESCR_M_RCC 0x003FE000
107#define PI_FMC_DESCR_M_LEN 0x00001FFF
108
109#define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA
110
111#define PI_FMC_DESCR_K_RRR_SUCCESS 0x00
112#define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01
113#define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02
114#define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03
115#define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04
116#define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05
117#define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06
118#define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07
119
120#define PI_FMC_DESCR_K_DD_NO_MATCH 0x0
121#define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1
122#define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2
123#define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3
124
125#define PI_FMC_DESCR_K_SS_NO_MATCH 0x0
126#define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1
127#define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2
128#define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3
129
130/* Define some max buffer sizes */
131
132#define PI_CMD_REQ_K_SIZE_MAX 512
133#define PI_CMD_RSP_K_SIZE_MAX 512
134#define PI_UNSOL_K_SIZE_MAX 512
135#define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */
136#define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
137#define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
138
139/* Define adapter states */
140
141#define PI_STATE_K_RESET 0
142#define PI_STATE_K_UPGRADE 1
143#define PI_STATE_K_DMA_UNAVAIL 2
144#define PI_STATE_K_DMA_AVAIL 3
145#define PI_STATE_K_LINK_AVAIL 4
146#define PI_STATE_K_LINK_UNAVAIL 5
147#define PI_STATE_K_HALTED 6
148#define PI_STATE_K_RING_MEMBER 7
149#define PI_STATE_K_NUMBER 8
150
151/* Define codes for command type */
152
153#define PI_CMD_K_START 0x00
154#define PI_CMD_K_FILTERS_SET 0x01
155#define PI_CMD_K_FILTERS_GET 0x02
156#define PI_CMD_K_CHARS_SET 0x03
157#define PI_CMD_K_STATUS_CHARS_GET 0x04
158#define PI_CMD_K_CNTRS_GET 0x05
159#define PI_CMD_K_CNTRS_SET 0x06
160#define PI_CMD_K_ADDR_FILTER_SET 0x07
161#define PI_CMD_K_ADDR_FILTER_GET 0x08
162#define PI_CMD_K_ERROR_LOG_CLEAR 0x09
163#define PI_CMD_K_ERROR_LOG_GET 0x0A
164#define PI_CMD_K_FDDI_MIB_GET 0x0B
165#define PI_CMD_K_DEC_EXT_MIB_GET 0x0C
166#define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D
167#define PI_CMD_K_SNMP_SET 0x0E
168#define PI_CMD_K_UNSOL_TEST 0x0F
169#define PI_CMD_K_SMT_MIB_GET 0x10
170#define PI_CMD_K_SMT_MIB_SET 0x11
171#define PI_CMD_K_MAX 0x11 /* Must match last */
172
173/* Define item codes for Chars_Set and Filters_Set commands */
174
175#define PI_ITEM_K_EOL 0x00 /* End-of-Item list */
176#define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */
177#define PI_ITEM_K_TVX 0x02 /* DECnet TVX */
178#define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */
179#define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */
180#define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */
181#define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */
182#define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */
183#define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */
184#define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */
185#define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */
186#define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */
187#define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */
188#define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */
189#define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */
190#define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */
191#define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */
192#define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */
193#define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */
194#define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */
195#define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */
196#define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */
197#define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */
198#define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */
199#define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */
200#define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */
201#define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */
202#define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */
203#define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */
204#define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */
205#define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */
206#define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */
207#define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */
208#define PI_ITEM_K_MAX 0x2C /* Must equal high item */
209
210/* Values for some of the items */
211
212#define PI_K_FALSE 0 /* Generic false */
213#define PI_K_TRUE 1 /* Generic true */
214
215#define PI_SNMP_K_TRUE 1 /* SNMP true/false values */
216#define PI_SNMP_K_FALSE 2
217
218#define PI_FSTATE_K_BLOCK 0 /* Filter State */
219#define PI_FSTATE_K_PASS 1
220
221/* Define command return codes */
222
223#define PI_RSP_K_SUCCESS 0x00
224#define PI_RSP_K_FAILURE 0x01
225#define PI_RSP_K_WARNING 0x02
226#define PI_RSP_K_LOOP_MODE_BAD 0x03
227#define PI_RSP_K_ITEM_CODE_BAD 0x04
228#define PI_RSP_K_TVX_BAD 0x05
229#define PI_RSP_K_TREQ_BAD 0x06
230#define PI_RSP_K_TOKEN_BAD 0x07
231#define PI_RSP_K_NO_EOL 0x0C
232#define PI_RSP_K_FILTER_STATE_BAD 0x0D
233#define PI_RSP_K_CMD_TYPE_BAD 0x0E
234#define PI_RSP_K_ADAPTER_STATE_BAD 0x0F
235#define PI_RSP_K_RING_PURGER_BAD 0x10
236#define PI_RSP_K_LEM_THRESHOLD_BAD 0x11
237#define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12
238#define PI_RSP_K_FLUSH_TIME_BAD 0x13
239#define PI_RSP_K_NOT_IMPLEMENTED 0x14
240#define PI_RSP_K_CONFIG_POLICY_BAD 0x15
241#define PI_RSP_K_STATION_ACTION_BAD 0x16
242#define PI_RSP_K_MAC_ACTION_BAD 0x17
243#define PI_RSP_K_CON_POLICIES_BAD 0x18
244#define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19
245#define PI_RSP_K_TB_MAX_BAD 0x1A
246#define PI_RSP_K_LER_CUTOFF_BAD 0x1B
247#define PI_RSP_K_LER_ALARM_BAD 0x1C
248#define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D
249#define PI_RSP_K_MAC_T_REQ_BAD 0x1E
250#define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F
251#define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20
252#define PI_RSP_K_NO_SUCH_ENTRY 0x21
253#define PI_RSP_K_T_NOTIFY_BAD 0x22
254#define PI_RSP_K_TR_MAX_EXP_BAD 0x23
255#define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24
256#define PI_RSP_K_MAX_T_REQ_BAD 0x25
257#define PI_RSP_K_FDX_ENB_DIS_BAD 0x26
258#define PI_RSP_K_ITEM_INDEX_BAD 0x27
259#define PI_RSP_K_PORT_ACTION_BAD 0x28
260
261/* Commonly used structures */
262
263typedef struct /* Item list */
264 {
265 PI_UINT32 item_code;
266 PI_UINT32 value;
267 } PI_ITEM_LIST;
268
269typedef struct /* Response header */
270 {
271 PI_UINT32 reserved;
272 PI_UINT32 cmd_type;
273 PI_UINT32 status;
274 } PI_RSP_HEADER;
275
276
277/* Start Command */
278
279typedef struct
280 {
281 PI_UINT32 cmd_type;
282 } PI_CMD_START_REQ;
283
284/* Start Response */
285
286typedef struct
287 {
288 PI_RSP_HEADER header;
289 } PI_CMD_START_RSP;
290
291/* Filters_Set Request */
292
293#define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */
294
295typedef struct
296 {
297 PI_UINT32 cmd_type;
298 PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
299 } PI_CMD_FILTERS_SET_REQ;
300
301/* Filters_Set Response */
302
303typedef struct
304 {
305 PI_RSP_HEADER header;
306 } PI_CMD_FILTERS_SET_RSP;
307
308/* Filters_Get Request */
309
310typedef struct
311 {
312 PI_UINT32 cmd_type;
313 } PI_CMD_FILTERS_GET_REQ;
314
315/* Filters_Get Response */
316
317typedef struct
318 {
319 PI_RSP_HEADER header;
320 PI_UINT32 ind_group_prom;
321 PI_UINT32 group_prom;
322 PI_UINT32 broadcast_all;
323 PI_UINT32 smt_all;
324 PI_UINT32 smt_user;
325 PI_UINT32 reserved_all;
326 PI_UINT32 implementor_all;
327 } PI_CMD_FILTERS_GET_RSP;
328
329
330/* Chars_Set Request */
331
332#define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
333
334typedef struct
335 {
336 PI_UINT32 cmd_type;
337 struct /* Item list */
338 {
339 PI_UINT32 item_code;
340 PI_UINT32 value;
341 PI_UINT32 item_index;
342 } item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
343 } PI_CMD_CHARS_SET_REQ;
344
345/* Chars_Set Response */
346
347typedef struct
348 {
349 PI_RSP_HEADER header;
350 } PI_CMD_CHARS_SET_RSP;
351
352
353/* SNMP_Set Request */
354
355#define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
356
357typedef struct
358 {
359 PI_UINT32 cmd_type;
360 struct /* Item list */
361 {
362 PI_UINT32 item_code;
363 PI_UINT32 value;
364 PI_UINT32 item_index;
365 } item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
366 } PI_CMD_SNMP_SET_REQ;
367
368/* SNMP_Set Response */
369
370typedef struct
371 {
372 PI_RSP_HEADER header;
373 } PI_CMD_SNMP_SET_RSP;
374
375
376/* SMT_MIB_Set Request */
377
378#define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */
379
380typedef struct
381 {
382 PI_UINT32 cmd_type;
383 struct
384 {
385 PI_UINT32 item_code;
386 PI_UINT32 value;
387 PI_UINT32 item_index;
388 } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
389 } PI_CMD_SMT_MIB_SET_REQ;
390
391/* SMT_MIB_Set Response */
392
393typedef struct
394 {
395 PI_RSP_HEADER header;
396 } PI_CMD_SMT_MIB_SET_RSP;
397
398/* SMT_MIB_Get Request */
399
400typedef struct
401 {
402 PI_UINT32 cmd_type;
403 } PI_CMD_SMT_MIB_GET_REQ;
404
405/* SMT_MIB_Get Response */
406
407typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */
408 {
409 PI_RSP_HEADER header;
410
411 /* SMT GROUP */
412
413 PI_STATION_ID smt_station_id;
414 PI_UINT32 smt_op_version_id;
415 PI_UINT32 smt_hi_version_id;
416 PI_UINT32 smt_lo_version_id;
417 PI_UINT32 smt_user_data[8];
418 PI_UINT32 smt_mib_version_id;
419 PI_UINT32 smt_mac_ct;
420 PI_UINT32 smt_non_master_ct;
421 PI_UINT32 smt_master_ct;
422 PI_UINT32 smt_available_paths;
423 PI_UINT32 smt_config_capabilities;
424 PI_UINT32 smt_config_policy;
425 PI_UINT32 smt_connection_policy;
426 PI_UINT32 smt_t_notify;
427 PI_UINT32 smt_stat_rpt_policy;
428 PI_UINT32 smt_trace_max_expiration;
429 PI_UINT32 smt_bypass_present;
430 PI_UINT32 smt_ecm_state;
431 PI_UINT32 smt_cf_state;
432 PI_UINT32 smt_remote_disconnect_flag;
433 PI_UINT32 smt_station_status;
434 PI_UINT32 smt_peer_wrap_flag;
435 PI_CNTR smt_msg_time_stamp;
436 PI_CNTR smt_transition_time_stamp;
437
438 /* MAC GROUP */
439
440 PI_UINT32 mac_frame_status_functions;
441 PI_UINT32 mac_t_max_capability;
442 PI_UINT32 mac_tvx_capability;
443 PI_UINT32 mac_available_paths;
444 PI_UINT32 mac_current_path;
445 PI_LAN_ADDR mac_upstream_nbr;
446 PI_LAN_ADDR mac_downstream_nbr;
447 PI_LAN_ADDR mac_old_upstream_nbr;
448 PI_LAN_ADDR mac_old_downstream_nbr;
449 PI_UINT32 mac_dup_address_test;
450 PI_UINT32 mac_requested_paths;
451 PI_UINT32 mac_downstream_port_type;
452 PI_LAN_ADDR mac_smt_address;
453 PI_UINT32 mac_t_req;
454 PI_UINT32 mac_t_neg;
455 PI_UINT32 mac_t_max;
456 PI_UINT32 mac_tvx_value;
457 PI_UINT32 mac_frame_error_threshold;
458 PI_UINT32 mac_frame_error_ratio;
459 PI_UINT32 mac_rmt_state;
460 PI_UINT32 mac_da_flag;
461 PI_UINT32 mac_unda_flag;
462 PI_UINT32 mac_frame_error_flag;
463 PI_UINT32 mac_ma_unitdata_available;
464 PI_UINT32 mac_hardware_present;
465 PI_UINT32 mac_ma_unitdata_enable;
466
467 /* PATH GROUP */
468
469 PI_UINT32 path_configuration[8];
470 PI_UINT32 path_tvx_lower_bound;
471 PI_UINT32 path_t_max_lower_bound;
472 PI_UINT32 path_max_t_req;
473
474 /* PORT GROUP */
475
476 PI_UINT32 port_my_type[PI_PHY_K_MAX];
477 PI_UINT32 port_neighbor_type[PI_PHY_K_MAX];
478 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
479 PI_UINT32 port_mac_indicated[PI_PHY_K_MAX];
480 PI_UINT32 port_current_path[PI_PHY_K_MAX];
481 PI_UINT32 port_requested_paths[PI_PHY_K_MAX];
482 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
483 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
484 PI_UINT32 port_pmd_class[PI_PHY_K_MAX];
485 PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX];
486 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
487 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
488 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
489 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
490 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
491 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
492 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
493 PI_UINT32 port_ler_flag[PI_PHY_K_MAX];
494 PI_UINT32 port_hardware_present[PI_PHY_K_MAX];
495
496 /* GROUP for things that were added later, so must be at the end. */
497
498 PI_CNTR path_ring_latency;
499
500 } PI_CMD_SMT_MIB_GET_RSP;
501
502
503/*
504 * Item and group code definitions for SMT 7.3 mandatory objects. These
505 * definitions are to be used as appropriate in SMT_MIB_SET commands and
506 * certain host-sent SMT frames such as PMF Get and Set requests. The
507 * codes have been taken from the MIB summary section of ANSI SMT 7.3.
508 */
509
510#define PI_GRP_K_SMT_STATION_ID 0x100A
511#define PI_ITEM_K_SMT_STATION_ID 0x100B
512#define PI_ITEM_K_SMT_OP_VERS_ID 0x100D
513#define PI_ITEM_K_SMT_HI_VERS_ID 0x100E
514#define PI_ITEM_K_SMT_LO_VERS_ID 0x100F
515#define PI_ITEM_K_SMT_USER_DATA 0x1011
516#define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012
517
518#define PI_GRP_K_SMT_STATION_CONFIG 0x1014
519#define PI_ITEM_K_SMT_MAC_CT 0x1015
520#define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016
521#define PI_ITEM_K_SMT_MASTER_CT 0x1017
522#define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018
523#define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019
524#define PI_ITEM_K_SMT_CONFIG_POL 0x101A
525#define PI_ITEM_K_SMT_CONN_POL 0x101B
526#define PI_ITEM_K_SMT_T_NOTIFY 0x101D
527#define PI_ITEM_K_SMT_STAT_POL 0x101E
528#define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F
529#define PI_ITEM_K_SMT_PORT_INDEXES 0x1020
530#define PI_ITEM_K_SMT_MAC_INDEXES 0x1021
531#define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022
532
533#define PI_GRP_K_SMT_STATUS 0x1028
534#define PI_ITEM_K_SMT_ECM_STATE 0x1029
535#define PI_ITEM_K_SMT_CF_STATE 0x102A
536#define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C
537#define PI_ITEM_K_SMT_STATION_STATUS 0x102D
538#define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E
539
540#define PI_GRP_K_SMT_MIB_OPERATION 0x1032
541#define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033
542#define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034
543
544#define PI_ITEM_K_SMT_STATION_ACT 0x103C
545
546#define PI_GRP_K_MAC_CAPABILITIES 0x200A
547#define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B
548#define PI_ITEM_K_MAC_T_MAX_CAP 0x200D
549#define PI_ITEM_K_MAC_TVX_CAP 0x200E
550
551#define PI_GRP_K_MAC_CONFIG 0x2014
552#define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016
553#define PI_ITEM_K_MAC_CURRENT_PATH 0x2017
554#define PI_ITEM_K_MAC_UP_NBR 0x2018
555#define PI_ITEM_K_MAC_DOWN_NBR 0x2019
556#define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A
557#define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B
558#define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D
559#define PI_ITEM_K_MAC_REQ_PATHS 0x2020
560#define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021
561#define PI_ITEM_K_MAC_INDEX 0x2022
562
563#define PI_GRP_K_MAC_ADDRESS 0x2028
564#define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029
565
566#define PI_GRP_K_MAC_OPERATION 0x2032
567#define PI_ITEM_K_MAC_TREQ 0x2033
568#define PI_ITEM_K_MAC_TNEG 0x2034
569#define PI_ITEM_K_MAC_TMAX 0x2035
570#define PI_ITEM_K_MAC_TVX_VALUE 0x2036
571
572#define PI_GRP_K_MAC_COUNTERS 0x2046
573#define PI_ITEM_K_MAC_FRAME_CT 0x2047
574#define PI_ITEM_K_MAC_COPIED_CT 0x2048
575#define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049
576#define PI_ITEM_K_MAC_ERROR_CT 0x2051
577#define PI_ITEM_K_MAC_LOST_CT 0x2052
578
579#define PI_GRP_K_MAC_FRM_ERR_COND 0x205A
580#define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F
581#define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060
582
583#define PI_GRP_K_MAC_STATUS 0x206E
584#define PI_ITEM_K_MAC_RMT_STATE 0x206F
585#define PI_ITEM_K_MAC_DA_FLAG 0x2070
586#define PI_ITEM_K_MAC_UNDA_FLAG 0x2071
587#define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072
588#define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074
589#define PI_ITEM_K_MAC_HW_PRESENT 0x2075
590#define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076
591
592#define PI_GRP_K_PATH_CONFIG 0x320A
593#define PI_ITEM_K_PATH_INDEX 0x320B
594#define PI_ITEM_K_PATH_CONFIGURATION 0x3212
595#define PI_ITEM_K_PATH_TVX_LB 0x3215
596#define PI_ITEM_K_PATH_T_MAX_LB 0x3216
597#define PI_ITEM_K_PATH_MAX_T_REQ 0x3217
598
599#define PI_GRP_K_PORT_CONFIG 0x400A
600#define PI_ITEM_K_PORT_MY_TYPE 0x400C
601#define PI_ITEM_K_PORT_NBR_TYPE 0x400D
602#define PI_ITEM_K_PORT_CONN_POLS 0x400E
603#define PI_ITEM_K_PORT_MAC_INDICATED 0x400F
604#define PI_ITEM_K_PORT_CURRENT_PATH 0x4010
605#define PI_ITEM_K_PORT_REQ_PATHS 0x4011
606#define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012
607#define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013
608#define PI_ITEM_K_PORT_PMD_CLASS 0x4016
609#define PI_ITEM_K_PORT_CONN_CAPS 0x4017
610#define PI_ITEM_K_PORT_INDEX 0x401D
611
612#define PI_GRP_K_PORT_OPERATION 0x401E
613#define PI_ITEM_K_PORT_BS_FLAG 0x4021
614
615#define PI_GRP_K_PORT_ERR_CNTRS 0x4028
616#define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A
617
618#define PI_GRP_K_PORT_LER 0x4032
619#define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033
620#define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034
621#define PI_ITEM_K_PORT_LEM_CT 0x4035
622#define PI_ITEM_K_PORT_LER_CUTOFF 0x403A
623#define PI_ITEM_K_PORT_LER_ALARM 0x403B
624
625#define PI_GRP_K_PORT_STATUS 0x403C
626#define PI_ITEM_K_PORT_CONNECT_STATE 0x403D
627#define PI_ITEM_K_PORT_PCM_STATE 0x403E
628#define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F
629#define PI_ITEM_K_PORT_LER_FLAG 0x4040
630#define PI_ITEM_K_PORT_HW_PRESENT 0x4041
631
632#define PI_ITEM_K_PORT_ACT 0x4046
633
634/* Addr_Filter_Set Request */
635
636#define PI_CMD_ADDR_FILTER_K_SIZE 62
637
638typedef struct
639 {
640 PI_UINT32 cmd_type;
641 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
642 } PI_CMD_ADDR_FILTER_SET_REQ;
643
644/* Addr_Filter_Set Response */
645
646typedef struct
647 {
648 PI_RSP_HEADER header;
649 } PI_CMD_ADDR_FILTER_SET_RSP;
650
651/* Addr_Filter_Get Request */
652
653typedef struct
654 {
655 PI_UINT32 cmd_type;
656 } PI_CMD_ADDR_FILTER_GET_REQ;
657
658/* Addr_Filter_Get Response */
659
660typedef struct
661 {
662 PI_RSP_HEADER header;
663 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
664 } PI_CMD_ADDR_FILTER_GET_RSP;
665
666/* Status_Chars_Get Request */
667
668typedef struct
669 {
670 PI_UINT32 cmd_type;
671 } PI_CMD_STATUS_CHARS_GET_REQ;
672
673/* Status_Chars_Get Response */
674
675typedef struct
676 {
677 PI_RSP_HEADER header;
678 PI_STATION_ID station_id; /* Station */
679 PI_UINT32 station_type;
680 PI_UINT32 smt_ver_id;
681 PI_UINT32 smt_ver_id_max;
682 PI_UINT32 smt_ver_id_min;
683 PI_UINT32 station_state;
684 PI_LAN_ADDR link_addr; /* Link */
685 PI_UINT32 t_req;
686 PI_UINT32 tvx;
687 PI_UINT32 token_timeout;
688 PI_UINT32 purger_enb;
689 PI_UINT32 link_state;
690 PI_UINT32 tneg;
691 PI_UINT32 dup_addr_flag;
692 PI_LAN_ADDR una;
693 PI_LAN_ADDR una_old;
694 PI_UINT32 un_dup_addr_flag;
695 PI_LAN_ADDR dna;
696 PI_LAN_ADDR dna_old;
697 PI_UINT32 purger_state;
698 PI_UINT32 fci_mode;
699 PI_UINT32 error_reason;
700 PI_UINT32 loopback;
701 PI_UINT32 ring_latency;
702 PI_LAN_ADDR last_dir_beacon_sa;
703 PI_LAN_ADDR last_dir_beacon_una;
704 PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */
705 PI_UINT32 pmd_type[PI_PHY_K_MAX];
706 PI_UINT32 lem_threshold[PI_PHY_K_MAX];
707 PI_UINT32 phy_state[PI_PHY_K_MAX];
708 PI_UINT32 nbor_phy_type[PI_PHY_K_MAX];
709 PI_UINT32 link_error_est[PI_PHY_K_MAX];
710 PI_UINT32 broken_reason[PI_PHY_K_MAX];
711 PI_UINT32 reject_reason[PI_PHY_K_MAX];
712 PI_UINT32 cntr_interval; /* Miscellaneous */
713 PI_UINT32 module_rev;
714 PI_UINT32 firmware_rev;
715 PI_UINT32 mop_device_type;
716 PI_UINT32 phy_led[PI_PHY_K_MAX];
717 PI_UINT32 flush_time;
718 } PI_CMD_STATUS_CHARS_GET_RSP;
719
720/* FDDI_MIB_Get Request */
721
722typedef struct
723 {
724 PI_UINT32 cmd_type;
725 } PI_CMD_FDDI_MIB_GET_REQ;
726
727/* FDDI_MIB_Get Response */
728
729typedef struct
730 {
731 PI_RSP_HEADER header;
732
733 /* SMT GROUP */
734
735 PI_STATION_ID smt_station_id;
736 PI_UINT32 smt_op_version_id;
737 PI_UINT32 smt_hi_version_id;
738 PI_UINT32 smt_lo_version_id;
739 PI_UINT32 smt_mac_ct;
740 PI_UINT32 smt_non_master_ct;
741 PI_UINT32 smt_master_ct;
742 PI_UINT32 smt_paths_available;
743 PI_UINT32 smt_config_capabilities;
744 PI_UINT32 smt_config_policy;
745 PI_UINT32 smt_connection_policy;
746 PI_UINT32 smt_t_notify;
747 PI_UINT32 smt_status_reporting;
748 PI_UINT32 smt_ecm_state;
749 PI_UINT32 smt_cf_state;
750 PI_UINT32 smt_hold_state;
751 PI_UINT32 smt_remote_disconnect_flag;
752 PI_UINT32 smt_station_action;
753
754 /* MAC GROUP */
755
756 PI_UINT32 mac_frame_status_capabilities;
757 PI_UINT32 mac_t_max_greatest_lower_bound;
758 PI_UINT32 mac_tvx_greatest_lower_bound;
759 PI_UINT32 mac_paths_available;
760 PI_UINT32 mac_current_path;
761 PI_LAN_ADDR mac_upstream_nbr;
762 PI_LAN_ADDR mac_old_upstream_nbr;
763 PI_UINT32 mac_dup_addr_test;
764 PI_UINT32 mac_paths_requested;
765 PI_UINT32 mac_downstream_port_type;
766 PI_LAN_ADDR mac_smt_address;
767 PI_UINT32 mac_t_req;
768 PI_UINT32 mac_t_neg;
769 PI_UINT32 mac_t_max;
770 PI_UINT32 mac_tvx_value;
771 PI_UINT32 mac_t_min;
772 PI_UINT32 mac_current_frame_status;
773 /* mac_frame_cts */
774 /* mac_error_cts */
775 /* mac_lost_cts */
776 PI_UINT32 mac_frame_error_threshold;
777 PI_UINT32 mac_frame_error_ratio;
778 PI_UINT32 mac_rmt_state;
779 PI_UINT32 mac_da_flag;
780 PI_UINT32 mac_una_da_flag;
781 PI_UINT32 mac_frame_condition;
782 PI_UINT32 mac_chip_set;
783 PI_UINT32 mac_action;
784
785 /* PATH GROUP => Does not need to be implemented */
786
787 /* PORT GROUP */
788
789 PI_UINT32 port_pc_type[PI_PHY_K_MAX];
790 PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX];
791 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
792 PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX];
793 PI_UINT32 port_ce_state[PI_PHY_K_MAX];
794 PI_UINT32 port_paths_requested[PI_PHY_K_MAX];
795 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
796 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
797 PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX];
798 PI_UINT32 port_tb_max[PI_PHY_K_MAX];
799 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
800 /* port_lct_fail_cts[PI_PHY_K_MAX]; */
801 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
802 /* port_lem_reject_cts[PI_PHY_K_MAX]; */
803 /* port_lem_cts[PI_PHY_K_MAX]; */
804 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
805 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
806 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
807 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
808 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
809 PI_UINT32 port_ler_condition[PI_PHY_K_MAX];
810 PI_UINT32 port_chip_set[PI_PHY_K_MAX];
811 PI_UINT32 port_action[PI_PHY_K_MAX];
812
813 /* ATTACHMENT GROUP */
814
815 PI_UINT32 attachment_class;
816 PI_UINT32 attachment_ob_present;
817 PI_UINT32 attachment_imax_expiration;
818 PI_UINT32 attachment_inserted_status;
819 PI_UINT32 attachment_insert_policy;
820
821 /* CHIP SET GROUP => Does not need to be implemented */
822
823 } PI_CMD_FDDI_MIB_GET_RSP;
824
825/* DEC_Ext_MIB_Get Request */
826
827typedef struct
828 {
829 PI_UINT32 cmd_type;
830 } PI_CMD_DEC_EXT_MIB_GET_REQ;
831
832/* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
833
834typedef struct
835 {
836 PI_RSP_HEADER header;
837
838 /* SMT GROUP */
839
840 PI_UINT32 esmt_station_type;
841
842 /* MAC GROUP */
843
844 PI_UINT32 emac_link_state;
845 PI_UINT32 emac_ring_purger_state;
846 PI_UINT32 emac_ring_purger_enable;
847 PI_UINT32 emac_frame_strip_mode;
848 PI_UINT32 emac_ring_error_reason;
849 PI_UINT32 emac_up_nbr_dup_addr_flag;
850 PI_UINT32 emac_restricted_token_timeout;
851
852 /* PORT GROUP */
853
854 PI_UINT32 eport_pmd_type[PI_PHY_K_MAX];
855 PI_UINT32 eport_phy_state[PI_PHY_K_MAX];
856 PI_UINT32 eport_reject_reason[PI_PHY_K_MAX];
857
858 /* FDX (Full-Duplex) GROUP */
859
860 PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */
861 PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */
862 PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */
863
864 } PI_CMD_DEC_EXT_MIB_GET_RSP;
865
866typedef struct
867 {
868 PI_CNTR traces_rcvd; /* Station */
869 PI_CNTR frame_cnt; /* Link */
870 PI_CNTR error_cnt;
871 PI_CNTR lost_cnt;
872 PI_CNTR octets_rcvd;
873 PI_CNTR octets_sent;
874 PI_CNTR pdus_rcvd;
875 PI_CNTR pdus_sent;
876 PI_CNTR mcast_octets_rcvd;
877 PI_CNTR mcast_octets_sent;
878 PI_CNTR mcast_pdus_rcvd;
879 PI_CNTR mcast_pdus_sent;
880 PI_CNTR xmt_underruns;
881 PI_CNTR xmt_failures;
882 PI_CNTR block_check_errors;
883 PI_CNTR frame_status_errors;
884 PI_CNTR pdu_length_errors;
885 PI_CNTR rcv_overruns;
886 PI_CNTR user_buff_unavailable;
887 PI_CNTR inits_initiated;
888 PI_CNTR inits_rcvd;
889 PI_CNTR beacons_initiated;
890 PI_CNTR dup_addrs;
891 PI_CNTR dup_tokens;
892 PI_CNTR purge_errors;
893 PI_CNTR fci_strip_errors;
894 PI_CNTR traces_initiated;
895 PI_CNTR directed_beacons_rcvd;
896 PI_CNTR emac_frame_alignment_errors;
897 PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */
898 PI_CNTR lct_rejects[PI_PHY_K_MAX];
899 PI_CNTR lem_rejects[PI_PHY_K_MAX];
900 PI_CNTR link_errors[PI_PHY_K_MAX];
901 PI_CNTR connections[PI_PHY_K_MAX];
902 PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */
903 PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */
904 PI_CNTR tokens;
905 } PI_CNTR_BLK;
906
907/* Counters_Get Request */
908
909typedef struct
910 {
911 PI_UINT32 cmd_type;
912 } PI_CMD_CNTRS_GET_REQ;
913
914/* Counters_Get Response */
915
916typedef struct
917 {
918 PI_RSP_HEADER header;
919 PI_CNTR time_since_reset;
920 PI_CNTR_BLK cntrs;
921 } PI_CMD_CNTRS_GET_RSP;
922
923/* Counters_Set Request */
924
925typedef struct
926 {
927 PI_UINT32 cmd_type;
928 PI_CNTR_BLK cntrs;
929 } PI_CMD_CNTRS_SET_REQ;
930
931/* Counters_Set Response */
932
933typedef struct
934 {
935 PI_RSP_HEADER header;
936 } PI_CMD_CNTRS_SET_RSP;
937
938/* Error_Log_Clear Request */
939
940typedef struct
941 {
942 PI_UINT32 cmd_type;
943 } PI_CMD_ERROR_LOG_CLEAR_REQ;
944
945/* Error_Log_Clear Response */
946
947typedef struct
948 {
949 PI_RSP_HEADER header;
950 } PI_CMD_ERROR_LOG_CLEAR_RSP;
951
952/* Error_Log_Get Request */
953
954#define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */
955
956typedef struct
957 {
958 PI_UINT32 cmd_type;
959 PI_UINT32 entry_index;
960 } PI_CMD_ERROR_LOG_GET_REQ;
961
962/* Error_Log_Get Response */
963
964#define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */
965#define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */
966
967typedef struct
968 {
969 struct
970 {
971 PI_UINT32 fru_imp_mask;
972 PI_UINT32 test_id;
973 PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE];
974 } diag;
975 PI_UINT32 fw[PI_K_LOG_FW_SIZE];
976 } PI_LOG_ENTRY;
977
978typedef struct
979 {
980 PI_RSP_HEADER header;
981 PI_UINT32 event_status;
982 PI_UINT32 caller_id;
983 PI_UINT32 timestamp_l;
984 PI_UINT32 timestamp_h;
985 PI_UINT32 write_count;
986 PI_LOG_ENTRY entry_info;
987 } PI_CMD_ERROR_LOG_GET_RSP;
988
989/* Define error log related constants and types. */
990/* Not all of the caller id's can occur. The only ones currently */
991/* implemented are: none, selftest, mfg, fw, console */
992
993#define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */
994#define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */
995#define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */
996#define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */
997#define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */
998#define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */
999#define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */
1000#define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */
1001#define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */
1002#define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */
1003#define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */
1004
1005/*
1006 * Place all DMA commands in the following request and response structures
1007 * to simplify code.
1008 */
1009
1010typedef union
1011 {
1012 PI_UINT32 cmd_type;
1013 PI_CMD_START_REQ start;
1014 PI_CMD_FILTERS_SET_REQ filter_set;
1015 PI_CMD_FILTERS_GET_REQ filter_get;
1016 PI_CMD_CHARS_SET_REQ char_set;
1017 PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set;
1018 PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get;
1019 PI_CMD_STATUS_CHARS_GET_REQ stat_char_get;
1020 PI_CMD_CNTRS_GET_REQ cntrs_get;
1021 PI_CMD_CNTRS_SET_REQ cntrs_set;
1022 PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear;
1023 PI_CMD_ERROR_LOG_GET_REQ error_log_read;
1024 PI_CMD_SNMP_SET_REQ snmp_set;
1025 PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get;
1026 PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get;
1027 PI_CMD_SMT_MIB_SET_REQ smt_mib_set;
1028 PI_CMD_SMT_MIB_GET_REQ smt_mib_get;
1029 char pad[PI_CMD_REQ_K_SIZE_MAX];
1030 } PI_DMA_CMD_REQ;
1031
1032typedef union
1033 {
1034 PI_RSP_HEADER header;
1035 PI_CMD_START_RSP start;
1036 PI_CMD_FILTERS_SET_RSP filter_set;
1037 PI_CMD_FILTERS_GET_RSP filter_get;
1038 PI_CMD_CHARS_SET_RSP char_set;
1039 PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set;
1040 PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get;
1041 PI_CMD_STATUS_CHARS_GET_RSP stat_char_get;
1042 PI_CMD_CNTRS_GET_RSP cntrs_get;
1043 PI_CMD_CNTRS_SET_RSP cntrs_set;
1044 PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear;
1045 PI_CMD_ERROR_LOG_GET_RSP error_log_get;
1046 PI_CMD_SNMP_SET_RSP snmp_set;
1047 PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get;
1048 PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get;
1049 PI_CMD_SMT_MIB_SET_RSP smt_mib_set;
1050 PI_CMD_SMT_MIB_GET_RSP smt_mib_get;
1051 char pad[PI_CMD_RSP_K_SIZE_MAX];
1052 } PI_DMA_CMD_RSP;
1053
1054typedef union
1055 {
1056 PI_DMA_CMD_REQ request;
1057 PI_DMA_CMD_RSP response;
1058 } PI_DMA_CMD_BUFFER;
1059
1060
1061/* Define format of Consumer Block (resident in host memory) */
1062
1063typedef struct
1064 {
1065 volatile PI_UINT32 xmt_rcv_data;
1066 volatile PI_UINT32 reserved_1;
1067 volatile PI_UINT32 smt_host;
1068 volatile PI_UINT32 reserved_2;
1069 volatile PI_UINT32 unsol;
1070 volatile PI_UINT32 reserved_3;
1071 volatile PI_UINT32 cmd_rsp;
1072 volatile PI_UINT32 reserved_4;
1073 volatile PI_UINT32 cmd_req;
1074 volatile PI_UINT32 reserved_5;
1075 } PI_CONSUMER_BLOCK;
1076
1077#define PI_CONS_M_RCV_INDEX 0x000000FF
1078#define PI_CONS_M_XMT_INDEX 0x00FF0000
1079#define PI_CONS_V_RCV_INDEX 0
1080#define PI_CONS_V_XMT_INDEX 16
1081
1082/* Offsets into consumer block */
1083
1084#define PI_CONS_BLK_K_XMT_RCV 0x00
1085#define PI_CONS_BLK_K_SMT_HOST 0x08
1086#define PI_CONS_BLK_K_UNSOL 0x10
1087#define PI_CONS_BLK_K_CMD_RSP 0x18
1088#define PI_CONS_BLK_K_CMD_REQ 0x20
1089
1090/* Offsets into descriptor block */
1091
1092#define PI_DESCR_BLK_K_RCV_DATA 0x0000
1093#define PI_DESCR_BLK_K_XMT_DATA 0x0800
1094#define PI_DESCR_BLK_K_SMT_HOST 0x1000
1095#define PI_DESCR_BLK_K_UNSOL 0x1200
1096#define PI_DESCR_BLK_K_CMD_RSP 0x1280
1097#define PI_DESCR_BLK_K_CMD_REQ 0x1300
1098
1099/* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */
1100/* Note a field has been added for later versions of the PDQ to allow for */
1101/* finer granularity of the rcv buffer alignment. For backwards */
1102/* compatibility, the two bits (which allow the rcv buffer to be longword */
1103/* aligned) have been added at the MBZ bits. To support previous drivers, */
1104/* the MBZ definition is left intact. */
1105
1106typedef struct
1107 {
1108 PI_UINT32 long_0;
1109 PI_UINT32 long_1;
1110 } PI_RCV_DESCR;
1111
1112#define PI_RCV_DESCR_M_SOP 0x80000000
1113#define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000
1114#define PI_RCV_DESCR_M_MBZ 0x60000000
1115#define PI_RCV_DESCR_M_SEG_LEN 0x1F800000
1116#define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000
1117#define PI_RCV_DESCR_M_SEG_CNT 0x000F0000
1118#define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF
1119
1120#define PI_RCV_DESCR_V_SOP 31
1121#define PI_RCV_DESCR_V_SEG_LEN_LO 29
1122#define PI_RCV_DESCR_V_MBZ 29
1123#define PI_RCV_DESCR_V_SEG_LEN 23
1124#define PI_RCV_DESCR_V_SEG_LEN_HI 20
1125#define PI_RCV_DESCR_V_SEG_CNT 16
1126#define PI_RCV_DESCR_V_BUFF_HI 0
1127
1128/* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1129
1130typedef struct
1131 {
1132 PI_UINT32 long_0;
1133 PI_UINT32 long_1;
1134 } PI_XMT_DESCR;
1135
1136#define PI_XMT_DESCR_M_SOP 0x80000000
1137#define PI_XMT_DESCR_M_EOP 0x40000000
1138#define PI_XMT_DESCR_M_MBZ 0x20000000
1139#define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000
1140#define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF
1141
1142#define PI_XMT_DESCR_V_SOP 31
1143#define PI_XMT_DESCR_V_EOP 30
1144#define PI_XMT_DESCR_V_MBZ 29
1145#define PI_XMT_DESCR_V_SEG_LEN 16
1146#define PI_XMT_DESCR_V_BUFF_HI 0
1147
1148/* Define format of the Descriptor Block (resident in host memory) */
1149
1150#define PI_RCV_DATA_K_NUM_ENTRIES 256
1151#define PI_XMT_DATA_K_NUM_ENTRIES 256
1152#define PI_SMT_HOST_K_NUM_ENTRIES 64
1153#define PI_UNSOL_K_NUM_ENTRIES 16
1154#define PI_CMD_RSP_K_NUM_ENTRIES 16
1155#define PI_CMD_REQ_K_NUM_ENTRIES 16
1156
1157typedef struct
1158 {
1159 PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1160 PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1161 PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1162 PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES];
1163 PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1164 PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1165 } PI_DESCR_BLOCK;
1166
1167/* Define Port Registers - offsets from PDQ Base address */
1168
1169#define PI_PDQ_K_REG_PORT_RESET 0x00000000
1170#define PI_PDQ_K_REG_HOST_DATA 0x00000004
1171#define PI_PDQ_K_REG_PORT_CTRL 0x00000008
1172#define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C
1173#define PI_PDQ_K_REG_PORT_DATA_B 0x00000010
1174#define PI_PDQ_K_REG_PORT_STATUS 0x00000014
1175#define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018
1176#define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C
1177#define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020
1178#define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024
1179#define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028
1180#define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C
1181#define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030
1182#define PI_PDQ_K_REG_UNSOL_PROD 0x00000034
1183
1184/* Port Control Register - Command codes for primary commands */
1185
1186#define PI_PCTRL_M_CMD_ERROR 0x8000
1187#define PI_PCTRL_M_BLAST_FLASH 0x4000
1188#define PI_PCTRL_M_HALT 0x2000
1189#define PI_PCTRL_M_COPY_DATA 0x1000
1190#define PI_PCTRL_M_ERROR_LOG_START 0x0800
1191#define PI_PCTRL_M_ERROR_LOG_READ 0x0400
1192#define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200
1193#define PI_PCTRL_M_INIT 0x0100
1194#define PI_PCTRL_M_INIT_START 0x0080
1195#define PI_PCTRL_M_CONS_BLOCK 0x0040
1196#define PI_PCTRL_M_UNINIT 0x0020
1197#define PI_PCTRL_M_RING_MEMBER 0x0010
1198#define PI_PCTRL_M_MLA 0x0008
1199#define PI_PCTRL_M_FW_REV_READ 0x0004
1200#define PI_PCTRL_M_DEV_SPECIFIC 0x0002
1201#define PI_PCTRL_M_SUB_CMD 0x0001
1202
1203/* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1204
1205#define PI_SUB_CMD_K_LINK_UNINIT 0x0001
1206#define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002
1207#define PI_SUB_CMD_K_PDQ_REV_GET 0x0004
1208#define PI_SUB_CMD_K_HW_REV_GET 0x0008
1209
1210/* Define some Port Data B values */
1211
1212#define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */
1213#define PI_PDATA_B_DMA_BURST_SIZE_8 1
1214#define PI_PDATA_B_DMA_BURST_SIZE_16 2
1215#define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */
1216#define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16
1217
1218/* Port Data A Reset state */
1219
1220#define PI_PDATA_A_RESET_M_UPGRADE 0x00000001
1221#define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002
1222#define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004
1223
1224/* Read adapter MLA address port control command constants */
1225
1226#define PI_PDATA_A_MLA_K_LO 0
1227#define PI_PDATA_A_MLA_K_HI 1
1228
1229/* Byte Swap values for init command */
1230
1231#define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000
1232#define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC
1233#define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002
1234#define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001
1235
1236#define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13
1237#define PI_PDATA_A_INIT_V_RESERVED 3
1238#define PI_PDATA_A_INIT_V_BSWAP_DATA 1
1239#define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0
1240
1241/* Port Reset Register */
1242
1243#define PI_RESET_M_ASSERT_RESET 1
1244
1245/* Port Status register */
1246
1247#define PI_PSTATUS_V_RCV_DATA_PENDING 31
1248#define PI_PSTATUS_V_XMT_DATA_PENDING 30
1249#define PI_PSTATUS_V_SMT_HOST_PENDING 29
1250#define PI_PSTATUS_V_UNSOL_PENDING 28
1251#define PI_PSTATUS_V_CMD_RSP_PENDING 27
1252#define PI_PSTATUS_V_CMD_REQ_PENDING 26
1253#define PI_PSTATUS_V_TYPE_0_PENDING 25
1254#define PI_PSTATUS_V_RESERVED_1 16
1255#define PI_PSTATUS_V_RESERVED_2 11
1256#define PI_PSTATUS_V_STATE 8
1257#define PI_PSTATUS_V_HALT_ID 0
1258
1259#define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000
1260#define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000
1261#define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000
1262#define PI_PSTATUS_M_UNSOL_PENDING 0x10000000
1263#define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000
1264#define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000
1265#define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000
1266#define PI_PSTATUS_M_RESERVED_1 0x01FF0000
1267#define PI_PSTATUS_M_RESERVED_2 0x0000F800
1268#define PI_PSTATUS_M_STATE 0x00000700
1269#define PI_PSTATUS_M_HALT_ID 0x000000FF
1270
1271/* Define Halt Id's */
1272/* Do not insert into this list, only append. */
1273
1274#define PI_HALT_ID_K_SELFTEST_TIMEOUT 0
1275#define PI_HALT_ID_K_PARITY_ERROR 1
1276#define PI_HALT_ID_K_HOST_DIR_HALT 2
1277#define PI_HALT_ID_K_SW_FAULT 3
1278#define PI_HALT_ID_K_HW_FAULT 4
1279#define PI_HALT_ID_K_PC_TRACE 5
1280#define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */
1281#define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */
1282#define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */
1283
1284/* Host Interrupt Enable Register as seen by host */
1285
1286#define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */
1287#define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000
1288#define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */
1289#define PI_HOST_INT_M_UNSOL_ENB 0x20000000
1290#define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000
1291#define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000
1292#define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000
1293#define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */
1294#define PI_HOST_INT_M_1MS 0x00000080
1295#define PI_HOST_INT_M_20MS 0x00000040
1296#define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020
1297#define PI_HOST_INT_M_STATE_CHANGE 0x00000010
1298#define PI_HOST_INT_M_XMT_FLUSH 0x00000008
1299#define PI_HOST_INT_M_NXM 0x00000004
1300#define PI_HOST_INT_M_PM_PAR_ERR 0x00000002
1301#define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001
1302
1303#define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */
1304#define PI_HOST_INT_V_RCV_DATA_ENB 30
1305#define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */
1306#define PI_HOST_INT_V_UNSOL_ENB 28
1307#define PI_HOST_INT_V_CMD_RSP_ENB 27
1308#define PI_HOST_INT_V_CMD_REQ_ENB 26
1309#define PI_HOST_INT_V_TYPE_1_RESERVED 16
1310#define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */
1311#define PI_HOST_INT_V_1MS_ENB 7
1312#define PI_HOST_INT_V_20MS_ENB 6
1313#define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5
1314#define PI_HOST_INT_V_STATE_CHANGE_ENB 4
1315#define PI_HOST_INT_V_XMT_FLUSH_ENB 3
1316#define PI_HOST_INT_V_NXM_ENB 2
1317#define PI_HOST_INT_V_PM_PAR_ERR_ENB 1
1318#define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0
1319
1320#define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF
1321#define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000
1322#define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF
1323#define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F
1324
1325/* Type 0 Interrupt Status Register */
1326
1327#define PI_TYPE_0_STAT_M_1MS 0x00000080
1328#define PI_TYPE_0_STAT_M_20MS 0x00000040
1329#define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020
1330#define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010
1331#define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008
1332#define PI_TYPE_0_STAT_M_NXM 0x00000004
1333#define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002
1334#define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001
1335
1336#define PI_TYPE_0_STAT_V_1MS 7
1337#define PI_TYPE_0_STAT_V_20MS 6
1338#define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5
1339#define PI_TYPE_0_STAT_V_STATE_CHANGE 4
1340#define PI_TYPE_0_STAT_V_XMT_FLUSH 3
1341#define PI_TYPE_0_STAT_V_NXM 2
1342#define PI_TYPE_0_STAT_V_PM_PAR_ERR 1
1343#define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0
1344
1345/* Register definition structures are defined for both big and little endian systems */
1346
1347#ifndef BIG_ENDIAN
1348
1349/* Little endian format of Type 1 Producer register */
1350
1351typedef union
1352 {
1353 PI_UINT32 lword;
1354 struct
1355 {
1356 PI_UINT8 prod;
1357 PI_UINT8 comp;
1358 PI_UINT8 mbz_1;
1359 PI_UINT8 mbz_2;
1360 } index;
1361 } PI_TYPE_1_PROD_REG;
1362
1363/* Little endian format of Type 2 Producer register */
1364
1365typedef union
1366 {
1367 PI_UINT32 lword;
1368 struct
1369 {
1370 PI_UINT8 rcv_prod;
1371 PI_UINT8 xmt_prod;
1372 PI_UINT8 rcv_comp;
1373 PI_UINT8 xmt_comp;
1374 } index;
1375 } PI_TYPE_2_PROD_REG;
1376
1377/* Little endian format of Type 1 Consumer Block longword */
1378
1379typedef union
1380 {
1381 PI_UINT32 lword;
1382 struct
1383 {
1384 PI_UINT8 cons;
1385 PI_UINT8 res0;
1386 PI_UINT8 res1;
1387 PI_UINT8 res2;
1388 } index;
1389 } PI_TYPE_1_CONSUMER;
1390
1391/* Little endian format of Type 2 Consumer Block longword */
1392
1393typedef union
1394 {
1395 PI_UINT32 lword;
1396 struct
1397 {
1398 PI_UINT8 rcv_cons;
1399 PI_UINT8 res0;
1400 PI_UINT8 xmt_cons;
1401 PI_UINT8 res1;
1402 } index;
1403 } PI_TYPE_2_CONSUMER;
1404
1405#else
1406
1407/* Big endian format of Type 1 Producer register */
1408
1409typedef union
1410 {
1411 PI_UINT32 lword;
1412 struct
1413 {
1414 PI_UINT8 mbz_2;
1415 PI_UINT8 mbz_1;
1416 PI_UINT8 comp;
1417 PI_UINT8 prod;
1418 } index;
1419 } PI_TYPE_1_PROD_REG;
1420
1421/* Big endian format of Type 2 Producer register */
1422
1423typedef union
1424 {
1425 PI_UINT32 lword;
1426 struct
1427 {
1428 PI_UINT8 xmt_comp;
1429 PI_UINT8 rcv_comp;
1430 PI_UINT8 xmt_prod;
1431 PI_UINT8 rcv_prod;
1432 } index;
1433 } PI_TYPE_2_PROD_REG;
1434
1435/* Big endian format of Type 1 Consumer Block longword */
1436
1437typedef union
1438 {
1439 PI_UINT32 lword;
1440 struct
1441 {
1442 PI_UINT8 res2;
1443 PI_UINT8 res1;
1444 PI_UINT8 res0;
1445 PI_UINT8 cons;
1446 } index;
1447 } PI_TYPE_1_CONSUMER;
1448
1449/* Big endian format of Type 2 Consumer Block longword */
1450
1451typedef union
1452 {
1453 PI_UINT32 lword;
1454 struct
1455 {
1456 PI_UINT8 res1;
1457 PI_UINT8 xmt_cons;
1458 PI_UINT8 res0;
1459 PI_UINT8 rcv_cons;
1460 } index;
1461 } PI_TYPE_2_CONSUMER;
1462
1463#endif /* #ifndef BIG_ENDIAN */
1464
1465/* Define EISA controller register offsets */
1466
1467#define PI_ESIC_K_BURST_HOLDOFF 0x040
1468#define PI_ESIC_K_SLOT_ID 0xC80
1469#define PI_ESIC_K_SLOT_CNTRL 0xC84
1470#define PI_ESIC_K_MEM_ADD_CMP_0 0xC85
1471#define PI_ESIC_K_MEM_ADD_CMP_1 0xC86
1472#define PI_ESIC_K_MEM_ADD_CMP_2 0xC87
1473#define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88
1474#define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89
1475#define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A
1476#define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B
1477#define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C
1478#define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D
1479#define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E
1480#define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F
1481#define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90
1482#define PI_ESIC_K_IO_CMP_0_0 0xC91
1483#define PI_ESIC_K_IO_CMP_0_1 0xC92
1484#define PI_ESIC_K_IO_CMP_1_0 0xC93
1485#define PI_ESIC_K_IO_CMP_1_1 0xC94
1486#define PI_ESIC_K_IO_CMP_2_0 0xC95
1487#define PI_ESIC_K_IO_CMP_2_1 0xC96
1488#define PI_ESIC_K_IO_CMP_3_0 0xC97
1489#define PI_ESIC_K_IO_CMP_3_1 0xC98
1490#define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99
1491#define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A
1492#define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B
1493#define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C
1494#define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D
1495#define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E
1496#define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F
1497#define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0
1498#define PI_ESIC_K_MOD_CONFIG_1 0xCA1
1499#define PI_ESIC_K_MOD_CONFIG_2 0xCA2
1500#define PI_ESIC_K_MOD_CONFIG_3 0xCA3
1501#define PI_ESIC_K_MOD_CONFIG_4 0xCA4
1502#define PI_ESIC_K_MOD_CONFIG_5 0xCA5
1503#define PI_ESIC_K_MOD_CONFIG_6 0xCA6
1504#define PI_ESIC_K_MOD_CONFIG_7 0xCA7
1505#define PI_ESIC_K_DIP_SWITCH 0xCA8
1506#define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9
1507#define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA
1508#define PI_ESIC_K_DMA_CONFIG 0xCAB
1509#define PI_ESIC_K_INPUT_PORT 0xCAC
1510#define PI_ESIC_K_OUTPUT_PORT 0xCAD
1511#define PI_ESIC_K_FUNCTION_CNTRL 0xCAE
1512#define PI_ESIC_K_CSR_IO_LEN PI_ESIC_K_FUNCTION_CNTRL+1 /* always last reg + 1 */
1513
1514/* Define the value all drivers must write to the function control register. */
1515
1516#define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB 0x03
1517
1518/* Define the bits in the slot control register. */
1519
1520#define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */
1521#define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */
1522#define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */
1523
1524/* Define the bits in the burst holdoff register. */
1525
1526#define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC
1527#define PI_BURST_HOLDOFF_M_RESERVED 0x02
1528#define PI_BURST_HOLDOFF_M_MEM_MAP 0x01
1529
1530#define PI_BURST_HOLDOFF_V_HOLDOFF 2
1531#define PI_BURST_HOLDOFF_V_RESERVED 1
1532#define PI_BURST_HOLDOFF_V_MEM_MAP 0
1533
1534/*
1535 * Define the fields in the IO Compare registers.
1536 * The driver must initialize the slot field with the slot ID shifted by the
1537 * amount shown below.
1538 */
1539
1540#define PI_IO_CMP_V_SLOT 4
1541
1542/* Define the fields in the Interrupt Channel Configuration and Status reg */
1543
1544#define PI_CONFIG_STAT_0_M_PEND 0x80
1545#define PI_CONFIG_STAT_0_M_RES_1 0x40
1546#define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20
1547#define PI_CONFIG_STAT_0_M_IREQ_IN 0x10
1548#define PI_CONFIG_STAT_0_M_INT_ENB 0x08
1549#define PI_CONFIG_STAT_0_M_RES_0 0x04
1550#define PI_CONFIG_STAT_0_M_IRQ 0x03
1551
1552#define PI_CONFIG_STAT_0_V_PEND 7
1553#define PI_CONFIG_STAT_0_V_RES_1 6
1554#define PI_CONFIG_STAT_0_V_IREQ_OUT 5
1555#define PI_CONFIG_STAT_0_V_IREQ_IN 4
1556#define PI_CONFIG_STAT_0_V_INT_ENB 3
1557#define PI_CONFIG_STAT_0_V_RES_0 2
1558#define PI_CONFIG_STAT_0_V_IRQ 0
1559
1560#define PI_CONFIG_STAT_0_IRQ_K_9 0
1561#define PI_CONFIG_STAT_0_IRQ_K_10 1
1562#define PI_CONFIG_STAT_0_IRQ_K_11 2
1563#define PI_CONFIG_STAT_0_IRQ_K_15 3
1564
1565/* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1566
1567#define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */
1568#define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */
1569#define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */
1570#define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */
1571
1572/**********************************************/
1573/* Digital PFI Specification v1.0 Definitions */
1574/**********************************************/
1575
1576/* PCI Configuration Space Constants */
1577
1578#define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */
1579#define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */
1580#define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */
1581#define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */
1582#define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */
1583
1584/* PFI Register Offsets (starting at PDQ Register Base Address) */
1585
1586#define PFI_K_REG_RESERVED_0 0X00000038
1587#define PFI_K_REG_RESERVED_1 0X0000003C
1588#define PFI_K_REG_MODE_CTRL 0X00000040
1589#define PFI_K_REG_STATUS 0X00000044
1590#define PFI_K_REG_FIFO_WRITE 0X00000048
1591#define PFI_K_REG_FIFO_READ 0X0000004C
1592
1593/* PFI Mode Control Register Constants */
1594
1595#define PFI_MODE_M_RESERVED 0XFFFFFFF0
1596#define PFI_MODE_M_TGT_ABORT_ENB 0X00000008
1597#define PFI_MODE_M_PDQ_INT_ENB 0X00000004
1598#define PFI_MODE_M_PFI_INT_ENB 0X00000002
1599#define PFI_MODE_M_DMA_ENB 0X00000001
1600
1601#define PFI_MODE_V_RESERVED 4
1602#define PFI_MODE_V_TGT_ABORT_ENB 3
1603#define PFI_MODE_V_PDQ_INT_ENB 2
1604#define PFI_MODE_V_PFI_INT_ENB 1
1605#define PFI_MODE_V_DMA_ENB 0
1606
1607#define PFI_MODE_K_ALL_DISABLE 0X00000000
1608
1609/* PFI Status Register Constants */
1610
1611#define PFI_STATUS_M_RESERVED 0XFFFFFFC0
1612#define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */
1613#define PFI_STATUS_M_PDQ_INT 0X00000010
1614#define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008
1615#define PFI_STATUS_M_FIFO_FULL 0X00000004
1616#define PFI_STATUS_M_FIFO_EMPTY 0X00000002
1617#define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001
1618
1619#define PFI_STATUS_V_RESERVED 6
1620#define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */
1621#define PFI_STATUS_V_PDQ_INT 4
1622#define PFI_STATUS_V_PDQ_DMA_ABORT 3
1623#define PFI_STATUS_V_FIFO_FULL 2
1624#define PFI_STATUS_V_FIFO_EMPTY 1
1625#define PFI_STATUS_V_DMA_IN_PROGRESS 0
1626
1627#define DFX_MAX_EISA_SLOTS 16 /* maximum number of EISA slots to scan */
1628#define DFX_MAX_NUM_BOARDS 8 /* maximum number of adapters supported */
1629
1630#define DFX_BUS_TYPE_PCI 0 /* type code for DEC FDDIcontroller/PCI */
1631#define DFX_BUS_TYPE_EISA 1 /* type code for DEC FDDIcontroller/EISA */
1632
1633#define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */
1634#define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */
1635#define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */
1636#define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */
1637
1638/* Driver routine status (return) codes */
1639
1640#define DFX_K_SUCCESS 0 /* routine succeeded */
1641#define DFX_K_FAILURE 1 /* routine failed */
1642#define DFX_K_OUTSTATE 2 /* bad state for command */
1643#define DFX_K_HW_TIMEOUT 3 /* command timed out */
1644
1645/* Define LLC host receive buffer min/max/default values */
1646
1647#define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */
1648#define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */
1649#define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */
1650
1651/* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
1652
1653#define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */
1654#define RCV_BUFF_K_PADDING 4 /* three null bytes */
1655#define RCV_BUFF_K_FC 7 /* one byte frame control */
1656#define RCV_BUFF_K_DA 8 /* six byte destination address */
1657#define RCV_BUFF_K_SA 14 /* six byte source address */
1658#define RCV_BUFF_K_DATA 20 /* offset to start of packet data */
1659
1660/* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
1661
1662#define XMT_BUFF_K_FC 0 /* one byte frame control */
1663#define XMT_BUFF_K_DA 1 /* six byte destination address */
1664#define XMT_BUFF_K_SA 7 /* six byte source address */
1665#define XMT_BUFF_K_DATA 13 /* offset to start of packet data */
1666
1667/* Macro for checking a "value" is within a specific range */
1668
1669#define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
1670
1671/* Only execute special print call when debug driver was built */
1672
1673#ifdef DEFXX_DEBUG
1674#define DBG_printk(args...) printk(## args)
1675#else
1676#define DBG_printk(args...)
1677#endif
1678
1679/* Define constants for masking/unmasking interrupts */
1680
1681#define DFX_MASK_INTERRUPTS 1
1682#define DFX_UNMASK_INTERRUPTS 0
1683
1684/* Define structure for driver transmit descriptor block */
1685
1686typedef struct
1687 {
1688 struct sk_buff *p_skb; /* ptr to skb */
1689 } XMT_DRIVER_DESCR;
1690
1691typedef struct DFX_board_tag
1692 {
1693 /* Keep virtual and physical pointers to locked, physically contiguous memory */
1694
1695 char *kmalloced; /* pci_free_consistent this on unload */
1696 dma_addr_t kmalloced_dma;
1697 /* DMA handle for the above */
1698 PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */
1699 dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */
1700 PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */
1701 dma_addr_t cmd_req_phys; /* Command request buffer phys address */
1702 PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */
1703 dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */
1704 char *rcv_block_virt; /* LLC host receive queue buf blk virt */
1705 dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */
1706 PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */
1707 dma_addr_t cons_block_phys; /* PDQ consumer block phys address */
1708
1709 /* Keep local copies of Type 1 and Type 2 register data */
1710
1711 PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */
1712 PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */
1713 PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */
1714
1715 /* Storage for unicast and multicast address entries in adapter CAM */
1716
1717 u8 uc_table[1*FDDI_K_ALEN];
1718 u32 uc_count; /* number of unicast addresses */
1719 u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
1720 u32 mc_count; /* number of multicast addresses */
1721
1722 /* Current packet filter settings */
1723
1724 u32 ind_group_prom; /* LLC individual & group frame prom mode */
1725 u32 group_prom; /* LLC group (multicast) frame prom mode */
1726
1727 /* Link available flag needed to determine whether to drop outgoing packet requests */
1728
1729 u32 link_available; /* is link available? */
1730
1731 /* Resources to indicate reset type when resetting adapter */
1732
1733 u32 reset_type; /* skip or rerun diagnostics */
1734
1735 /* Store pointers to receive buffers for queue processing code */
1736
1737 char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
1738
1739 /* Store pointers to transmit buffers for transmit completion code */
1740
1741 XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
1742
1743 /* Transmit spinlocks */
1744
1745 spinlock_t lock;
1746
1747 /* Store device, bus-specific, and parameter information for this adapter */
1748
1749 struct net_device *dev; /* pointer to device structure */
1750 struct net_device *next;
1751 u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */
1752 u16 base_addr; /* base I/O address (same as dev->base_addr) */
1753 struct pci_dev * pci_dev;
1754 u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */
1755 u32 req_ttrt; /* requested TTRT value (in 80ns units) */
1756 u32 burst_size; /* adapter burst size (enumerated) */
1757 u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */
1758 u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */
1759
1760 /* Common FDDI statistics structure and private counters */
1761
1762 struct fddi_statistics stats;
1763
1764 u32 rcv_discards;
1765 u32 rcv_crc_errors;
1766 u32 rcv_frame_status_errors;
1767 u32 rcv_length_errors;
1768 u32 rcv_total_frames;
1769 u32 rcv_multicast_frames;
1770 u32 rcv_total_bytes;
1771
1772 u32 xmt_discards;
1773 u32 xmt_length_errors;
1774 u32 xmt_total_frames;
1775 u32 xmt_total_bytes;
1776 } DFX_board_t;
1777
1778#endif /* #ifndef _DEFXX_H_ */