tjh.dev
Linux kernel mirror (for testing)
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linux
1/*
2 * arch/ppc/syslib/cpc700.h
3 *
4 * Header file for IBM CPC700 Host Bridge, et. al.
5 *
6 * Author: Mark A. Greer
7 * mgreer@mvista.com
8 *
9 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15/*
16 * This file contains the defines and macros for the IBM CPC700 host bridge,
17 * memory controller, PIC, UARTs, IIC, and Timers.
18 */
19
20#ifndef __PPC_SYSLIB_CPC700_H__
21#define __PPC_SYSLIB_CPC700_H__
22
23#include <linux/stddef.h>
24#include <linux/types.h>
25#include <linux/init.h>
26
27/* XXX no barriers? not even any volatiles? -- paulus */
28#define CPC700_OUT_32(a,d) (*(u_int *)a = d)
29#define CPC700_IN_32(a) (*(u_int *)a)
30
31/*
32 * PCI Section
33 */
34#define CPC700_PCI_CONFIG_ADDR 0xfec00000
35#define CPC700_PCI_CONFIG_DATA 0xfec00004
36
37/* CPU -> PCI memory window 0 */
38#define CPC700_PMM0_LOCAL 0xff400000 /* CPU physical addr */
39#define CPC700_PMM0_MASK_ATTR 0xff400004 /* size and attrs */
40#define CPC700_PMM0_PCI_LOW 0xff400008 /* PCI addr, low word */
41#define CPC700_PMM0_PCI_HIGH 0xff40000c /* PCI addr, high wd */
42/* CPU -> PCI memory window 1 */
43#define CPC700_PMM1_LOCAL 0xff400010
44#define CPC700_PMM1_MASK_ATTR 0xff400014
45#define CPC700_PMM1_PCI_LOW 0xff400018
46#define CPC700_PMM1_PCI_HIGH 0xff40001c
47/* CPU -> PCI memory window 2 */
48#define CPC700_PMM2_LOCAL 0xff400020
49#define CPC700_PMM2_MASK_ATTR 0xff400024
50#define CPC700_PMM2_PCI_LOW 0xff400028
51#define CPC700_PMM2_PCI_HIGH 0xff40002c
52/* PCI memory -> CPU window 1 */
53#define CPC700_PTM1_MEMSIZE 0xff400030 /* window size */
54#define CPC700_PTM1_LOCAL 0xff400034 /* CPU phys addr */
55/* PCI memory -> CPU window 2 */
56#define CPC700_PTM2_MEMSIZE 0xff400038 /* size and enable */
57#define CPC700_PTM2_LOCAL 0xff40003c
58
59/*
60 * PIC Section
61 *
62 * IBM calls the CPC700's programmable interrupt controller the Universal
63 * Interrupt Controller or UIC.
64 */
65
66/*
67 * UIC Register Addresses.
68 */
69#define CPC700_UIC_UICSR 0xff500880 /* Status Reg (Rd/Clr)*/
70#define CPC700_UIC_UICSRS 0xff500884 /* Status Reg (Set) */
71#define CPC700_UIC_UICER 0xff500888 /* Enable Reg */
72#define CPC700_UIC_UICCR 0xff50088c /* Critical Reg */
73#define CPC700_UIC_UICPR 0xff500890 /* Polarity Reg */
74#define CPC700_UIC_UICTR 0xff500894 /* Trigger Reg */
75#define CPC700_UIC_UICMSR 0xff500898 /* Masked Status Reg */
76#define CPC700_UIC_UICVR 0xff50089c /* Vector Reg */
77#define CPC700_UIC_UICVCR 0xff5008a0 /* Vector Config Reg */
78
79#define CPC700_UIC_UICER_ENABLE 0x00000001 /* Enable an IRQ */
80
81#define CPC700_UIC_UICVCR_31_HI 0x00000000 /* IRQ 31 hi priority */
82#define CPC700_UIC_UICVCR_0_HI 0x00000001 /* IRQ 0 hi priority */
83#define CPC700_UIC_UICVCR_BASE_MASK 0xfffffffc
84#define CPC700_UIC_UICVCR_ORDER_MASK 0x00000001
85
86/* Specify value of a bit for an IRQ. */
87#define CPC700_UIC_IRQ_BIT(i) ((0x00000001) << (31 - (i)))
88
89/*
90 * UIC Exports...
91 */
92extern struct hw_interrupt_type cpc700_pic;
93extern unsigned int cpc700_irq_assigns[32][2];
94
95extern void __init cpc700_init_IRQ(void);
96extern int cpc700_get_irq(struct pt_regs *);
97
98#endif /* __PPC_SYSLIB_CPC700_H__ */