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Linux kernel mirror (for testing)
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linux
1/* Definitions for Xtensa instructions, types, and protos. */
2
3/*
4 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2.1 of the GNU Lesser General Public
8 * License as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it would be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Further, this software is distributed without any warranty that it is
15 * free of the rightful claim of any third person regarding infringement
16 * or the like. Any license provided herein, whether implied or
17 * otherwise, applies only to this software file. Patent licenses, if
18 * any, provided herein do not apply to combinations of this program with
19 * other software, or any other product whatsoever.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this program; if not, write the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
24 * USA.
25 */
26
27/* Do not modify. This is automatically generated.*/
28
29#ifndef _XTENSA_BASE_HEADER
30#define _XTENSA_BASE_HEADER
31
32#ifdef __XTENSA__
33#if defined(__GNUC__) && !defined(__XCC__)
34
35#define L8UI_ASM(arr, ars, imm) { \
36 __asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
37}
38
39#define XT_L8UI(ars, imm) \
40({ \
41 unsigned char _arr; \
42 const unsigned char *_ars = ars; \
43 L8UI_ASM(_arr, _ars, imm); \
44 _arr; \
45})
46
47#define L16UI_ASM(arr, ars, imm) { \
48 __asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
49}
50
51#define XT_L16UI(ars, imm) \
52({ \
53 unsigned short _arr; \
54 const unsigned short *_ars = ars; \
55 L16UI_ASM(_arr, _ars, imm); \
56 _arr; \
57})
58
59#define L16SI_ASM(arr, ars, imm) {\
60 __asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
61}
62
63#define XT_L16SI(ars, imm) \
64({ \
65 signed short _arr; \
66 const signed short *_ars = ars; \
67 L16SI_ASM(_arr, _ars, imm); \
68 _arr; \
69})
70
71#define L32I_ASM(arr, ars, imm) { \
72 __asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
73}
74
75#define XT_L32I(ars, imm) \
76({ \
77 unsigned _arr; \
78 const unsigned *_ars = ars; \
79 L32I_ASM(_arr, _ars, imm); \
80 _arr; \
81})
82
83#define S8I_ASM(arr, ars, imm) {\
84 __asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
85}
86
87#define XT_S8I(arr, ars, imm) \
88({ \
89 signed char _arr = arr; \
90 const signed char *_ars = ars; \
91 S8I_ASM(_arr, _ars, imm); \
92})
93
94#define S16I_ASM(arr, ars, imm) {\
95 __asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
96}
97
98#define XT_S16I(arr, ars, imm) \
99({ \
100 signed short _arr = arr; \
101 const signed short *_ars = ars; \
102 S16I_ASM(_arr, _ars, imm); \
103})
104
105#define S32I_ASM(arr, ars, imm) { \
106 __asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
107}
108
109#define XT_S32I(arr, ars, imm) \
110({ \
111 signed int _arr = arr; \
112 const signed int *_ars = ars; \
113 S32I_ASM(_arr, _ars, imm); \
114})
115
116#define ADDI_ASM(art, ars, imm) {\
117 __asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
118}
119
120#define XT_ADDI(ars, imm) \
121({ \
122 unsigned _art; \
123 unsigned _ars = ars; \
124 ADDI_ASM(_art, _ars, imm); \
125 _art; \
126})
127
128#define ABS_ASM(arr, art) {\
129 __asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
130}
131
132#define XT_ABS(art) \
133({ \
134 unsigned _arr; \
135 signed _art = art; \
136 ABS_ASM(_arr, _art); \
137 _arr; \
138})
139
140/* Note: In the following macros that reference SAR, the magic "state"
141 register is used to capture the dependency on SAR. This is because
142 SAR is a 5-bit register and thus there are no C types that can be
143 used to represent it. It doesn't appear that the SAR register is
144 even relevant to GCC, but it is marked as "clobbered" just in
145 case. */
146
147#define SRC_ASM(arr, ars, art) {\
148 register int _xt_sar __asm__ ("state"); \
149 __asm__ ("src %0, %1, %2" \
150 : "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
151}
152
153#define XT_SRC(ars, art) \
154({ \
155 unsigned _arr; \
156 unsigned _ars = ars; \
157 unsigned _art = art; \
158 SRC_ASM(_arr, _ars, _art); \
159 _arr; \
160})
161
162#define SSR_ASM(ars) {\
163 register int _xt_sar __asm__ ("state"); \
164 __asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
165}
166
167#define XT_SSR(ars) \
168({ \
169 unsigned _ars = ars; \
170 SSR_ASM(_ars); \
171})
172
173#define SSL_ASM(ars) {\
174 register int _xt_sar __asm__ ("state"); \
175 __asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
176}
177
178#define XT_SSL(ars) \
179({ \
180 unsigned _ars = ars; \
181 SSL_ASM(_ars); \
182})
183
184#define SSA8B_ASM(ars) {\
185 register int _xt_sar __asm__ ("state"); \
186 __asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
187}
188
189#define XT_SSA8B(ars) \
190({ \
191 unsigned _ars = ars; \
192 SSA8B_ASM(_ars); \
193})
194
195#define SSA8L_ASM(ars) {\
196 register int _xt_sar __asm__ ("state"); \
197 __asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
198}
199
200#define XT_SSA8L(ars) \
201({ \
202 unsigned _ars = ars; \
203 SSA8L_ASM(_ars); \
204})
205
206#define SSAI_ASM(imm) {\
207 register int _xt_sar __asm__ ("state"); \
208 __asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
209}
210
211#define XT_SSAI(imm) \
212({ \
213 SSAI_ASM(imm); \
214})
215
216
217
218
219
220
221
222
223#endif /* __GNUC__ && !__XCC__ */
224
225#ifdef __XCC__
226
227/* Core load/store instructions */
228extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
229extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
230extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
231extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
232extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
233extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
234extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
235
236#define XT_L8UI _TIE_L8UI
237#define XT_L16UI _TIE_L16UI
238#define XT_L16SI _TIE_L16SI
239#define XT_L32I _TIE_L32I
240#define XT_S8I _TIE_S8I
241#define XT_S16I _TIE_S16I
242#define XT_S32I _TIE_S32I
243
244/* Add-immediate instruction */
245extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
246#define XT_ADDI _TIE_ADDI
247
248/* Absolute value instruction */
249extern unsigned _TIE_ABS(int art);
250#define XT_ABS _TIE_ABS
251
252/* funnel shift instructions */
253extern unsigned _TIE_SRC(unsigned ars, unsigned art);
254#define XT_SRC _TIE_SRC
255extern void _TIE_SSR(unsigned ars);
256#define XT_SSR _TIE_SSR
257extern void _TIE_SSL(unsigned ars);
258#define XT_SSL _TIE_SSL
259extern void _TIE_SSA8B(unsigned ars);
260#define XT_SSA8B _TIE_SSA8B
261extern void _TIE_SSA8L(unsigned ars);
262#define XT_SSA8L _TIE_SSA8L
263extern void _TIE_SSAI(immediate imm);
264#define XT_SSAI _TIE_SSAI
265
266
267#endif /* __XCC__ */
268
269#endif /* __XTENSA__ */
270#endif /* !_XTENSA_BASE_HEADER */