Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1
2/*
3 * snull.h -- definitions for the network module
4 *
5 * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet
6 * Copyright (C) 2001 O'Reilly & Associates
7 *
8 * The source code in this file can be freely used, adapted,
9 * and redistributed in source or binary form, so long as an
10 * acknowledgment appears in derived source files. The citation
11 * should list that the code comes from the book "Linux Device
12 * Drivers" by Alessandro Rubini and Jonathan Corbet, published
13 * by O'Reilly & Associates. No warranty is attached;
14 * we cannot take responsibility for errors or fitness for use.
15 */
16
17/* version dependencies have been confined to a separate file */
18
19/* Tunable parameters */
20#define TX_RING_ENTRIES 64 /* 64-512?*/
21
22#define RX_RING_ENTRIES 16 /* Do not change */
23/* Internal constants */
24#define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
25#define RX_BUFFER_SIZE 1546 /* ethenet packet size */
26#define METH_RX_BUFF_SIZE 4096
27#define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
28#define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
29#define RX_BUCKET_SIZE 256
30
31#undef BIT
32#define BIT(x) (1UL << (x))
33
34/* For more detailed explanations of what each field menas,
35 see Nick's great comments to #defines below (or docs, if
36 you are lucky enough toget hold of them :)*/
37
38/* tx status vector is written over tx command header upon
39 dma completion. */
40
41typedef struct tx_status_vector {
42 u64 sent:1; /* always set to 1...*/
43 u64 pad0:34;/* always set to 0 */
44 u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/
45 u64 col_retry_cnt:4; /*collision retry count*/
46 u64 len:16; /*Transmit length in bytes*/
47} tx_status_vector;
48
49/*
50 * Each packet is 128 bytes long.
51 * It consists of header, 0-3 concatination
52 * buffer pointers and up to 120 data bytes.
53 */
54typedef struct tx_packet_hdr {
55 u64 pad1:36; /*should be filled with 0 */
56 u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/
57 cat_ptr2_valid:1,
58 cat_ptr1_valid:1;
59 u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
60 u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/
61 u64 data_offset:7; /*Starting byte offset in ring data block*/
62 u64 data_len:16; /*Length of valid data in bytes-1*/
63} tx_packet_hdr;
64typedef union tx_cat_ptr {
65 struct {
66 u64 pad2:16; /* should be 0 */
67 u64 len:16; /*length of buffer data - 1*/
68 u64 start_addr:29; /*Physical starting address*/
69 u64 pad1:3; /* should be zero */
70 } form;
71 u64 raw;
72} tx_cat_ptr;
73
74typedef struct tx_packet {
75 union {
76 tx_packet_hdr header;
77 tx_status_vector res;
78 u64 raw;
79 }header;
80 union {
81 tx_cat_ptr cat_buf[3];
82 char dt[120];
83 } data;
84} tx_packet;
85
86typedef union rx_status_vector {
87 volatile struct {
88 u64 pad1:1;/*fill it with ones*/
89 u64 pad2:15;/*fill with 0*/
90 u64 ip_chk_sum:16;
91 u64 seq_num:5;
92 u64 mac_addr_match:1;
93 u64 mcast_addr_match:1;
94 u64 carrier_event_seen:1;
95 u64 bad_packet:1;
96 u64 long_event_seen:1;
97 u64 invalid_preamble:1;
98 u64 broadcast:1;
99 u64 multicast:1;
100 u64 crc_error:1;
101 u64 huh:1;/*???*/
102 u64 rx_code_violation:1;
103 u64 rx_len:16;
104 } parsed;
105 volatile u64 raw;
106} rx_status_vector;
107
108typedef struct rx_packet {
109 rx_status_vector status;
110 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
111 u16 pad2;
112 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
113} rx_packet;
114
115#define TX_INFO_RPTR 0x00FF0000
116#define TX_INFO_WPTR 0x000000FF
117
118 /* Bits in METH_MAC */
119
120#define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
121#define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
122#define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
123 /* selects ignored */
124#define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
125#define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
126 /* Note: when loopback is set this bit becomes collision control. Setting this bit will */
127 /* cause a collision to be reported. */
128
129 /* Bits 5 and 6 are used to determine the the Destination address filter mode */
130#define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */
131#define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */
132#define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
133#define METH_PROMISC 0x60 /* 11: Promiscious mode */
134
135#define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
136
137#define METH_MAC_IPG 0x1ffff00
138
139#define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
140 /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
141 /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
142 /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */
143 /* per increment for 10BaseT */
144
145 /* Bits 15 through 21 are used to determine IPGR1 */
146
147 /* Bits 22 through 28 are used to determine IPGR2 */
148
149#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
150 /* 000: Inital revision */
151 /* 001: First revision, Improved TX concatenation */
152
153
154/* DMA control bits */
155#define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
156#define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
157
158#define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
159#define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
160#define METH_DMA_RX_EN BIT(15) /* Enable RX */
161#define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
162
163/* RX FIFO MCL Info bits */
164#define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf)
165#define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf)
166#define METH_RX_FIFO_DEPTH(x) ((x)&0x1f)
167
168/* RX status bits */
169
170#define METH_RX_ST_VALID BIT(63)
171#define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
172#define METH_RX_ST_DRBL_NBL BIT(17)
173#define METH_RX_ST_CRC_ERR BIT(18)
174#define METH_RX_ST_MCAST_PKT BIT(19)
175#define METH_RX_ST_BCAST_PKT BIT(20)
176#define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
177#define METH_RX_ST_LONG_EVT_SEEN BIT(22)
178#define METH_RX_ST_BAD_PACKET BIT(23)
179#define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
180#define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
181#define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
182
183#define METH_RX_STATUS_ERRORS \
184 ( \
185 METH_RX_ST_RCV_CODE_VIOLATION| \
186 METH_RX_ST_CRC_ERR| \
187 METH_RX_ST_INV_PREAMBLE_CTX| \
188 METH_RX_ST_LONG_EVT_SEEN| \
189 METH_RX_ST_BAD_PACKET| \
190 METH_RX_ST_CARRIER_EVT_SEEN \
191 )
192 /* Bits in METH_INT */
193 /* Write _1_ to corresponding bit to clear */
194#define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
195#define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
196 /* 1: A TX message had the INT request bit set, the packet has been sent. */
197#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */
198#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
199 /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */
200#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
201#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
202#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
203#define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
204
205/*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
206#define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
207
208 /* Bits 13 through 15 are always 0. */
209
210#define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
211
212#define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */
213
214 /* top of the queue */
215
216#define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \
217 METH_INT_MEM_ERROR| \
218 METH_INT_TX_ABORT| \
219 METH_INT_RX_OVERFLOW| \
220 METH_INT_RX_UNDERFLOW)
221
222#define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
223
224/* TX status bits */
225#define METH_TX_ST_DONE BIT(63) /* TX complete */
226#define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */
227#define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */
228#define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */
229#define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */
230#define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */
231#define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */
232
233
234/* Tx command header bits */
235#define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
236
237/* Phy MDIO interface busy flag */
238#define MDIO_BUSY BIT(16)
239#define MDIO_DATA_MASK 0xFFFF
240/* PHY defines */
241#define PHY_QS6612X 0x0181441 /* Quality TX */
242#define PHY_ICS1889 0x0015F41 /* ICS FX */
243#define PHY_ICS1890 0x0015F42 /* ICS TX */
244#define PHY_DP83840 0x20005C0 /* National TX */
245
246#define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)