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1/* 2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware 3 * 4 * Copyright 2004 Red Hat, Inc. 5 * 6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/pci.h> 17#include <linux/slab.h> 18#include <linux/spinlock.h> 19#include <linux/blkdev.h> 20#include <linux/sched.h> 21#include <linux/devfs_fs_kernel.h> 22#include <linux/interrupt.h> 23#include <linux/compiler.h> 24#include <linux/workqueue.h> 25#include <linux/bitops.h> 26#include <linux/delay.h> 27#include <linux/time.h> 28#include <linux/hdreg.h> 29#include <linux/dma-mapping.h> 30#include <asm/io.h> 31#include <asm/semaphore.h> 32#include <asm/uaccess.h> 33 34MODULE_AUTHOR("Jeff Garzik"); 35MODULE_LICENSE("GPL"); 36MODULE_DESCRIPTION("Promise SATA SX8 block driver"); 37 38#if 0 39#define CARM_DEBUG 40#define CARM_VERBOSE_DEBUG 41#else 42#undef CARM_DEBUG 43#undef CARM_VERBOSE_DEBUG 44#endif 45#undef CARM_NDEBUG 46 47#define DRV_NAME "sx8" 48#define DRV_VERSION "0.8" 49#define PFX DRV_NAME ": " 50 51#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) 52 53/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ 54#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) 55#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) 56#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) 57 58/* note: prints function name for you */ 59#ifdef CARM_DEBUG 60#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 61#ifdef CARM_VERBOSE_DEBUG 62#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 63#else 64#define VPRINTK(fmt, args...) 65#endif /* CARM_VERBOSE_DEBUG */ 66#else 67#define DPRINTK(fmt, args...) 68#define VPRINTK(fmt, args...) 69#endif /* CARM_DEBUG */ 70 71#ifdef CARM_NDEBUG 72#define assert(expr) 73#else 74#define assert(expr) \ 75 if(unlikely(!(expr))) { \ 76 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ 77 #expr,__FILE__,__FUNCTION__,__LINE__); \ 78 } 79#endif 80 81/* defines only for the constants which don't work well as enums */ 82struct carm_host; 83 84enum { 85 /* adapter-wide limits */ 86 CARM_MAX_PORTS = 8, 87 CARM_SHM_SIZE = (4096 << 7), 88 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, 89 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, 90 91 /* command message queue limits */ 92 CARM_MAX_REQ = 64, /* max command msgs per host */ 93 CARM_MAX_Q = 1, /* one command at a time */ 94 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ 95 96 /* S/G limits, host-wide and per-request */ 97 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ 98 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ 99 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ 100 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ 101 102 /* hardware registers */ 103 CARM_IHQP = 0x1c, 104 CARM_INT_STAT = 0x10, /* interrupt status */ 105 CARM_INT_MASK = 0x14, /* interrupt mask */ 106 CARM_HMUC = 0x18, /* host message unit control */ 107 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ 108 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ 109 RBUF_BYTE_SZ = 0x28, 110 CARM_RESP_IDX = 0x2c, 111 CARM_CMS0 = 0x30, /* command message size reg 0 */ 112 CARM_LMUC = 0x48, 113 CARM_HMPHA = 0x6c, 114 CARM_INITC = 0xb5, 115 116 /* bits in CARM_INT_{STAT,MASK} */ 117 INT_RESERVED = 0xfffffff0, 118 INT_WATCHDOG = (1 << 3), /* watchdog timer */ 119 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ 120 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ 121 INT_RESPONSE = (1 << 0), /* response msg available */ 122 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, 123 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | 124 INT_RESPONSE, 125 126 /* command messages, and related register bits */ 127 CARM_HAVE_RESP = 0x01, 128 CARM_MSG_READ = 1, 129 CARM_MSG_WRITE = 2, 130 CARM_MSG_VERIFY = 3, 131 CARM_MSG_GET_CAPACITY = 4, 132 CARM_MSG_FLUSH = 5, 133 CARM_MSG_IOCTL = 6, 134 CARM_MSG_ARRAY = 8, 135 CARM_MSG_MISC = 9, 136 CARM_CME = (1 << 2), 137 CARM_RME = (1 << 1), 138 CARM_WZBC = (1 << 0), 139 CARM_RMI = (1 << 0), 140 CARM_Q_FULL = (1 << 3), 141 CARM_MSG_SIZE = 288, 142 CARM_Q_LEN = 48, 143 144 /* CARM_MSG_IOCTL messages */ 145 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ 146 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ 147 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ 148 149 IOC_SCAN_CHAN_NODEV = 0x1f, 150 IOC_SCAN_CHAN_OFFSET = 0x40, 151 152 /* CARM_MSG_ARRAY messages */ 153 CARM_ARRAY_INFO = 0, 154 155 ARRAY_NO_EXIST = (1 << 31), 156 157 /* response messages */ 158 RMSG_SZ = 8, /* sizeof(struct carm_response) */ 159 RMSG_Q_LEN = 48, /* resp. msg list length */ 160 RMSG_OK = 1, /* bit indicating msg was successful */ 161 /* length of entire resp. msg buffer */ 162 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, 163 164 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ 165 166 /* CARM_MSG_MISC messages */ 167 MISC_GET_FW_VER = 2, 168 MISC_ALLOC_MEM = 3, 169 MISC_SET_TIME = 5, 170 171 /* MISC_GET_FW_VER feature bits */ 172 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ 173 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ 174 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ 175 176 /* carm_host flags */ 177 FL_NON_RAID = FW_VER_NON_RAID, 178 FL_4PORT = FW_VER_4PORT, 179 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), 180 FL_DAC = (1 << 16), 181 FL_DYN_MAJOR = (1 << 17), 182}; 183 184enum scatter_gather_types { 185 SGT_32BIT = 0, 186 SGT_64BIT = 1, 187}; 188 189enum host_states { 190 HST_INVALID, /* invalid state; never used */ 191 HST_ALLOC_BUF, /* setting up master SHM area */ 192 HST_ERROR, /* we never leave here */ 193 HST_PORT_SCAN, /* start dev scan */ 194 HST_DEV_SCAN_START, /* start per-device probe */ 195 HST_DEV_SCAN, /* continue per-device probe */ 196 HST_DEV_ACTIVATE, /* activate devices we found */ 197 HST_PROBE_FINISHED, /* probe is complete */ 198 HST_PROBE_START, /* initiate probe */ 199 HST_SYNC_TIME, /* tell firmware what time it is */ 200 HST_GET_FW_VER, /* get firmware version, adapter port cnt */ 201}; 202 203#ifdef CARM_DEBUG 204static const char *state_name[] = { 205 "HST_INVALID", 206 "HST_ALLOC_BUF", 207 "HST_ERROR", 208 "HST_PORT_SCAN", 209 "HST_DEV_SCAN_START", 210 "HST_DEV_SCAN", 211 "HST_DEV_ACTIVATE", 212 "HST_PROBE_FINISHED", 213 "HST_PROBE_START", 214 "HST_SYNC_TIME", 215 "HST_GET_FW_VER", 216}; 217#endif 218 219struct carm_port { 220 unsigned int port_no; 221 unsigned int n_queued; 222 struct gendisk *disk; 223 struct carm_host *host; 224 225 /* attached device characteristics */ 226 u64 capacity; 227 char name[41]; 228 u16 dev_geom_head; 229 u16 dev_geom_sect; 230 u16 dev_geom_cyl; 231}; 232 233struct carm_request { 234 unsigned int tag; 235 int n_elem; 236 unsigned int msg_type; 237 unsigned int msg_subtype; 238 unsigned int msg_bucket; 239 struct request *rq; 240 struct carm_port *port; 241 struct scatterlist sg[CARM_MAX_REQ_SG]; 242}; 243 244struct carm_host { 245 unsigned long flags; 246 void __iomem *mmio; 247 void *shm; 248 dma_addr_t shm_dma; 249 250 int major; 251 int id; 252 char name[32]; 253 254 spinlock_t lock; 255 struct pci_dev *pdev; 256 unsigned int state; 257 u32 fw_ver; 258 259 request_queue_t *oob_q; 260 unsigned int n_oob; 261 262 unsigned int hw_sg_used; 263 264 unsigned int resp_idx; 265 266 unsigned int wait_q_prod; 267 unsigned int wait_q_cons; 268 request_queue_t *wait_q[CARM_MAX_WAIT_Q]; 269 270 unsigned int n_msgs; 271 u64 msg_alloc; 272 struct carm_request req[CARM_MAX_REQ]; 273 void *msg_base; 274 dma_addr_t msg_dma; 275 276 int cur_scan_dev; 277 unsigned long dev_active; 278 unsigned long dev_present; 279 struct carm_port port[CARM_MAX_PORTS]; 280 281 struct work_struct fsm_task; 282 283 struct semaphore probe_sem; 284}; 285 286struct carm_response { 287 __le32 ret_handle; 288 __le32 status; 289} __attribute__((packed)); 290 291struct carm_msg_sg { 292 __le32 start; 293 __le32 len; 294} __attribute__((packed)); 295 296struct carm_msg_rw { 297 u8 type; 298 u8 id; 299 u8 sg_count; 300 u8 sg_type; 301 __le32 handle; 302 __le32 lba; 303 __le16 lba_count; 304 __le16 lba_high; 305 struct carm_msg_sg sg[32]; 306} __attribute__((packed)); 307 308struct carm_msg_allocbuf { 309 u8 type; 310 u8 subtype; 311 u8 n_sg; 312 u8 sg_type; 313 __le32 handle; 314 __le32 addr; 315 __le32 len; 316 __le32 evt_pool; 317 __le32 n_evt; 318 __le32 rbuf_pool; 319 __le32 n_rbuf; 320 __le32 msg_pool; 321 __le32 n_msg; 322 struct carm_msg_sg sg[8]; 323} __attribute__((packed)); 324 325struct carm_msg_ioctl { 326 u8 type; 327 u8 subtype; 328 u8 array_id; 329 u8 reserved1; 330 __le32 handle; 331 __le32 data_addr; 332 u32 reserved2; 333} __attribute__((packed)); 334 335struct carm_msg_sync_time { 336 u8 type; 337 u8 subtype; 338 u16 reserved1; 339 __le32 handle; 340 u32 reserved2; 341 __le32 timestamp; 342} __attribute__((packed)); 343 344struct carm_msg_get_fw_ver { 345 u8 type; 346 u8 subtype; 347 u16 reserved1; 348 __le32 handle; 349 __le32 data_addr; 350 u32 reserved2; 351} __attribute__((packed)); 352 353struct carm_fw_ver { 354 __le32 version; 355 u8 features; 356 u8 reserved1; 357 u16 reserved2; 358} __attribute__((packed)); 359 360struct carm_array_info { 361 __le32 size; 362 363 __le16 size_hi; 364 __le16 stripe_size; 365 366 __le32 mode; 367 368 __le16 stripe_blk_sz; 369 __le16 reserved1; 370 371 __le16 cyl; 372 __le16 head; 373 374 __le16 sect; 375 u8 array_id; 376 u8 reserved2; 377 378 char name[40]; 379 380 __le32 array_status; 381 382 /* device list continues beyond this point? */ 383} __attribute__((packed)); 384 385static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 386static void carm_remove_one (struct pci_dev *pdev); 387static int carm_bdev_ioctl(struct inode *ino, struct file *fil, 388 unsigned int cmd, unsigned long arg); 389 390static struct pci_device_id carm_pci_tbl[] = { 391 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 392 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 393 { } /* terminate list */ 394}; 395MODULE_DEVICE_TABLE(pci, carm_pci_tbl); 396 397static struct pci_driver carm_driver = { 398 .name = DRV_NAME, 399 .id_table = carm_pci_tbl, 400 .probe = carm_init_one, 401 .remove = carm_remove_one, 402}; 403 404static struct block_device_operations carm_bd_ops = { 405 .owner = THIS_MODULE, 406 .ioctl = carm_bdev_ioctl, 407}; 408 409static unsigned int carm_host_id; 410static unsigned long carm_major_alloc; 411 412 413 414static int carm_bdev_ioctl(struct inode *ino, struct file *fil, 415 unsigned int cmd, unsigned long arg) 416{ 417 void __user *usermem = (void __user *) arg; 418 struct carm_port *port = ino->i_bdev->bd_disk->private_data; 419 struct hd_geometry geom; 420 421 switch (cmd) { 422 case HDIO_GETGEO: 423 if (!usermem) 424 return -EINVAL; 425 426 geom.heads = (u8) port->dev_geom_head; 427 geom.sectors = (u8) port->dev_geom_sect; 428 geom.cylinders = port->dev_geom_cyl; 429 geom.start = get_start_sect(ino->i_bdev); 430 431 if (copy_to_user(usermem, &geom, sizeof(geom))) 432 return -EFAULT; 433 return 0; 434 435 default: 436 break; 437 } 438 439 return -EOPNOTSUPP; 440} 441 442static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; 443 444static inline int carm_lookup_bucket(u32 msg_size) 445{ 446 int i; 447 448 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 449 if (msg_size <= msg_sizes[i]) 450 return i; 451 452 return -ENOENT; 453} 454 455static void carm_init_buckets(void __iomem *mmio) 456{ 457 unsigned int i; 458 459 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 460 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); 461} 462 463static inline void *carm_ref_msg(struct carm_host *host, 464 unsigned int msg_idx) 465{ 466 return host->msg_base + (msg_idx * CARM_MSG_SIZE); 467} 468 469static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, 470 unsigned int msg_idx) 471{ 472 return host->msg_dma + (msg_idx * CARM_MSG_SIZE); 473} 474 475static int carm_send_msg(struct carm_host *host, 476 struct carm_request *crq) 477{ 478 void __iomem *mmio = host->mmio; 479 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); 480 u32 cm_bucket = crq->msg_bucket; 481 u32 tmp; 482 int rc = 0; 483 484 VPRINTK("ENTER\n"); 485 486 tmp = readl(mmio + CARM_HMUC); 487 if (tmp & CARM_Q_FULL) { 488#if 0 489 tmp = readl(mmio + CARM_INT_MASK); 490 tmp |= INT_Q_AVAILABLE; 491 writel(tmp, mmio + CARM_INT_MASK); 492 readl(mmio + CARM_INT_MASK); /* flush */ 493#endif 494 DPRINTK("host msg queue full\n"); 495 rc = -EBUSY; 496 } else { 497 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); 498 readl(mmio + CARM_IHQP); /* flush */ 499 } 500 501 return rc; 502} 503 504static struct carm_request *carm_get_request(struct carm_host *host) 505{ 506 unsigned int i; 507 508 /* obey global hardware limit on S/G entries */ 509 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) 510 return NULL; 511 512 for (i = 0; i < CARM_MAX_Q; i++) 513 if ((host->msg_alloc & (1ULL << i)) == 0) { 514 struct carm_request *crq = &host->req[i]; 515 crq->port = NULL; 516 crq->n_elem = 0; 517 518 host->msg_alloc |= (1ULL << i); 519 host->n_msgs++; 520 521 assert(host->n_msgs <= CARM_MAX_REQ); 522 return crq; 523 } 524 525 DPRINTK("no request available, returning NULL\n"); 526 return NULL; 527} 528 529static int carm_put_request(struct carm_host *host, struct carm_request *crq) 530{ 531 assert(crq->tag < CARM_MAX_Q); 532 533 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) 534 return -EINVAL; /* tried to clear a tag that was not active */ 535 536 assert(host->hw_sg_used >= crq->n_elem); 537 538 host->msg_alloc &= ~(1ULL << crq->tag); 539 host->hw_sg_used -= crq->n_elem; 540 host->n_msgs--; 541 542 return 0; 543} 544 545static struct carm_request *carm_get_special(struct carm_host *host) 546{ 547 unsigned long flags; 548 struct carm_request *crq = NULL; 549 struct request *rq; 550 int tries = 5000; 551 552 while (tries-- > 0) { 553 spin_lock_irqsave(&host->lock, flags); 554 crq = carm_get_request(host); 555 spin_unlock_irqrestore(&host->lock, flags); 556 557 if (crq) 558 break; 559 msleep(10); 560 } 561 562 if (!crq) 563 return NULL; 564 565 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL); 566 if (!rq) { 567 spin_lock_irqsave(&host->lock, flags); 568 carm_put_request(host, crq); 569 spin_unlock_irqrestore(&host->lock, flags); 570 return NULL; 571 } 572 573 crq->rq = rq; 574 return crq; 575} 576 577static int carm_array_info (struct carm_host *host, unsigned int array_idx) 578{ 579 struct carm_msg_ioctl *ioc; 580 unsigned int idx; 581 u32 msg_data; 582 dma_addr_t msg_dma; 583 struct carm_request *crq; 584 int rc; 585 586 crq = carm_get_special(host); 587 if (!crq) { 588 rc = -ENOMEM; 589 goto err_out; 590 } 591 592 idx = crq->tag; 593 594 ioc = carm_ref_msg(host, idx); 595 msg_dma = carm_ref_msg_dma(host, idx); 596 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); 597 598 crq->msg_type = CARM_MSG_ARRAY; 599 crq->msg_subtype = CARM_ARRAY_INFO; 600 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + 601 sizeof(struct carm_array_info)); 602 BUG_ON(rc < 0); 603 crq->msg_bucket = (u32) rc; 604 605 memset(ioc, 0, sizeof(*ioc)); 606 ioc->type = CARM_MSG_ARRAY; 607 ioc->subtype = CARM_ARRAY_INFO; 608 ioc->array_id = (u8) array_idx; 609 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 610 ioc->data_addr = cpu_to_le32(msg_data); 611 612 spin_lock_irq(&host->lock); 613 assert(host->state == HST_DEV_SCAN_START || 614 host->state == HST_DEV_SCAN); 615 spin_unlock_irq(&host->lock); 616 617 DPRINTK("blk_insert_request, tag == %u\n", idx); 618 blk_insert_request(host->oob_q, crq->rq, 1, crq); 619 620 return 0; 621 622err_out: 623 spin_lock_irq(&host->lock); 624 host->state = HST_ERROR; 625 spin_unlock_irq(&host->lock); 626 return rc; 627} 628 629typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); 630 631static int carm_send_special (struct carm_host *host, carm_sspc_t func) 632{ 633 struct carm_request *crq; 634 struct carm_msg_ioctl *ioc; 635 void *mem; 636 unsigned int idx, msg_size; 637 int rc; 638 639 crq = carm_get_special(host); 640 if (!crq) 641 return -ENOMEM; 642 643 idx = crq->tag; 644 645 mem = carm_ref_msg(host, idx); 646 647 msg_size = func(host, idx, mem); 648 649 ioc = mem; 650 crq->msg_type = ioc->type; 651 crq->msg_subtype = ioc->subtype; 652 rc = carm_lookup_bucket(msg_size); 653 BUG_ON(rc < 0); 654 crq->msg_bucket = (u32) rc; 655 656 DPRINTK("blk_insert_request, tag == %u\n", idx); 657 blk_insert_request(host->oob_q, crq->rq, 1, crq); 658 659 return 0; 660} 661 662static unsigned int carm_fill_sync_time(struct carm_host *host, 663 unsigned int idx, void *mem) 664{ 665 struct timeval tv; 666 struct carm_msg_sync_time *st = mem; 667 668 do_gettimeofday(&tv); 669 670 memset(st, 0, sizeof(*st)); 671 st->type = CARM_MSG_MISC; 672 st->subtype = MISC_SET_TIME; 673 st->handle = cpu_to_le32(TAG_ENCODE(idx)); 674 st->timestamp = cpu_to_le32(tv.tv_sec); 675 676 return sizeof(struct carm_msg_sync_time); 677} 678 679static unsigned int carm_fill_alloc_buf(struct carm_host *host, 680 unsigned int idx, void *mem) 681{ 682 struct carm_msg_allocbuf *ab = mem; 683 684 memset(ab, 0, sizeof(*ab)); 685 ab->type = CARM_MSG_MISC; 686 ab->subtype = MISC_ALLOC_MEM; 687 ab->handle = cpu_to_le32(TAG_ENCODE(idx)); 688 ab->n_sg = 1; 689 ab->sg_type = SGT_32BIT; 690 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 691 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); 692 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); 693 ab->n_evt = cpu_to_le32(1024); 694 ab->rbuf_pool = cpu_to_le32(host->shm_dma); 695 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); 696 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); 697 ab->n_msg = cpu_to_le32(CARM_Q_LEN); 698 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 699 ab->sg[0].len = cpu_to_le32(65536); 700 701 return sizeof(struct carm_msg_allocbuf); 702} 703 704static unsigned int carm_fill_scan_channels(struct carm_host *host, 705 unsigned int idx, void *mem) 706{ 707 struct carm_msg_ioctl *ioc = mem; 708 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + 709 IOC_SCAN_CHAN_OFFSET); 710 711 memset(ioc, 0, sizeof(*ioc)); 712 ioc->type = CARM_MSG_IOCTL; 713 ioc->subtype = CARM_IOC_SCAN_CHAN; 714 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 715 ioc->data_addr = cpu_to_le32(msg_data); 716 717 /* fill output data area with "no device" default values */ 718 mem += IOC_SCAN_CHAN_OFFSET; 719 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); 720 721 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; 722} 723 724static unsigned int carm_fill_get_fw_ver(struct carm_host *host, 725 unsigned int idx, void *mem) 726{ 727 struct carm_msg_get_fw_ver *ioc = mem; 728 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); 729 730 memset(ioc, 0, sizeof(*ioc)); 731 ioc->type = CARM_MSG_MISC; 732 ioc->subtype = MISC_GET_FW_VER; 733 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 734 ioc->data_addr = cpu_to_le32(msg_data); 735 736 return sizeof(struct carm_msg_get_fw_ver) + 737 sizeof(struct carm_fw_ver); 738} 739 740static inline void carm_end_request_queued(struct carm_host *host, 741 struct carm_request *crq, 742 int uptodate) 743{ 744 struct request *req = crq->rq; 745 int rc; 746 747 rc = end_that_request_first(req, uptodate, req->hard_nr_sectors); 748 assert(rc == 0); 749 750 end_that_request_last(req); 751 752 rc = carm_put_request(host, crq); 753 assert(rc == 0); 754} 755 756static inline void carm_push_q (struct carm_host *host, request_queue_t *q) 757{ 758 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; 759 760 blk_stop_queue(q); 761 VPRINTK("STOPPED QUEUE %p\n", q); 762 763 host->wait_q[idx] = q; 764 host->wait_q_prod++; 765 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ 766} 767 768static inline request_queue_t *carm_pop_q(struct carm_host *host) 769{ 770 unsigned int idx; 771 772 if (host->wait_q_prod == host->wait_q_cons) 773 return NULL; 774 775 idx = host->wait_q_cons % CARM_MAX_WAIT_Q; 776 host->wait_q_cons++; 777 778 return host->wait_q[idx]; 779} 780 781static inline void carm_round_robin(struct carm_host *host) 782{ 783 request_queue_t *q = carm_pop_q(host); 784 if (q) { 785 blk_start_queue(q); 786 VPRINTK("STARTED QUEUE %p\n", q); 787 } 788} 789 790static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, 791 int is_ok) 792{ 793 carm_end_request_queued(host, crq, is_ok); 794 if (CARM_MAX_Q == 1) 795 carm_round_robin(host); 796 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && 797 (host->hw_sg_used <= CARM_SG_LOW_WATER)) { 798 carm_round_robin(host); 799 } 800} 801 802static void carm_oob_rq_fn(request_queue_t *q) 803{ 804 struct carm_host *host = q->queuedata; 805 struct carm_request *crq; 806 struct request *rq; 807 int rc; 808 809 while (1) { 810 DPRINTK("get req\n"); 811 rq = elv_next_request(q); 812 if (!rq) 813 break; 814 815 blkdev_dequeue_request(rq); 816 817 crq = rq->special; 818 assert(crq != NULL); 819 assert(crq->rq == rq); 820 821 crq->n_elem = 0; 822 823 DPRINTK("send req\n"); 824 rc = carm_send_msg(host, crq); 825 if (rc) { 826 blk_requeue_request(q, rq); 827 carm_push_q(host, q); 828 return; /* call us again later, eventually */ 829 } 830 } 831} 832 833static void carm_rq_fn(request_queue_t *q) 834{ 835 struct carm_port *port = q->queuedata; 836 struct carm_host *host = port->host; 837 struct carm_msg_rw *msg; 838 struct carm_request *crq; 839 struct request *rq; 840 struct scatterlist *sg; 841 int writing = 0, pci_dir, i, n_elem, rc; 842 u32 tmp; 843 unsigned int msg_size; 844 845queue_one_request: 846 VPRINTK("get req\n"); 847 rq = elv_next_request(q); 848 if (!rq) 849 return; 850 851 crq = carm_get_request(host); 852 if (!crq) { 853 carm_push_q(host, q); 854 return; /* call us again later, eventually */ 855 } 856 crq->rq = rq; 857 858 blkdev_dequeue_request(rq); 859 860 if (rq_data_dir(rq) == WRITE) { 861 writing = 1; 862 pci_dir = PCI_DMA_TODEVICE; 863 } else { 864 pci_dir = PCI_DMA_FROMDEVICE; 865 } 866 867 /* get scatterlist from block layer */ 868 sg = &crq->sg[0]; 869 n_elem = blk_rq_map_sg(q, rq, sg); 870 if (n_elem <= 0) { 871 carm_end_rq(host, crq, 0); 872 return; /* request with no s/g entries? */ 873 } 874 875 /* map scatterlist to PCI bus addresses */ 876 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); 877 if (n_elem <= 0) { 878 carm_end_rq(host, crq, 0); 879 return; /* request with no s/g entries? */ 880 } 881 crq->n_elem = n_elem; 882 crq->port = port; 883 host->hw_sg_used += n_elem; 884 885 /* 886 * build read/write message 887 */ 888 889 VPRINTK("build msg\n"); 890 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); 891 892 if (writing) { 893 msg->type = CARM_MSG_WRITE; 894 crq->msg_type = CARM_MSG_WRITE; 895 } else { 896 msg->type = CARM_MSG_READ; 897 crq->msg_type = CARM_MSG_READ; 898 } 899 900 msg->id = port->port_no; 901 msg->sg_count = n_elem; 902 msg->sg_type = SGT_32BIT; 903 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); 904 msg->lba = cpu_to_le32(rq->sector & 0xffffffff); 905 tmp = (rq->sector >> 16) >> 16; 906 msg->lba_high = cpu_to_le16( (u16) tmp ); 907 msg->lba_count = cpu_to_le16(rq->nr_sectors); 908 909 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); 910 for (i = 0; i < n_elem; i++) { 911 struct carm_msg_sg *carm_sg = &msg->sg[i]; 912 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); 913 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); 914 msg_size += sizeof(struct carm_msg_sg); 915 } 916 917 rc = carm_lookup_bucket(msg_size); 918 BUG_ON(rc < 0); 919 crq->msg_bucket = (u32) rc; 920 921 /* 922 * queue read/write message to hardware 923 */ 924 925 VPRINTK("send msg, tag == %u\n", crq->tag); 926 rc = carm_send_msg(host, crq); 927 if (rc) { 928 carm_put_request(host, crq); 929 blk_requeue_request(q, rq); 930 carm_push_q(host, q); 931 return; /* call us again later, eventually */ 932 } 933 934 goto queue_one_request; 935} 936 937static void carm_handle_array_info(struct carm_host *host, 938 struct carm_request *crq, u8 *mem, 939 int is_ok) 940{ 941 struct carm_port *port; 942 u8 *msg_data = mem + sizeof(struct carm_array_info); 943 struct carm_array_info *desc = (struct carm_array_info *) msg_data; 944 u64 lo, hi; 945 int cur_port; 946 size_t slen; 947 948 DPRINTK("ENTER\n"); 949 950 carm_end_rq(host, crq, is_ok); 951 952 if (!is_ok) 953 goto out; 954 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) 955 goto out; 956 957 cur_port = host->cur_scan_dev; 958 959 /* should never occur */ 960 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { 961 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", 962 cur_port, (int) desc->array_id); 963 goto out; 964 } 965 966 port = &host->port[cur_port]; 967 968 lo = (u64) le32_to_cpu(desc->size); 969 hi = (u64) le16_to_cpu(desc->size_hi); 970 971 port->capacity = lo | (hi << 32); 972 port->dev_geom_head = le16_to_cpu(desc->head); 973 port->dev_geom_sect = le16_to_cpu(desc->sect); 974 port->dev_geom_cyl = le16_to_cpu(desc->cyl); 975 976 host->dev_active |= (1 << cur_port); 977 978 strncpy(port->name, desc->name, sizeof(port->name)); 979 port->name[sizeof(port->name) - 1] = 0; 980 slen = strlen(port->name); 981 while (slen && (port->name[slen - 1] == ' ')) { 982 port->name[slen - 1] = 0; 983 slen--; 984 } 985 986 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", 987 pci_name(host->pdev), port->port_no, 988 (unsigned long long) port->capacity); 989 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", 990 pci_name(host->pdev), port->port_no, port->name); 991 992out: 993 assert(host->state == HST_DEV_SCAN); 994 schedule_work(&host->fsm_task); 995} 996 997static void carm_handle_scan_chan(struct carm_host *host, 998 struct carm_request *crq, u8 *mem, 999 int is_ok) 1000{ 1001 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; 1002 unsigned int i, dev_count = 0; 1003 int new_state = HST_DEV_SCAN_START; 1004 1005 DPRINTK("ENTER\n"); 1006 1007 carm_end_rq(host, crq, is_ok); 1008 1009 if (!is_ok) { 1010 new_state = HST_ERROR; 1011 goto out; 1012 } 1013 1014 /* TODO: scan and support non-disk devices */ 1015 for (i = 0; i < 8; i++) 1016 if (msg_data[i] == 0) { /* direct-access device (disk) */ 1017 host->dev_present |= (1 << i); 1018 dev_count++; 1019 } 1020 1021 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", 1022 pci_name(host->pdev), dev_count); 1023 1024out: 1025 assert(host->state == HST_PORT_SCAN); 1026 host->state = new_state; 1027 schedule_work(&host->fsm_task); 1028} 1029 1030static void carm_handle_generic(struct carm_host *host, 1031 struct carm_request *crq, int is_ok, 1032 int cur_state, int next_state) 1033{ 1034 DPRINTK("ENTER\n"); 1035 1036 carm_end_rq(host, crq, is_ok); 1037 1038 assert(host->state == cur_state); 1039 if (is_ok) 1040 host->state = next_state; 1041 else 1042 host->state = HST_ERROR; 1043 schedule_work(&host->fsm_task); 1044} 1045 1046static inline void carm_handle_rw(struct carm_host *host, 1047 struct carm_request *crq, int is_ok) 1048{ 1049 int pci_dir; 1050 1051 VPRINTK("ENTER\n"); 1052 1053 if (rq_data_dir(crq->rq) == WRITE) 1054 pci_dir = PCI_DMA_TODEVICE; 1055 else 1056 pci_dir = PCI_DMA_FROMDEVICE; 1057 1058 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); 1059 1060 carm_end_rq(host, crq, is_ok); 1061} 1062 1063static inline void carm_handle_resp(struct carm_host *host, 1064 __le32 ret_handle_le, u32 status) 1065{ 1066 u32 handle = le32_to_cpu(ret_handle_le); 1067 unsigned int msg_idx; 1068 struct carm_request *crq; 1069 int is_ok = (status == RMSG_OK); 1070 u8 *mem; 1071 1072 VPRINTK("ENTER, handle == 0x%x\n", handle); 1073 1074 if (unlikely(!TAG_VALID(handle))) { 1075 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", 1076 pci_name(host->pdev), handle); 1077 return; 1078 } 1079 1080 msg_idx = TAG_DECODE(handle); 1081 VPRINTK("tag == %u\n", msg_idx); 1082 1083 crq = &host->req[msg_idx]; 1084 1085 /* fast path */ 1086 if (likely(crq->msg_type == CARM_MSG_READ || 1087 crq->msg_type == CARM_MSG_WRITE)) { 1088 carm_handle_rw(host, crq, is_ok); 1089 return; 1090 } 1091 1092 mem = carm_ref_msg(host, msg_idx); 1093 1094 switch (crq->msg_type) { 1095 case CARM_MSG_IOCTL: { 1096 switch (crq->msg_subtype) { 1097 case CARM_IOC_SCAN_CHAN: 1098 carm_handle_scan_chan(host, crq, mem, is_ok); 1099 break; 1100 default: 1101 /* unknown / invalid response */ 1102 goto err_out; 1103 } 1104 break; 1105 } 1106 1107 case CARM_MSG_MISC: { 1108 switch (crq->msg_subtype) { 1109 case MISC_ALLOC_MEM: 1110 carm_handle_generic(host, crq, is_ok, 1111 HST_ALLOC_BUF, HST_SYNC_TIME); 1112 break; 1113 case MISC_SET_TIME: 1114 carm_handle_generic(host, crq, is_ok, 1115 HST_SYNC_TIME, HST_GET_FW_VER); 1116 break; 1117 case MISC_GET_FW_VER: { 1118 struct carm_fw_ver *ver = (struct carm_fw_ver *) 1119 mem + sizeof(struct carm_msg_get_fw_ver); 1120 if (is_ok) { 1121 host->fw_ver = le32_to_cpu(ver->version); 1122 host->flags |= (ver->features & FL_FW_VER_MASK); 1123 } 1124 carm_handle_generic(host, crq, is_ok, 1125 HST_GET_FW_VER, HST_PORT_SCAN); 1126 break; 1127 } 1128 default: 1129 /* unknown / invalid response */ 1130 goto err_out; 1131 } 1132 break; 1133 } 1134 1135 case CARM_MSG_ARRAY: { 1136 switch (crq->msg_subtype) { 1137 case CARM_ARRAY_INFO: 1138 carm_handle_array_info(host, crq, mem, is_ok); 1139 break; 1140 default: 1141 /* unknown / invalid response */ 1142 goto err_out; 1143 } 1144 break; 1145 } 1146 1147 default: 1148 /* unknown / invalid response */ 1149 goto err_out; 1150 } 1151 1152 return; 1153 1154err_out: 1155 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", 1156 pci_name(host->pdev), crq->msg_type, crq->msg_subtype); 1157 carm_end_rq(host, crq, 0); 1158} 1159 1160static inline void carm_handle_responses(struct carm_host *host) 1161{ 1162 void __iomem *mmio = host->mmio; 1163 struct carm_response *resp = (struct carm_response *) host->shm; 1164 unsigned int work = 0; 1165 unsigned int idx = host->resp_idx % RMSG_Q_LEN; 1166 1167 while (1) { 1168 u32 status = le32_to_cpu(resp[idx].status); 1169 1170 if (status == 0xffffffff) { 1171 VPRINTK("ending response on index %u\n", idx); 1172 writel(idx << 3, mmio + CARM_RESP_IDX); 1173 break; 1174 } 1175 1176 /* response to a message we sent */ 1177 else if ((status & (1 << 31)) == 0) { 1178 VPRINTK("handling msg response on index %u\n", idx); 1179 carm_handle_resp(host, resp[idx].ret_handle, status); 1180 resp[idx].status = cpu_to_le32(0xffffffff); 1181 } 1182 1183 /* asynchronous events the hardware throws our way */ 1184 else if ((status & 0xff000000) == (1 << 31)) { 1185 u8 *evt_type_ptr = (u8 *) &resp[idx]; 1186 u8 evt_type = *evt_type_ptr; 1187 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", 1188 pci_name(host->pdev), (int) evt_type); 1189 resp[idx].status = cpu_to_le32(0xffffffff); 1190 } 1191 1192 idx = NEXT_RESP(idx); 1193 work++; 1194 } 1195 1196 VPRINTK("EXIT, work==%u\n", work); 1197 host->resp_idx += work; 1198} 1199 1200static irqreturn_t carm_interrupt(int irq, void *__host, struct pt_regs *regs) 1201{ 1202 struct carm_host *host = __host; 1203 void __iomem *mmio; 1204 u32 mask; 1205 int handled = 0; 1206 unsigned long flags; 1207 1208 if (!host) { 1209 VPRINTK("no host\n"); 1210 return IRQ_NONE; 1211 } 1212 1213 spin_lock_irqsave(&host->lock, flags); 1214 1215 mmio = host->mmio; 1216 1217 /* reading should also clear interrupts */ 1218 mask = readl(mmio + CARM_INT_STAT); 1219 1220 if (mask == 0 || mask == 0xffffffff) { 1221 VPRINTK("no work, mask == 0x%x\n", mask); 1222 goto out; 1223 } 1224 1225 if (mask & INT_ACK_MASK) 1226 writel(mask, mmio + CARM_INT_STAT); 1227 1228 if (unlikely(host->state == HST_INVALID)) { 1229 VPRINTK("not initialized yet, mask = 0x%x\n", mask); 1230 goto out; 1231 } 1232 1233 if (mask & CARM_HAVE_RESP) { 1234 handled = 1; 1235 carm_handle_responses(host); 1236 } 1237 1238out: 1239 spin_unlock_irqrestore(&host->lock, flags); 1240 VPRINTK("EXIT\n"); 1241 return IRQ_RETVAL(handled); 1242} 1243 1244static void carm_fsm_task (void *_data) 1245{ 1246 struct carm_host *host = _data; 1247 unsigned long flags; 1248 unsigned int state; 1249 int rc, i, next_dev; 1250 int reschedule = 0; 1251 int new_state = HST_INVALID; 1252 1253 spin_lock_irqsave(&host->lock, flags); 1254 state = host->state; 1255 spin_unlock_irqrestore(&host->lock, flags); 1256 1257 DPRINTK("ENTER, state == %s\n", state_name[state]); 1258 1259 switch (state) { 1260 case HST_PROBE_START: 1261 new_state = HST_ALLOC_BUF; 1262 reschedule = 1; 1263 break; 1264 1265 case HST_ALLOC_BUF: 1266 rc = carm_send_special(host, carm_fill_alloc_buf); 1267 if (rc) { 1268 new_state = HST_ERROR; 1269 reschedule = 1; 1270 } 1271 break; 1272 1273 case HST_SYNC_TIME: 1274 rc = carm_send_special(host, carm_fill_sync_time); 1275 if (rc) { 1276 new_state = HST_ERROR; 1277 reschedule = 1; 1278 } 1279 break; 1280 1281 case HST_GET_FW_VER: 1282 rc = carm_send_special(host, carm_fill_get_fw_ver); 1283 if (rc) { 1284 new_state = HST_ERROR; 1285 reschedule = 1; 1286 } 1287 break; 1288 1289 case HST_PORT_SCAN: 1290 rc = carm_send_special(host, carm_fill_scan_channels); 1291 if (rc) { 1292 new_state = HST_ERROR; 1293 reschedule = 1; 1294 } 1295 break; 1296 1297 case HST_DEV_SCAN_START: 1298 host->cur_scan_dev = -1; 1299 new_state = HST_DEV_SCAN; 1300 reschedule = 1; 1301 break; 1302 1303 case HST_DEV_SCAN: 1304 next_dev = -1; 1305 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) 1306 if (host->dev_present & (1 << i)) { 1307 next_dev = i; 1308 break; 1309 } 1310 1311 if (next_dev >= 0) { 1312 host->cur_scan_dev = next_dev; 1313 rc = carm_array_info(host, next_dev); 1314 if (rc) { 1315 new_state = HST_ERROR; 1316 reschedule = 1; 1317 } 1318 } else { 1319 new_state = HST_DEV_ACTIVATE; 1320 reschedule = 1; 1321 } 1322 break; 1323 1324 case HST_DEV_ACTIVATE: { 1325 int activated = 0; 1326 for (i = 0; i < CARM_MAX_PORTS; i++) 1327 if (host->dev_active & (1 << i)) { 1328 struct carm_port *port = &host->port[i]; 1329 struct gendisk *disk = port->disk; 1330 1331 set_capacity(disk, port->capacity); 1332 add_disk(disk); 1333 activated++; 1334 } 1335 1336 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", 1337 pci_name(host->pdev), activated); 1338 1339 new_state = HST_PROBE_FINISHED; 1340 reschedule = 1; 1341 break; 1342 } 1343 1344 case HST_PROBE_FINISHED: 1345 up(&host->probe_sem); 1346 break; 1347 1348 case HST_ERROR: 1349 /* FIXME: TODO */ 1350 break; 1351 1352 default: 1353 /* should never occur */ 1354 printk(KERN_ERR PFX "BUG: unknown state %d\n", state); 1355 assert(0); 1356 break; 1357 } 1358 1359 if (new_state != HST_INVALID) { 1360 spin_lock_irqsave(&host->lock, flags); 1361 host->state = new_state; 1362 spin_unlock_irqrestore(&host->lock, flags); 1363 } 1364 if (reschedule) 1365 schedule_work(&host->fsm_task); 1366} 1367 1368static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) 1369{ 1370 unsigned int i; 1371 1372 for (i = 0; i < 50000; i++) { 1373 u32 tmp = readl(mmio + CARM_LMUC); 1374 udelay(100); 1375 1376 if (test_bit) { 1377 if ((tmp & bits) == bits) 1378 return 0; 1379 } else { 1380 if ((tmp & bits) == 0) 1381 return 0; 1382 } 1383 1384 cond_resched(); 1385 } 1386 1387 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", 1388 bits, test_bit ? "yes" : "no"); 1389 return -EBUSY; 1390} 1391 1392static void carm_init_responses(struct carm_host *host) 1393{ 1394 void __iomem *mmio = host->mmio; 1395 unsigned int i; 1396 struct carm_response *resp = (struct carm_response *) host->shm; 1397 1398 for (i = 0; i < RMSG_Q_LEN; i++) 1399 resp[i].status = cpu_to_le32(0xffffffff); 1400 1401 writel(0, mmio + CARM_RESP_IDX); 1402} 1403 1404static int carm_init_host(struct carm_host *host) 1405{ 1406 void __iomem *mmio = host->mmio; 1407 u32 tmp; 1408 u8 tmp8; 1409 int rc; 1410 1411 DPRINTK("ENTER\n"); 1412 1413 writel(0, mmio + CARM_INT_MASK); 1414 1415 tmp8 = readb(mmio + CARM_INITC); 1416 if (tmp8 & 0x01) { 1417 tmp8 &= ~0x01; 1418 writeb(tmp8, mmio + CARM_INITC); 1419 readb(mmio + CARM_INITC); /* flush */ 1420 1421 DPRINTK("snooze...\n"); 1422 msleep(5000); 1423 } 1424 1425 tmp = readl(mmio + CARM_HMUC); 1426 if (tmp & CARM_CME) { 1427 DPRINTK("CME bit present, waiting\n"); 1428 rc = carm_init_wait(mmio, CARM_CME, 1); 1429 if (rc) { 1430 DPRINTK("EXIT, carm_init_wait 1 failed\n"); 1431 return rc; 1432 } 1433 } 1434 if (tmp & CARM_RME) { 1435 DPRINTK("RME bit present, waiting\n"); 1436 rc = carm_init_wait(mmio, CARM_RME, 1); 1437 if (rc) { 1438 DPRINTK("EXIT, carm_init_wait 2 failed\n"); 1439 return rc; 1440 } 1441 } 1442 1443 tmp &= ~(CARM_RME | CARM_CME); 1444 writel(tmp, mmio + CARM_HMUC); 1445 readl(mmio + CARM_HMUC); /* flush */ 1446 1447 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); 1448 if (rc) { 1449 DPRINTK("EXIT, carm_init_wait 3 failed\n"); 1450 return rc; 1451 } 1452 1453 carm_init_buckets(mmio); 1454 1455 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); 1456 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); 1457 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); 1458 1459 tmp = readl(mmio + CARM_HMUC); 1460 tmp |= (CARM_RME | CARM_CME | CARM_WZBC); 1461 writel(tmp, mmio + CARM_HMUC); 1462 readl(mmio + CARM_HMUC); /* flush */ 1463 1464 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); 1465 if (rc) { 1466 DPRINTK("EXIT, carm_init_wait 4 failed\n"); 1467 return rc; 1468 } 1469 1470 writel(0, mmio + CARM_HMPHA); 1471 writel(INT_DEF_MASK, mmio + CARM_INT_MASK); 1472 1473 carm_init_responses(host); 1474 1475 /* start initialization, probing state machine */ 1476 spin_lock_irq(&host->lock); 1477 assert(host->state == HST_INVALID); 1478 host->state = HST_PROBE_START; 1479 spin_unlock_irq(&host->lock); 1480 schedule_work(&host->fsm_task); 1481 1482 DPRINTK("EXIT\n"); 1483 return 0; 1484} 1485 1486static int carm_init_disks(struct carm_host *host) 1487{ 1488 unsigned int i; 1489 int rc = 0; 1490 1491 for (i = 0; i < CARM_MAX_PORTS; i++) { 1492 struct gendisk *disk; 1493 request_queue_t *q; 1494 struct carm_port *port; 1495 1496 port = &host->port[i]; 1497 port->host = host; 1498 port->port_no = i; 1499 1500 disk = alloc_disk(CARM_MINORS_PER_MAJOR); 1501 if (!disk) { 1502 rc = -ENOMEM; 1503 break; 1504 } 1505 1506 port->disk = disk; 1507 sprintf(disk->disk_name, DRV_NAME "/%u", 1508 (unsigned int) (host->id * CARM_MAX_PORTS) + i); 1509 sprintf(disk->devfs_name, DRV_NAME "/%u_%u", host->id, i); 1510 disk->major = host->major; 1511 disk->first_minor = i * CARM_MINORS_PER_MAJOR; 1512 disk->fops = &carm_bd_ops; 1513 disk->private_data = port; 1514 1515 q = blk_init_queue(carm_rq_fn, &host->lock); 1516 if (!q) { 1517 rc = -ENOMEM; 1518 break; 1519 } 1520 disk->queue = q; 1521 blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG); 1522 blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG); 1523 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); 1524 1525 q->queuedata = port; 1526 } 1527 1528 return rc; 1529} 1530 1531static void carm_free_disks(struct carm_host *host) 1532{ 1533 unsigned int i; 1534 1535 for (i = 0; i < CARM_MAX_PORTS; i++) { 1536 struct gendisk *disk = host->port[i].disk; 1537 if (disk) { 1538 request_queue_t *q = disk->queue; 1539 1540 if (disk->flags & GENHD_FL_UP) 1541 del_gendisk(disk); 1542 if (q) 1543 blk_cleanup_queue(q); 1544 put_disk(disk); 1545 } 1546 } 1547} 1548 1549static int carm_init_shm(struct carm_host *host) 1550{ 1551 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, 1552 &host->shm_dma); 1553 if (!host->shm) 1554 return -ENOMEM; 1555 1556 host->msg_base = host->shm + RBUF_LEN; 1557 host->msg_dma = host->shm_dma + RBUF_LEN; 1558 1559 memset(host->shm, 0xff, RBUF_LEN); 1560 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); 1561 1562 return 0; 1563} 1564 1565static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1566{ 1567 static unsigned int printed_version; 1568 struct carm_host *host; 1569 unsigned int pci_dac; 1570 int rc; 1571 request_queue_t *q; 1572 unsigned int i; 1573 1574 if (!printed_version++) 1575 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); 1576 1577 rc = pci_enable_device(pdev); 1578 if (rc) 1579 return rc; 1580 1581 rc = pci_request_regions(pdev, DRV_NAME); 1582 if (rc) 1583 goto err_out; 1584 1585#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1586 rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK); 1587 if (!rc) { 1588 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1589 if (rc) { 1590 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", 1591 pci_name(pdev)); 1592 goto err_out_regions; 1593 } 1594 pci_dac = 1; 1595 } else { 1596#endif 1597 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1598 if (rc) { 1599 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", 1600 pci_name(pdev)); 1601 goto err_out_regions; 1602 } 1603 pci_dac = 0; 1604#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1605 } 1606#endif 1607 1608 host = kmalloc(sizeof(*host), GFP_KERNEL); 1609 if (!host) { 1610 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", 1611 pci_name(pdev)); 1612 rc = -ENOMEM; 1613 goto err_out_regions; 1614 } 1615 1616 memset(host, 0, sizeof(*host)); 1617 host->pdev = pdev; 1618 host->flags = pci_dac ? FL_DAC : 0; 1619 spin_lock_init(&host->lock); 1620 INIT_WORK(&host->fsm_task, carm_fsm_task, host); 1621 init_MUTEX_LOCKED(&host->probe_sem); 1622 1623 for (i = 0; i < ARRAY_SIZE(host->req); i++) 1624 host->req[i].tag = i; 1625 1626 host->mmio = ioremap(pci_resource_start(pdev, 0), 1627 pci_resource_len(pdev, 0)); 1628 if (!host->mmio) { 1629 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", 1630 pci_name(pdev)); 1631 rc = -ENOMEM; 1632 goto err_out_kfree; 1633 } 1634 1635 rc = carm_init_shm(host); 1636 if (rc) { 1637 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", 1638 pci_name(pdev)); 1639 goto err_out_iounmap; 1640 } 1641 1642 q = blk_init_queue(carm_oob_rq_fn, &host->lock); 1643 if (!q) { 1644 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", 1645 pci_name(pdev)); 1646 rc = -ENOMEM; 1647 goto err_out_pci_free; 1648 } 1649 host->oob_q = q; 1650 q->queuedata = host; 1651 1652 /* 1653 * Figure out which major to use: 160, 161, or dynamic 1654 */ 1655 if (!test_and_set_bit(0, &carm_major_alloc)) 1656 host->major = 160; 1657 else if (!test_and_set_bit(1, &carm_major_alloc)) 1658 host->major = 161; 1659 else 1660 host->flags |= FL_DYN_MAJOR; 1661 1662 host->id = carm_host_id; 1663 sprintf(host->name, DRV_NAME "%d", carm_host_id); 1664 1665 rc = register_blkdev(host->major, host->name); 1666 if (rc < 0) 1667 goto err_out_free_majors; 1668 if (host->flags & FL_DYN_MAJOR) 1669 host->major = rc; 1670 1671 devfs_mk_dir(DRV_NAME); 1672 1673 rc = carm_init_disks(host); 1674 if (rc) 1675 goto err_out_blkdev_disks; 1676 1677 pci_set_master(pdev); 1678 1679 rc = request_irq(pdev->irq, carm_interrupt, SA_SHIRQ, DRV_NAME, host); 1680 if (rc) { 1681 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", 1682 pci_name(pdev)); 1683 goto err_out_blkdev_disks; 1684 } 1685 1686 rc = carm_init_host(host); 1687 if (rc) 1688 goto err_out_free_irq; 1689 1690 DPRINTK("waiting for probe_sem\n"); 1691 down(&host->probe_sem); 1692 1693 printk(KERN_INFO "%s: pci %s, ports %d, io %lx, irq %u, major %d\n", 1694 host->name, pci_name(pdev), (int) CARM_MAX_PORTS, 1695 pci_resource_start(pdev, 0), pdev->irq, host->major); 1696 1697 carm_host_id++; 1698 pci_set_drvdata(pdev, host); 1699 return 0; 1700 1701err_out_free_irq: 1702 free_irq(pdev->irq, host); 1703err_out_blkdev_disks: 1704 carm_free_disks(host); 1705 unregister_blkdev(host->major, host->name); 1706err_out_free_majors: 1707 if (host->major == 160) 1708 clear_bit(0, &carm_major_alloc); 1709 else if (host->major == 161) 1710 clear_bit(1, &carm_major_alloc); 1711 blk_cleanup_queue(host->oob_q); 1712err_out_pci_free: 1713 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1714err_out_iounmap: 1715 iounmap(host->mmio); 1716err_out_kfree: 1717 kfree(host); 1718err_out_regions: 1719 pci_release_regions(pdev); 1720err_out: 1721 pci_disable_device(pdev); 1722 return rc; 1723} 1724 1725static void carm_remove_one (struct pci_dev *pdev) 1726{ 1727 struct carm_host *host = pci_get_drvdata(pdev); 1728 1729 if (!host) { 1730 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", 1731 pci_name(pdev)); 1732 return; 1733 } 1734 1735 free_irq(pdev->irq, host); 1736 carm_free_disks(host); 1737 devfs_remove(DRV_NAME); 1738 unregister_blkdev(host->major, host->name); 1739 if (host->major == 160) 1740 clear_bit(0, &carm_major_alloc); 1741 else if (host->major == 161) 1742 clear_bit(1, &carm_major_alloc); 1743 blk_cleanup_queue(host->oob_q); 1744 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1745 iounmap(host->mmio); 1746 kfree(host); 1747 pci_release_regions(pdev); 1748 pci_disable_device(pdev); 1749 pci_set_drvdata(pdev, NULL); 1750} 1751 1752static int __init carm_init(void) 1753{ 1754 return pci_module_init(&carm_driver); 1755} 1756 1757static void __exit carm_exit(void) 1758{ 1759 pci_unregister_driver(&carm_driver); 1760} 1761 1762module_init(carm_init); 1763module_exit(carm_exit); 1764 1765