at v2.6.13 47 lines 1.8 kB view raw
1 2/* 3 * Board initialization code should put one of these into dev->platform_data 4 * and place the isp116x onto platform_bus. 5 */ 6 7struct isp116x_platform_data { 8 /* Enable internal resistors on downstream ports */ 9 unsigned sel15Kres:1; 10 /* Chip's internal clock won't be stopped in suspended state. 11 Setting/unsetting this bit takes effect only if 12 'remote_wakeup_enable' below is not set. */ 13 unsigned clknotstop:1; 14 /* On-chip overcurrent protection */ 15 unsigned oc_enable:1; 16 /* INT output polarity */ 17 unsigned int_act_high:1; 18 /* INT edge or level triggered */ 19 unsigned int_edge_triggered:1; 20 /* WAKEUP pin connected - NOT SUPPORTED */ 21 /* unsigned remote_wakeup_connected:1; */ 22 /* Wakeup by devices on usb bus enabled */ 23 unsigned remote_wakeup_enable:1; 24 /* Switch or not to switch (keep always powered) */ 25 unsigned no_power_switching:1; 26 /* Ganged port power switching (0) or individual port 27 power switching (1) */ 28 unsigned power_switching_mode:1; 29 /* Given port_power, msec/2 after power on till power good */ 30 u8 potpg; 31 /* Hardware reset set/clear. If implemented, this function must: 32 if set == 0, deassert chip's HW reset pin 33 otherwise, assert chip's HW reset pin */ 34 void (*reset) (struct device * dev, int set); 35 /* Hardware clock start/stop. If implemented, this function must: 36 if start == 0, stop the external clock 37 otherwise, start the external clock 38 */ 39 void (*clock) (struct device * dev, int start); 40 /* Inter-io delay (ns). The chip is picky about access timings; it 41 expects at least: 42 150ns delay between consecutive accesses to DATA_REG, 43 300ns delay between access to ADDR_REG and DATA_REG 44 OE, WE MUST NOT be changed during these intervals 45 */ 46 void (*delay) (struct device * dev, int delay); 47};