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1/*****************************************************************************
2* sdlapci.h WANPIPE(tm) Multiprotocol WAN Link Driver.
3* Definitions for the SDLA PCI adapter.
4*
5* Author: Gideon Hack <ghack@sangoma.com>
6*
7* Copyright: (c) 1999-2000 Sangoma Technologies Inc.
8*
9* This program is free software; you can redistribute it and/or
10* modify it under the terms of the GNU General Public License
11* as published by the Free Software Foundation; either version
12* 2 of the License, or (at your option) any later version.
13* ============================================================================
14* Jun 02, 1999 Gideon Hack Initial version.
15*****************************************************************************/
16#ifndef _SDLAPCI_H
17#define _SDLAPCI_H
18
19/****** Defines *************************************************************/
20
21/* Definitions for identifying and finding S514 PCI adapters */
22#define V3_VENDOR_ID 0x11B0 /* V3 vendor ID number */
23#define V3_DEVICE_ID 0x0002 /* V3 device ID number */
24#define SANGOMA_SUBSYS_VENDOR 0x4753 /* ID for Sangoma */
25#define PCI_DEV_SLOT_MASK 0x1F /* mask for slot numbering */
26#define PCI_IRQ_NOT_ALLOCATED 0xFF /* interrupt line for no IRQ */
27
28/* Local PCI register offsets */
29#define PCI_VENDOR_ID_WORD 0x00 /* vendor ID */
30#define PCI_IO_BASE_DWORD 0x10 /* IO base */
31#define PCI_MEM_BASE0_DWORD 0x14 /* memory base - apperture 0 */
32#define PCI_MEM_BASE1_DWORD 0x18 /* memory base - apperture 1 */
33#define PCI_SUBSYS_VENDOR_WORD 0x2C /* subsystem vendor ID */
34#define PCI_INT_LINE_BYTE 0x3C /* interrupt line */
35#define PCI_INT_PIN_BYTE 0x3D /* interrupt pin */
36#define PCI_MAP0_DWORD 0x40 /* PCI to local bus address 0 */
37#define PCI_MAP1_DWORD 0x44 /* PCI to local bus address 1 */
38#define PCI_INT_STATUS 0x48 /* interrupt status */
39#define PCI_INT_CONFIG 0x4C /* interrupt configuration */
40
41/* Local PCI register usage */
42#define PCI_MEMORY_ENABLE 0x00000003 /* enable PCI memory */
43#define PCI_CPU_A_MEM_DISABLE 0x00000002 /* disable CPU A memory */
44#define PCI_CPU_B_MEM_DISABLE 0x00100002 /* disable CPU B memory */
45#define PCI_ENABLE_IRQ_CPU_A 0x005A0004 /* enable IRQ for CPU A */
46#define PCI_ENABLE_IRQ_CPU_B 0x005A0008 /* enable IRQ for CPU B */
47#define PCI_DISABLE_IRQ_CPU_A 0x00000004 /* disable IRQ for CPU A */
48#define PCI_DISABLE_IRQ_CPU_B 0x00000008 /* disable IRQ for CPU B */
49
50/* Setting for the Interrupt Status register */
51#define IRQ_CPU_A 0x04 /* IRQ for CPU A */
52#define IRQ_CPU_B 0x08 /* IRQ for CPU B */
53
54/* The maximum size of the S514 memory */
55#define MAX_SIZEOF_S514_MEMORY (256 * 1024)
56
57/* S514 control register offsets within the memory address space */
58#define S514_CTRL_REG_BYTE 0x80000
59
60/* S514 adapter control bytes */
61#define S514_CPU_HALT 0x00
62#define S514_CPU_START 0x01
63
64/* The maximum number of S514 adapters supported */
65#define MAX_S514_CARDS 20
66
67#define PCI_CARD_TYPE 0x2E
68#define S514_DUAL_CPU 0x12
69#define S514_SINGLE_CPU 0x11
70
71#endif /* _SDLAPCI_H */
72