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1/*
2 * include/asm-x86_64/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_X86_64_PROCESSOR_H
8#define __ASM_X86_64_PROCESSOR_H
9
10#include <asm/segment.h>
11#include <asm/page.h>
12#include <asm/types.h>
13#include <asm/sigcontext.h>
14#include <asm/cpufeature.h>
15#include <linux/config.h>
16#include <linux/threads.h>
17#include <asm/msr.h>
18#include <asm/current.h>
19#include <asm/system.h>
20#include <asm/mmsegment.h>
21#include <asm/percpu.h>
22#include <linux/personality.h>
23
24#define TF_MASK 0x00000100
25#define IF_MASK 0x00000200
26#define IOPL_MASK 0x00003000
27#define NT_MASK 0x00004000
28#define VM_MASK 0x00020000
29#define AC_MASK 0x00040000
30#define VIF_MASK 0x00080000 /* virtual interrupt flag */
31#define VIP_MASK 0x00100000 /* virtual interrupt pending */
32#define ID_MASK 0x00200000
33
34#define desc_empty(desc) \
35 (!((desc)->a | (desc)->b))
36
37#define desc_equal(desc1, desc2) \
38 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
39
40/*
41 * Default implementation of macro that returns current
42 * instruction pointer ("program counter").
43 */
44#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
45
46/*
47 * CPU type and hardware bug flags. Kept separately for each CPU.
48 */
49
50struct cpuinfo_x86 {
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
53 __u8 x86_model;
54 __u8 x86_mask;
55 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
56 __u32 x86_capability[NCAPINTS];
57 char x86_vendor_id[16];
58 char x86_model_id[64];
59 int x86_cache_size; /* in KB */
60 int x86_clflush_size;
61 int x86_cache_alignment;
62 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
63 __u8 x86_virt_bits, x86_phys_bits;
64 __u8 x86_num_cores;
65 __u32 x86_power;
66 __u32 extended_cpuid_level; /* Max extended CPUID function supported */
67 unsigned long loops_per_jiffy;
68} ____cacheline_aligned;
69
70#define X86_VENDOR_INTEL 0
71#define X86_VENDOR_CYRIX 1
72#define X86_VENDOR_AMD 2
73#define X86_VENDOR_UMC 3
74#define X86_VENDOR_NEXGEN 4
75#define X86_VENDOR_CENTAUR 5
76#define X86_VENDOR_RISE 6
77#define X86_VENDOR_TRANSMETA 7
78#define X86_VENDOR_NUM 8
79#define X86_VENDOR_UNKNOWN 0xff
80
81#ifdef CONFIG_SMP
82extern struct cpuinfo_x86 cpu_data[];
83#define current_cpu_data cpu_data[smp_processor_id()]
84#else
85#define cpu_data (&boot_cpu_data)
86#define current_cpu_data boot_cpu_data
87#endif
88
89extern char ignore_irq13;
90
91extern void identify_cpu(struct cpuinfo_x86 *);
92extern void print_cpu_info(struct cpuinfo_x86 *);
93extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
94
95/*
96 * EFLAGS bits
97 */
98#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
99#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
100#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
101#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
102#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
103#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
104#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
105#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
106#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
107#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
108#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
109#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
110#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
111#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
112#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
113#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
114#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
115
116/*
117 * Intel CPU features in CR4
118 */
119#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
120#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
121#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
122#define X86_CR4_DE 0x0008 /* enable debugging extensions */
123#define X86_CR4_PSE 0x0010 /* enable page size extensions */
124#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
125#define X86_CR4_MCE 0x0040 /* Machine check enable */
126#define X86_CR4_PGE 0x0080 /* enable global pages */
127#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
128#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
129#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
130
131/*
132 * Save the cr4 feature set we're using (ie
133 * Pentium 4MB enable and PPro Global page
134 * enable), so that any CPU's that boot up
135 * after us can get the correct flags.
136 */
137extern unsigned long mmu_cr4_features;
138
139static inline void set_in_cr4 (unsigned long mask)
140{
141 mmu_cr4_features |= mask;
142 __asm__("movq %%cr4,%%rax\n\t"
143 "orq %0,%%rax\n\t"
144 "movq %%rax,%%cr4\n"
145 : : "irg" (mask)
146 :"ax");
147}
148
149static inline void clear_in_cr4 (unsigned long mask)
150{
151 mmu_cr4_features &= ~mask;
152 __asm__("movq %%cr4,%%rax\n\t"
153 "andq %0,%%rax\n\t"
154 "movq %%rax,%%cr4\n"
155 : : "irg" (~mask)
156 :"ax");
157}
158
159
160/*
161 * User space process size. 47bits minus one guard page.
162 */
163#define TASK_SIZE64 (0x800000000000UL - 4096)
164
165/* This decides where the kernel will search for a free chunk of vm
166 * space during mmap's.
167 */
168#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
169
170#define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
171#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
172
173#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
174
175/*
176 * Size of io_bitmap.
177 */
178#define IO_BITMAP_BITS 65536
179#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
180#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
181#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
182#define INVALID_IO_BITMAP_OFFSET 0x8000
183
184struct i387_fxsave_struct {
185 u16 cwd;
186 u16 swd;
187 u16 twd;
188 u16 fop;
189 u64 rip;
190 u64 rdp;
191 u32 mxcsr;
192 u32 mxcsr_mask;
193 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
194 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
195 u32 padding[24];
196} __attribute__ ((aligned (16)));
197
198union i387_union {
199 struct i387_fxsave_struct fxsave;
200};
201
202struct tss_struct {
203 u32 reserved1;
204 u64 rsp0;
205 u64 rsp1;
206 u64 rsp2;
207 u64 reserved2;
208 u64 ist[7];
209 u32 reserved3;
210 u32 reserved4;
211 u16 reserved5;
212 u16 io_bitmap_base;
213 /*
214 * The extra 1 is there because the CPU will access an
215 * additional byte beyond the end of the IO permission
216 * bitmap. The extra byte must be all 1 bits, and must
217 * be within the limit. Thus we have:
218 *
219 * 128 bytes, the bitmap itself, for ports 0..0x3ff
220 * 8 bytes, for an extra "long" of ~0UL
221 */
222 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
223} __attribute__((packed)) ____cacheline_aligned;
224
225extern struct cpuinfo_x86 boot_cpu_data;
226DECLARE_PER_CPU(struct tss_struct,init_tss);
227
228#define ARCH_MIN_TASKALIGN 16
229
230struct thread_struct {
231 unsigned long rsp0;
232 unsigned long rsp;
233 unsigned long userrsp; /* Copy from PDA */
234 unsigned long fs;
235 unsigned long gs;
236 unsigned short es, ds, fsindex, gsindex;
237/* Hardware debugging registers */
238 unsigned long debugreg0;
239 unsigned long debugreg1;
240 unsigned long debugreg2;
241 unsigned long debugreg3;
242 unsigned long debugreg6;
243 unsigned long debugreg7;
244/* fault info */
245 unsigned long cr2, trap_no, error_code;
246/* floating point info */
247 union i387_union i387 __attribute__((aligned(16)));
248/* IO permissions. the bitmap could be moved into the GDT, that would make
249 switch faster for a limited number of ioperm using tasks. -AK */
250 int ioperm;
251 unsigned long *io_bitmap_ptr;
252 unsigned io_bitmap_max;
253/* cached TLS descriptors. */
254 u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
255} __attribute__((aligned(16)));
256
257#define INIT_THREAD {}
258
259#define INIT_MMAP \
260{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
261
262#define STACKFAULT_STACK 1
263#define DOUBLEFAULT_STACK 2
264#define NMI_STACK 3
265#define DEBUG_STACK 4
266#define MCE_STACK 5
267#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
268#define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
269#define EXCEPTION_STACK_ORDER 0
270
271#define start_thread(regs,new_rip,new_rsp) do { \
272 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
273 load_gs_index(0); \
274 (regs)->rip = (new_rip); \
275 (regs)->rsp = (new_rsp); \
276 write_pda(oldrsp, (new_rsp)); \
277 (regs)->cs = __USER_CS; \
278 (regs)->ss = __USER_DS; \
279 (regs)->eflags = 0x200; \
280 set_fs(USER_DS); \
281} while(0)
282
283#define get_debugreg(var, register) \
284 __asm__("movq %%db" #register ", %0" \
285 :"=r" (var))
286#define set_debugreg(value, register) \
287 __asm__("movq %0,%%db" #register \
288 : /* no output */ \
289 :"r" (value))
290
291struct task_struct;
292struct mm_struct;
293
294/* Free all resources held by a thread. */
295extern void release_thread(struct task_struct *);
296
297/* Prepare to copy thread state - unlazy all lazy status */
298extern void prepare_to_copy(struct task_struct *tsk);
299
300/*
301 * create a kernel thread without removing it from tasklists
302 */
303extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
304
305/*
306 * Return saved PC of a blocked thread.
307 * What is this good for? it will be always the scheduler or ret_from_fork.
308 */
309#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
310
311extern unsigned long get_wchan(struct task_struct *p);
312#define KSTK_EIP(tsk) \
313 (((struct pt_regs *)(tsk->thread.rsp0 - sizeof(struct pt_regs)))->rip)
314#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
315
316
317struct microcode_header {
318 unsigned int hdrver;
319 unsigned int rev;
320 unsigned int date;
321 unsigned int sig;
322 unsigned int cksum;
323 unsigned int ldrver;
324 unsigned int pf;
325 unsigned int datasize;
326 unsigned int totalsize;
327 unsigned int reserved[3];
328};
329
330struct microcode {
331 struct microcode_header hdr;
332 unsigned int bits[0];
333};
334
335typedef struct microcode microcode_t;
336typedef struct microcode_header microcode_header_t;
337
338/* microcode format is extended from prescott processors */
339struct extended_signature {
340 unsigned int sig;
341 unsigned int pf;
342 unsigned int cksum;
343};
344
345struct extended_sigtable {
346 unsigned int count;
347 unsigned int cksum;
348 unsigned int reserved[3];
349 struct extended_signature sigs[0];
350};
351
352/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
353#define MICROCODE_IOCFREE _IO('6',0)
354
355
356#define ASM_NOP1 K8_NOP1
357#define ASM_NOP2 K8_NOP2
358#define ASM_NOP3 K8_NOP3
359#define ASM_NOP4 K8_NOP4
360#define ASM_NOP5 K8_NOP5
361#define ASM_NOP6 K8_NOP6
362#define ASM_NOP7 K8_NOP7
363#define ASM_NOP8 K8_NOP8
364
365/* Opteron nops */
366#define K8_NOP1 ".byte 0x90\n"
367#define K8_NOP2 ".byte 0x66,0x90\n"
368#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
369#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
370#define K8_NOP5 K8_NOP3 K8_NOP2
371#define K8_NOP6 K8_NOP3 K8_NOP3
372#define K8_NOP7 K8_NOP4 K8_NOP3
373#define K8_NOP8 K8_NOP4 K8_NOP4
374
375#define ASM_NOP_MAX 8
376
377/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
378extern inline void rep_nop(void)
379{
380 __asm__ __volatile__("rep;nop": : :"memory");
381}
382
383/* Stop speculative execution */
384extern inline void sync_core(void)
385{
386 int tmp;
387 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
388}
389
390#define cpu_has_fpu 1
391
392#define ARCH_HAS_PREFETCH
393static inline void prefetch(void *x)
394{
395 asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
396}
397
398#define ARCH_HAS_PREFETCHW 1
399static inline void prefetchw(void *x)
400{
401 alternative_input(ASM_NOP5,
402 "prefetchw (%1)",
403 X86_FEATURE_3DNOW,
404 "r" (x));
405}
406
407#define ARCH_HAS_SPINLOCK_PREFETCH 1
408
409#define spin_lock_prefetch(x) prefetchw(x)
410
411#define cpu_relax() rep_nop()
412
413/*
414 * NSC/Cyrix CPU configuration register indexes
415 */
416#define CX86_CCR0 0xc0
417#define CX86_CCR1 0xc1
418#define CX86_CCR2 0xc2
419#define CX86_CCR3 0xc3
420#define CX86_CCR4 0xe8
421#define CX86_CCR5 0xe9
422#define CX86_CCR6 0xea
423#define CX86_CCR7 0xeb
424#define CX86_DIR0 0xfe
425#define CX86_DIR1 0xff
426#define CX86_ARR_BASE 0xc4
427#define CX86_RCR_BASE 0xdc
428
429/*
430 * NSC/Cyrix CPU indexed register access macros
431 */
432
433#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
434
435#define setCx86(reg, data) do { \
436 outb((reg), 0x22); \
437 outb((data), 0x23); \
438} while (0)
439
440static inline void __monitor(const void *eax, unsigned long ecx,
441 unsigned long edx)
442{
443 /* "monitor %eax,%ecx,%edx;" */
444 asm volatile(
445 ".byte 0x0f,0x01,0xc8;"
446 : :"a" (eax), "c" (ecx), "d"(edx));
447}
448
449static inline void __mwait(unsigned long eax, unsigned long ecx)
450{
451 /* "mwait %eax,%ecx;" */
452 asm volatile(
453 ".byte 0x0f,0x01,0xc9;"
454 : :"a" (eax), "c" (ecx));
455}
456
457#define stack_current() \
458({ \
459 struct thread_info *ti; \
460 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
461 ti->task; \
462})
463
464#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
465
466extern unsigned long boot_option_idle_override;
467/* Boot loader type from the setup header */
468extern int bootloader_type;
469
470#endif /* __ASM_X86_64_PROCESSOR_H */