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1/* $Id: processor.h,v 1.83 2002/02/10 06:04:33 davem Exp $
2 * include/asm-sparc64/processor.h
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef __ASM_SPARC64_PROCESSOR_H
8#define __ASM_SPARC64_PROCESSOR_H
9
10/*
11 * Sparc64 implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
15
16#include <linux/config.h>
17#include <asm/asi.h>
18#include <asm/a.out.h>
19#include <asm/pstate.h>
20#include <asm/ptrace.h>
21#include <asm/segment.h>
22#include <asm/page.h>
23
24/* The sparc has no problems with write protection */
25#define wp_works_ok 1
26#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
27
28/*
29 * User lives in his very own context, and cannot reference us. Note
30 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
31 * address that the kernel will allocate out.
32 */
33#define VA_BITS 44
34#ifndef __ASSEMBLY__
35#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
36#else
37#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
38#endif
39#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
40
41/*
42 * The vpte base must be able to hold the entire vpte, half
43 * of which lives above, and half below, the base. And it
44 * is placed as close to the highest address range as possible.
45 */
46#define VPTE_BASE_SPITFIRE (-(VPTE_SIZE/2))
47#if 1
48#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
49#else
50#define VPTE_BASE_CHEETAH 0xffe0000000000000
51#endif
52
53#ifndef __ASSEMBLY__
54
55typedef struct {
56 unsigned char seg;
57} mm_segment_t;
58
59/* The Sparc processor specific thread struct. */
60/* XXX This should die, everything can go into thread_info now. */
61struct thread_struct {
62#ifdef CONFIG_DEBUG_SPINLOCK
63 /* How many spinlocks held by this thread.
64 * Used with spin lock debugging to catch tasks
65 * sleeping illegally with locks held.
66 */
67 int smp_lock_count;
68 unsigned int smp_lock_pc;
69#else
70 int dummy; /* f'in gcc bug... */
71#endif
72};
73
74#endif /* !(__ASSEMBLY__) */
75
76#ifndef CONFIG_DEBUG_SPINLOCK
77#define INIT_THREAD { \
78 0, \
79}
80#else /* CONFIG_DEBUG_SPINLOCK */
81#define INIT_THREAD { \
82/* smp_lock_count, smp_lock_pc, */ \
83 0, 0, \
84}
85#endif /* !(CONFIG_DEBUG_SPINLOCK) */
86
87#ifndef __ASSEMBLY__
88
89#include <linux/types.h>
90
91/* Return saved PC of a blocked thread. */
92struct task_struct;
93extern unsigned long thread_saved_pc(struct task_struct *);
94
95/* On Uniprocessor, even in RMO processes see TSO semantics */
96#ifdef CONFIG_SMP
97#define TSTATE_INITIAL_MM TSTATE_TSO
98#else
99#define TSTATE_INITIAL_MM TSTATE_RMO
100#endif
101
102/* Do necessary setup to start up a newly executed thread. */
103#define start_thread(regs, pc, sp) \
104do { \
105 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (ASI_PNF << 24); \
106 regs->tpc = ((pc & (~3)) - 4); \
107 regs->tnpc = regs->tpc + 4; \
108 regs->y = 0; \
109 set_thread_wstate(1 << 3); \
110 if (current_thread_info()->utraps) { \
111 if (*(current_thread_info()->utraps) < 2) \
112 kfree(current_thread_info()->utraps); \
113 else \
114 (*(current_thread_info()->utraps))--; \
115 current_thread_info()->utraps = NULL; \
116 } \
117 __asm__ __volatile__( \
118 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
119 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
120 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
121 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
122 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
123 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
124 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
125 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
126 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
132 "stx %1, [%0 + %2 + 0x70]\n\t" \
133 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
134 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
135 : \
136 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
137 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
138} while (0)
139
140#define start_thread32(regs, pc, sp) \
141do { \
142 pc &= 0x00000000ffffffffUL; \
143 sp &= 0x00000000ffffffffUL; \
144\
145 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM); \
146 regs->tpc = ((pc & (~3)) - 4); \
147 regs->tnpc = regs->tpc + 4; \
148 regs->y = 0; \
149 set_thread_wstate(2 << 3); \
150 if (current_thread_info()->utraps) { \
151 if (*(current_thread_info()->utraps) < 2) \
152 kfree(current_thread_info()->utraps); \
153 else \
154 (*(current_thread_info()->utraps))--; \
155 current_thread_info()->utraps = NULL; \
156 } \
157 __asm__ __volatile__( \
158 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
159 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
160 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
161 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
162 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
163 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
164 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
165 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
166 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
167 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
172 "stx %1, [%0 + %2 + 0x70]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
174 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
175 : \
176 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
177 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
178} while (0)
179
180/* Free all resources held by a thread. */
181#define release_thread(tsk) do { } while (0)
182
183/* Prepare to copy thread state - unlazy all lazy status */
184#define prepare_to_copy(tsk) do { } while (0)
185
186extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
187
188extern unsigned long get_wchan(struct task_struct *task);
189
190#define KSTK_EIP(tsk) ((tsk)->thread_info->kregs->tpc)
191#define KSTK_ESP(tsk) ((tsk)->thread_info->kregs->u_regs[UREG_FP])
192
193#define cpu_relax() barrier()
194
195/* Prefetch support. This is tuned for UltraSPARC-III and later.
196 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
197 * a shallower prefetch queue than later chips.
198 */
199#define ARCH_HAS_PREFETCH
200#define ARCH_HAS_PREFETCHW
201#define ARCH_HAS_SPINLOCK_PREFETCH
202
203static inline void prefetch(const void *x)
204{
205 /* We do not use the read prefetch mnemonic because that
206 * prefetches into the prefetch-cache which only is accessible
207 * by floating point operations in UltraSPARC-III and later.
208 * By contrast, "#one_write" prefetches into the L2 cache
209 * in shared state.
210 */
211 __asm__ __volatile__("prefetch [%0], #one_write"
212 : /* no outputs */
213 : "r" (x));
214}
215
216static inline void prefetchw(const void *x)
217{
218 /* The most optimal prefetch to use for writes is
219 * "#n_writes". This brings the cacheline into the
220 * L2 cache in "owned" state.
221 */
222 __asm__ __volatile__("prefetch [%0], #n_writes"
223 : /* no outputs */
224 : "r" (x));
225}
226
227#define spin_lock_prefetch(x) prefetchw(x)
228
229#endif /* !(__ASSEMBLY__) */
230
231#endif /* !(__ASM_SPARC64_PROCESSOR_H) */