tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef __ASM_SH_HD64461
2#define __ASM_SH_HD64461
3/*
4 * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
5 * Copyright (C) 2000 YAEGASHI Takeshi
6 * Hitachi HD64461 companion chip support
7 */
8#include <linux/config.h>
9
10/* Constants for PCMCIA mappings */
11#define HD64461_PCC_WINDOW 0x01000000
12
13#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */
14#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE)
15#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
16#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
17
18#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */
19#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE)
20#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
21
22#define HD64461_STBCR 0x10000
23#define HD64461_STBCR_CKIO_STBY 0x2000
24#define HD64461_STBCR_SAFECKE_IST 0x1000
25#define HD64461_STBCR_SLCKE_IST 0x0800
26#define HD64461_STBCR_SAFECKE_OST 0x0400
27#define HD64461_STBCR_SLCKE_OST 0x0200
28#define HD64461_STBCR_SMIAST 0x0100
29#define HD64461_STBCR_SLCDST 0x0080
30#define HD64461_STBCR_SPC0ST 0x0040
31#define HD64461_STBCR_SPC1ST 0x0020
32#define HD64461_STBCR_SAFEST 0x0010
33#define HD64461_STBCR_STM0ST 0x0008
34#define HD64461_STBCR_STM1ST 0x0004
35#define HD64461_STBCR_SIRST 0x0002
36#define HD64461_STBCR_SURTST 0x0001
37
38#define HD64461_SYSCR 0x10002
39#define HD64461_SCPUCR 0x10004
40
41#define HD64461_LCDCBAR 0x11000
42#define HD64461_LCDCLOR 0x11002
43#define HD64461_LCDCCR 0x11004
44#define HD64461_LCDCCR_MOFF 0x80
45
46#define HD64461_LDR1 0x11010
47#define HD64461_LDR1_DON 0x01
48#define HD64461_LDR1_DINV 0x80
49
50#define HD64461_LDR2 0x11012
51#define HD64461_LDHNCR 0x11014
52#define HD64461_LDHNSR 0x11016
53#define HD64461_LDVNTR 0x11018
54#define HD64461_LDVNDR 0x1101a
55#define HD64461_LDVSPR 0x1101c
56#define HD64461_LDR3 0x1101e
57
58#define HD64461_CPTWAR 0x11030
59#define HD64461_CPTWDR 0x11032
60#define HD64461_CPTRAR 0x11034
61#define HD64461_CPTRDR 0x11036
62
63#define HD64461_GRDOR 0x11040
64#define HD64461_GRSCR 0x11042
65#define HD64461_GRCFGR 0x11044
66#define HD64461_GRCFGR_ACCSTATUS 0x10
67#define HD64461_GRCFGR_ACCRESET 0x08
68#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06
69#define HD64461_GRCFGR_ACCSTART_LINE 0x04
70#define HD64461_GRCFGR_COLORDEPTH16 0x01
71
72#define HD64461_LNSARH 0x11046
73#define HD64461_LNSARL 0x11048
74#define HD64461_LNAXLR 0x1104a
75#define HD64461_LNDGR 0x1104c
76#define HD64461_LNAXR 0x1104e
77#define HD64461_LNERTR 0x11050
78#define HD64461_LNMDR 0x11052
79#define HD64461_BBTSSARH 0x11054
80#define HD64461_BBTSSARL 0x11056
81#define HD64461_BBTDSARH 0x11058
82#define HD64461_BBTDSARL 0x1105a
83#define HD64461_BBTDWR 0x1105c
84#define HD64461_BBTDHR 0x1105e
85#define HD64461_BBTPARH 0x11060
86#define HD64461_BBTPARL 0x11062
87#define HD64461_BBTMARH 0x11064
88#define HD64461_BBTMARL 0x11066
89#define HD64461_BBTROPR 0x11068
90#define HD64461_BBTMDR 0x1106a
91
92/* PC Card Controller Registers */
93#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */
94#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */
95#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */
96#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
97#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */
98#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */
99#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */
100#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */
101#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
102#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */
103
104/* PCC Interface Status Register */
105#define HD64461_PCCISR_READY 0x80 /* card ready */
106#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
107#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
108#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
109#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
110#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
111#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
112#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
113
114#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
115#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
116#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
117#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
118#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
119#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
120
121/* PCC General Control Register */
122#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
123#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
124#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
125#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
126#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
127#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
128#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
129#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
130
131/* PCC Card Status Change Register */
132#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
133#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
134#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
135#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
136#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
137#define HD64461_PCCCSCR_RC 0x04 /* READY change */
138#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
139#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
140
141/* PCC Card Status Change Interrupt Enable Register */
142#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
143#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
144#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
145#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
146#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
147#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
148
149#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
150#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
151#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
152#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
153#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
154
155/* PCC Software Control Register */
156#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
157#define HD64461_PCCSCR_SWP 0x01 /* write protect */
158
159
160#define HD64461_P0OCR 0x1202a
161#define HD64461_P1OCR 0x1202c
162#define HD64461_PGCR 0x1202e
163
164#define HD64461_GPACR 0x14000
165#define HD64461_GPBCR 0x14002
166#define HD64461_GPCCR 0x14004
167#define HD64461_GPDCR 0x14006
168#define HD64461_GPADR 0x14010
169#define HD64461_GPBDR 0x14012
170#define HD64461_GPCDR 0x14014
171#define HD64461_GPDDR 0x14016
172#define HD64461_GPAICR 0x14020
173#define HD64461_GPBICR 0x14022
174#define HD64461_GPCICR 0x14024
175#define HD64461_GPDICR 0x14026
176#define HD64461_GPAISR 0x14040
177#define HD64461_GPBISR 0x14042
178#define HD64461_GPCISR 0x14044
179#define HD64461_GPDISR 0x14046
180
181#define HD64461_NIRR 0x15000
182#define HD64461_NIMR 0x15002
183
184#ifndef CONFIG_HD64461_IOBASE
185#define CONFIG_HD64461_IOBASE 0xb0000000
186#endif
187#ifndef CONFIG_HD64461_IRQ
188#define CONFIG_HD64461_IRQ 36
189#endif
190
191#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
192#define HD64461_IRQ_NUM 16
193
194#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
195#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
196#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
197#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
198#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
199#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
200#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
201#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
202
203#endif