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1#ifndef __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H 3 4#define SH_DMAC_BASE 0xffa00000 5 6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ 7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) 8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ 9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) 10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ 11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) 12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ 13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c}) 14#define DMAOR (SH_DMAC_BASE + 0x40) 15 16#endif /* __ASM_CPU_SH4_DMA_H */ 17