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1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19
20/* Page is 4K, OC size is 16K, there are four lines. */
21#define CACHE_ALIAS 0x00003000
22
23struct page;
24struct mm_struct;
25struct vm_area_struct;
26
27extern void flush_cache_all(void);
28extern void flush_cache_mm(struct mm_struct *mm);
29extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
30 unsigned long end);
31extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
32extern void flush_dcache_page(struct page *pg);
33
34#define flush_dcache_mmap_lock(mapping) do { } while (0)
35#define flush_dcache_mmap_unlock(mapping) do { } while (0)
36
37extern void flush_icache_range(unsigned long start, unsigned long end);
38extern void flush_cache_sigtramp(unsigned long addr);
39extern void flush_icache_user_range(struct vm_area_struct *vma,
40 struct page *page, unsigned long addr,
41 int len);
42
43#define flush_icache_page(vma,pg) do { } while (0)
44
45/* Initialization of P3 area for copy_user_page */
46extern void p3_cache_init(void);
47
48#define PG_mapped PG_arch_1
49
50/* We provide our own get_unmapped_area to avoid cache alias issue */
51#define HAVE_ARCH_UNMAPPED_AREA
52
53#ifdef CONFIG_MMU
54extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
55 unsigned long size, unsigned long flags);
56#else /* CONFIG_MMU */
57static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
58 unsigned long size, unsigned long flags)
59{
60 return 0;
61}
62#endif /* CONFIG_MMU */
63#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
64