tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/asm-ppc/ibm44x.h
3 *
4 * PPC44x definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_IBM44x_H__
18#define __ASM_IBM44x_H__
19
20#include <linux/config.h>
21
22#ifndef NR_BOARD_IRQS
23#define NR_BOARD_IRQS 0
24#endif
25
26#define _IO_BASE isa_io_base
27#define _ISA_MEM_BASE isa_mem_base
28#define PCI_DRAM_OFFSET pci_dram_offset
29
30/* TLB entry offset/size used for pinning kernel lowmem */
31#define PPC44x_PIN_SHIFT 28
32#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
33
34/* Lowest TLB slot consumed by the default pinned TLBs */
35#define PPC44x_LOW_SLOT 63
36
37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#if defined(CONFIG_440SP)
39#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000
42#else
43#define UART0_PHYS_IO_BASE 0x40000200
44#endif
45
46/*
47 * XXX This 36-bit trap stuff will move somewhere in syslib/
48 * when we rework/abstract the PPC44x PCI-X handling -mdp
49 */
50
51/*
52 * Standard 4GB "page" definitions
53 */
54#if defined(CONFIG_440SP)
55#define PPC44x_IO_PAGE 0x0000000100000000ULL
56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
64#else
65#define PPC44x_IO_PAGE 0x0000000100000000ULL
66#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
67#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
68#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
69#endif
70
71/*
72 * 36-bit trap ranges
73 */
74#if defined(CONFIG_440SP)
75#define PPC44x_IO_LO 0xf0000000UL
76#define PPC44x_IO_HI 0xf0000fffUL
77#define PPC44x_PCI0CFG_LO 0x0ec00000UL
78#define PPC44x_PCI0CFG_HI 0x0ec00007UL
79#define PPC44x_PCI1CFG_LO 0x1ec00000UL
80#define PPC44x_PCI1CFG_HI 0x1ec00007UL
81#define PPC44x_PCI2CFG_LO 0x2ec00000UL
82#define PPC44x_PCI2CFG_HI 0x2ec00007UL
83#define PPC44x_PCIMEM_LO 0x80000000UL
84#define PPC44x_PCIMEM_HI 0xdfffffffUL
85#elif defined(CONFIG_440EP)
86#define PPC44x_IO_LO 0xef500000UL
87#define PPC44x_IO_HI 0xefffffffUL
88#define PPC44x_PCI0CFG_LO 0xeec00000UL
89#define PPC44x_PCI0CFG_HI 0xeecfffffUL
90#define PPC44x_PCIMEM_LO 0xa0000000UL
91#define PPC44x_PCIMEM_HI 0xdfffffffUL
92#else
93#define PPC44x_IO_LO 0x40000000UL
94#define PPC44x_IO_HI 0x40000fffUL
95#define PPC44x_PCI0CFG_LO 0x0ec00000UL
96#define PPC44x_PCI0CFG_HI 0x0ec00007UL
97#define PPC44x_PCIMEM_LO 0x80002000UL
98#define PPC44x_PCIMEM_HI 0xffffffffUL
99#endif
100
101/*
102 * The "residual" board information structure the boot loader passes
103 * into the kernel.
104 */
105#ifndef __ASSEMBLY__
106
107/*
108 * DCRN definitions
109 */
110
111
112/* CPRs (440GX and 440SP) */
113#define DCRN_CPR_CONFIG_ADDR 0xc
114#define DCRN_CPR_CONFIG_DATA 0xd
115
116#define DCRN_CPR_CLKUPD 0x0020
117#define DCRN_CPR_PLLC 0x0040
118#define DCRN_CPR_PLLD 0x0060
119#define DCRN_CPR_PRIMAD 0x0080
120#define DCRN_CPR_PRIMBD 0x00a0
121#define DCRN_CPR_OPBD 0x00c0
122#define DCRN_CPR_PERD 0x00e0
123#define DCRN_CPR_MALD 0x0100
124
125/* CPRs read/write helper macros */
126#define CPR_READ(offset) ({\
127 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
128 mfdcr(DCRN_CPR_CONFIG_DATA);})
129#define CPR_WRITE(offset, data) ({\
130 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
131 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
132
133/* SDRs (440GX and 440SP) */
134#define DCRN_SDR_CONFIG_ADDR 0xe
135#define DCRN_SDR_CONFIG_DATA 0xf
136#define DCRN_SDR_PFC0 0x4100
137#define DCRN_SDR_PFC1 0x4101
138#define DCRN_SDR_PFC1_EPS 0x1c00000
139#define DCRN_SDR_PFC1_EPS_SHIFT 22
140#define DCRN_SDR_PFC1_RMII 0x02000000
141#define DCRN_SDR_MFR 0x4300
142#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
143#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
144#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
145#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
146#define DCRN_SDR_MFR_T0TXFL 0x00080000
147#define DCRN_SDR_MFR_T0TXFH 0x00040000
148#define DCRN_SDR_MFR_T1TXFL 0x00020000
149#define DCRN_SDR_MFR_T1TXFH 0x00010000
150#define DCRN_SDR_MFR_E0TXFL 0x00008000
151#define DCRN_SDR_MFR_E0TXFH 0x00004000
152#define DCRN_SDR_MFR_E0RXFL 0x00002000
153#define DCRN_SDR_MFR_E0RXFH 0x00001000
154#define DCRN_SDR_MFR_E1TXFL 0x00000800
155#define DCRN_SDR_MFR_E1TXFH 0x00000400
156#define DCRN_SDR_MFR_E1RXFL 0x00000200
157#define DCRN_SDR_MFR_E1RXFH 0x00000100
158#define DCRN_SDR_MFR_E2TXFL 0x00000080
159#define DCRN_SDR_MFR_E2TXFH 0x00000040
160#define DCRN_SDR_MFR_E2RXFL 0x00000020
161#define DCRN_SDR_MFR_E2RXFH 0x00000010
162#define DCRN_SDR_MFR_E3TXFL 0x00000008
163#define DCRN_SDR_MFR_E3TXFH 0x00000004
164#define DCRN_SDR_MFR_E3RXFL 0x00000002
165#define DCRN_SDR_MFR_E3RXFH 0x00000001
166#define DCRN_SDR_UART0 0x0120
167#define DCRN_SDR_UART1 0x0121
168
169#ifdef CONFIG_440EP
170#define DCRN_SDR_UART2 0x0122
171#define DCRN_SDR_UART3 0x0123
172#define DCRN_SDR_CUST0 0x4000
173#endif
174
175/* SDR read/write helper macros */
176#define SDR_READ(offset) ({\
177 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
178 mfdcr(DCRN_SDR_CONFIG_DATA);})
179#define SDR_WRITE(offset, data) ({\
180 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
181 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
182
183/* DMA (excluding 440SP) */
184#define DCRN_DMA0_BASE 0x100
185#define DCRN_DMA1_BASE 0x108
186#define DCRN_DMA2_BASE 0x110
187#define DCRN_DMA3_BASE 0x118
188#define DCRN_DMASR_BASE 0x120
189#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
190#define DCRN_MAL_BASE 0x180
191
192#ifdef CONFIG_440EP
193#define DCRN_DMA2P40_BASE 0x300
194#define DCRN_DMA2P41_BASE 0x308
195#define DCRN_DMA2P42_BASE 0x310
196#define DCRN_DMA2P43_BASE 0x318
197#define DCRN_DMA2P4SR_BASE 0x320
198#endif
199
200/* UIC */
201#define DCRN_UIC0_BASE 0xc0
202#define DCRN_UIC1_BASE 0xd0
203#define DCRN_UIC2_BASE 0x210
204#define DCRN_UICB_BASE 0x200
205#define UIC0 DCRN_UIC0_BASE
206#define UIC1 DCRN_UIC1_BASE
207#define UIC2 DCRN_UIC2_BASE
208#define UICB DCRN_UICB_BASE
209
210#define DCRN_UIC_SR(base) (base + 0x0)
211#define DCRN_UIC_ER(base) (base + 0x2)
212#define DCRN_UIC_CR(base) (base + 0x3)
213#define DCRN_UIC_PR(base) (base + 0x4)
214#define DCRN_UIC_TR(base) (base + 0x5)
215#define DCRN_UIC_MSR(base) (base + 0x6)
216#define DCRN_UIC_VR(base) (base + 0x7)
217#define DCRN_UIC_VCR(base) (base + 0x8)
218
219#define UIC0_UIC1NC 0x00000002
220
221#define UICB_UIC0NC 0x40000000
222#define UICB_UIC1NC 0x10000000
223#define UICB_UIC2NC 0x04000000
224
225/* 440 MAL DCRs */
226#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
227#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
228#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
229#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
230#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
231#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
232#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
233#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
234#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
235#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
236#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
237#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
238#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
239#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
240#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
241#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
242#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
243#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
244#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
245
246/* Compatibility DCRN's */
247#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
248#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
249#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
250#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
251#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
252#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
253#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
254#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
255
256#define MALCR_MMSR 0x80000000 /* MAL Software reset */
257#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
258#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
259#define MALCR_PLBP_3 0x00C00000 /* highest */
260#define MALCR_GA 0x00200000 /* Guarded Active Bit */
261#define MALCR_OA 0x00100000 /* Ordered Active Bit */
262#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
263#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
264#define MALCR_PLBLT_2 0x00020000
265#define MALCR_PLBLT_3 0x00010000
266#define MALCR_PLBLT_4 0x00008000
267#ifdef CONFIG_440GP
268#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
269#else
270#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
271#endif
272#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
273#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
274#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
275#define MALCR_LEA 0x00000002 /* Locked Error Active */
276#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
277/* DCRN_MALESR */
278#define MALESR_EVB 0x80000000 /* Error Valid Bit */
279#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
280#define MALESR_DE 0x00100000 /* Descriptor Error */
281#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
282#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
283#define MALESR_OSE 0x00020000 /* OPB Slave Error */
284#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
285#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
286#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
287#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
288#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
289#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
290/* DCRN_MALIER */
291#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
292#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
293#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
294#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
295#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
296/* DCRN_MALTXEOBISR */
297#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
298#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
299
300/* 440GP/GX PLB Arbiter DCRs */
301#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
302#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
303#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
304#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
305#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
306#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
307
308/* 440GP/GX PLB to OPB bridge DCRs */
309#define DCRN_POB0_BESR0 0x090
310#define DCRN_POB0_BESR1 0x094
311#define DCRN_POB0_BEARL 0x092
312#define DCRN_POB0_BEARH 0x093
313
314/* 440GP/GX OPB to PLB bridge DCRs */
315#define DCRN_OPB0_BSTAT 0x0a9
316#define DCRN_OPB0_BEARL 0x0aa
317#define DCRN_OPB0_BEARH 0x0ab
318
319/* 440GP Clock, PM, chip control */
320#define DCRN_CPC0_SR 0x0b0
321#define DCRN_CPC0_ER 0x0b1
322#define DCRN_CPC0_FR 0x0b2
323#define DCRN_CPC0_SYS0 0x0e0
324#define DCRN_CPC0_SYS1 0x0e1
325#define DCRN_CPC0_CUST0 0x0e2
326#define DCRN_CPC0_CUST1 0x0e3
327#define DCRN_CPC0_STRP0 0x0e4
328#define DCRN_CPC0_STRP1 0x0e5
329#define DCRN_CPC0_STRP2 0x0e6
330#define DCRN_CPC0_STRP3 0x0e7
331#define DCRN_CPC0_GPIO 0x0e8
332#define DCRN_CPC0_PLB 0x0e9
333#define DCRN_CPC0_CR1 0x0ea
334#define DCRN_CPC0_CR0 0x0eb
335#define DCRN_CPC0_MIRQ0 0x0ec
336#define DCRN_CPC0_MIRQ1 0x0ed
337#define DCRN_CPC0_JTAGID 0x0ef
338
339/* 440GP DMA controller DCRs */
340#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
341#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
342#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
343#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
344#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
345#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
346#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
347#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
348
349#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
350#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
351#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
352#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
353#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
354#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
355#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
356#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
357
358#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
359#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
360#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
361#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
362#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
363#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
364#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
365#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
366
367#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
368#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
369#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
370#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
371#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
372#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
373#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
374#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
375
376#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
377#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
378#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
379#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
380
381/* 440GP/440GX SDRAM controller DCRs */
382#define DCRN_SDRAM0_CFGADDR 0x010
383#define DCRN_SDRAM0_CFGDATA 0x011
384
385#define SDRAM0_B0CR 0x40
386#define SDRAM0_B1CR 0x44
387#define SDRAM0_B2CR 0x48
388#define SDRAM0_B3CR 0x4c
389
390#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
391#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
392#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
393#define SDRAM_CONFIG_SIZE_8M 0x00000001
394#define SDRAM_CONFIG_SIZE_16M 0x00000002
395#define SDRAM_CONFIG_SIZE_32M 0x00000003
396#define SDRAM_CONFIG_SIZE_64M 0x00000004
397#define SDRAM_CONFIG_SIZE_128M 0x00000005
398#define SDRAM_CONFIG_SIZE_256M 0x00000006
399#define SDRAM_CONFIG_SIZE_512M 0x00000007
400#define PPC44x_MEM_SIZE_8M 0x00800000
401#define PPC44x_MEM_SIZE_16M 0x01000000
402#define PPC44x_MEM_SIZE_32M 0x02000000
403#define PPC44x_MEM_SIZE_64M 0x04000000
404#define PPC44x_MEM_SIZE_128M 0x08000000
405#define PPC44x_MEM_SIZE_256M 0x10000000
406#define PPC44x_MEM_SIZE_512M 0x20000000
407#define PPC44x_MEM_SIZE_1G 0x40000000
408#define PPC44x_MEM_SIZE_2G 0x80000000
409
410/* 440SP memory controller DCRs */
411#define DCRN_MQ0_BS0BAS 0x40
412#define DCRN_MQ0_BS1BAS 0x41
413
414#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
415#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
416#define MQ0_CONFIG_SIZE_16M 0x0000ff80
417#define MQ0_CONFIG_SIZE_32M 0x0000ff00
418#define MQ0_CONFIG_SIZE_64M 0x0000fe00
419#define MQ0_CONFIG_SIZE_128M 0x0000fc00
420#define MQ0_CONFIG_SIZE_256M 0x0000f800
421#define MQ0_CONFIG_SIZE_512M 0x0000f000
422#define MQ0_CONFIG_SIZE_1G 0x0000e000
423#define MQ0_CONFIG_SIZE_2G 0x0000c000
424
425/* Internal SRAM Controller 440GX/440SP */
426#define DCRN_SRAM0_BASE 0x000
427
428#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
429#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
430#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022)
431#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023)
432#define SRAM_SBCR_BAS0 0x80000000
433#define SRAM_SBCR_BAS1 0x80010000
434#define SRAM_SBCR_BAS2 0x80020000
435#define SRAM_SBCR_BAS3 0x80030000
436#define SRAM_SBCR_BU_MASK 0x00000180
437#define SRAM_SBCR_BS_64KB 0x00000800
438#define SRAM_SBCR_BU_RO 0x00000080
439#define SRAM_SBCR_BU_RW 0x00000180
440#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024)
441#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025)
442#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026)
443#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027)
444#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028)
445#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029)
446#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
447#define SRAM_DPC_ENABLE 0x80000000
448
449/* L2 Cache Controller 440GX/440SP */
450#define DCRN_L2C0_CFG 0x030
451#define L2C_CFG_L2M 0x80000000
452#define L2C_CFG_ICU 0x40000000
453#define L2C_CFG_DCU 0x20000000
454#define L2C_CFG_DCW_MASK 0x1e000000
455#define L2C_CFG_TPC 0x01000000
456#define L2C_CFG_CPC 0x00800000
457#define L2C_CFG_FRAN 0x00200000
458#define L2C_CFG_SS_MASK 0x00180000
459#define L2C_CFG_SS_256 0x00000000
460#define L2C_CFG_CPIM 0x00040000
461#define L2C_CFG_TPIM 0x00020000
462#define L2C_CFG_LIM 0x00010000
463#define L2C_CFG_PMUX_MASK 0x00007000
464#define L2C_CFG_PMUX_SNP 0x00000000
465#define L2C_CFG_PMUX_IF 0x00001000
466#define L2C_CFG_PMUX_DF 0x00002000
467#define L2C_CFG_PMUX_DS 0x00003000
468#define L2C_CFG_PMIM 0x00000800
469#define L2C_CFG_TPEI 0x00000400
470#define L2C_CFG_CPEI 0x00000200
471#define L2C_CFG_NAM 0x00000100
472#define L2C_CFG_SMCM 0x00000080
473#define L2C_CFG_NBRM 0x00000040
474#define DCRN_L2C0_CMD 0x031
475#define L2C_CMD_CLR 0x80000000
476#define L2C_CMD_DIAG 0x40000000
477#define L2C_CMD_INV 0x20000000
478#define L2C_CMD_CCP 0x10000000
479#define L2C_CMD_CTE 0x08000000
480#define L2C_CMD_STRC 0x04000000
481#define L2C_CMD_STPC 0x02000000
482#define L2C_CMD_RPMC 0x01000000
483#define L2C_CMD_HCC 0x00800000
484#define DCRN_L2C0_ADDR 0x032
485#define DCRN_L2C0_DATA 0x033
486#define DCRN_L2C0_SR 0x034
487#define L2C_SR_CC 0x80000000
488#define L2C_SR_CPE 0x40000000
489#define L2C_SR_TPE 0x20000000
490#define L2C_SR_LRU 0x10000000
491#define L2C_SR_PCS 0x08000000
492#define DCRN_L2C0_REVID 0x035
493#define DCRN_L2C0_SNP0 0x036
494#define DCRN_L2C0_SNP1 0x037
495#define L2C_SNP_BA_MASK 0xffff0000
496#define L2C_SNP_SSR_MASK 0x0000f000
497#define L2C_SNP_SSR_32G 0x0000f000
498#define L2C_SNP_ESR 0x00000800
499
500/*
501 * PCI-X definitions
502 */
503#define PCIX0_CFGA 0x0ec00000UL
504#define PCIX1_CFGA 0x1ec00000UL
505#define PCIX2_CFGA 0x2ec00000UL
506#define PCIX0_CFGD 0x0ec00004UL
507#define PCIX1_CFGD 0x1ec00004UL
508#define PCIX2_CFGD 0x2ec00004UL
509
510#define PCIX0_IO_BASE 0x0000000908000000ULL
511#define PCIX1_IO_BASE 0x0000000908000000ULL
512#define PCIX2_IO_BASE 0x0000000908000000ULL
513#define PCIX_IO_SIZE 0x00010000
514
515#ifdef CONFIG_440SP
516#define PCIX0_REG_BASE 0x000000090ec80000ULL
517#else
518#define PCIX0_REG_BASE 0x000000020ec80000ULL
519#endif
520#define PCIX_REG_OFFSET 0x10000000
521#define PCIX_REG_SIZE 0x200
522
523#define PCIX0_VENDID 0x000
524#define PCIX0_DEVID 0x002
525#define PCIX0_COMMAND 0x004
526#define PCIX0_STATUS 0x006
527#define PCIX0_REVID 0x008
528#define PCIX0_CLS 0x009
529#define PCIX0_CACHELS 0x00c
530#define PCIX0_LATTIM 0x00d
531#define PCIX0_HDTYPE 0x00e
532#define PCIX0_BIST 0x00f
533#define PCIX0_BAR0L 0x010
534#define PCIX0_BAR0H 0x014
535#define PCIX0_BAR1 0x018
536#define PCIX0_BAR2L 0x01c
537#define PCIX0_BAR2H 0x020
538#define PCIX0_BAR3 0x024
539#define PCIX0_CISPTR 0x028
540#define PCIX0_SBSYSVID 0x02c
541#define PCIX0_SBSYSID 0x02e
542#define PCIX0_EROMBA 0x030
543#define PCIX0_CAP 0x034
544#define PCIX0_RES0 0x035
545#define PCIX0_RES1 0x036
546#define PCIX0_RES2 0x038
547#define PCIX0_INTLN 0x03c
548#define PCIX0_INTPN 0x03d
549#define PCIX0_MINGNT 0x03e
550#define PCIX0_MAXLTNCY 0x03f
551#define PCIX0_BRDGOPT1 0x040
552#define PCIX0_BRDGOPT2 0x044
553#define PCIX0_ERREN 0x050
554#define PCIX0_ERRSTS 0x054
555#define PCIX0_PLBBESR 0x058
556#define PCIX0_PLBBEARL 0x05c
557#define PCIX0_PLBBEARH 0x060
558#define PCIX0_POM0LAL 0x068
559#define PCIX0_POM0LAH 0x06c
560#define PCIX0_POM0SA 0x070
561#define PCIX0_POM0PCIAL 0x074
562#define PCIX0_POM0PCIAH 0x078
563#define PCIX0_POM1LAL 0x07c
564#define PCIX0_POM1LAH 0x080
565#define PCIX0_POM1SA 0x084
566#define PCIX0_POM1PCIAL 0x088
567#define PCIX0_POM1PCIAH 0x08c
568#define PCIX0_POM2SA 0x090
569#define PCIX0_PIM0SAL 0x098
570#define PCIX0_PIM0SA PCIX0_PIM0SAL
571#define PCIX0_PIM0LAL 0x09c
572#define PCIX0_PIM0LAH 0x0a0
573#define PCIX0_PIM1SA 0x0a4
574#define PCIX0_PIM1LAL 0x0a8
575#define PCIX0_PIM1LAH 0x0ac
576#define PCIX0_PIM2SAL 0x0b0
577#define PCIX0_PIM2SA PCIX0_PIM2SAL
578#define PCIX0_PIM2LAL 0x0b4
579#define PCIX0_PIM2LAH 0x0b8
580#define PCIX0_OMCAPID 0x0c0
581#define PCIX0_OMNIPTR 0x0c1
582#define PCIX0_OMMC 0x0c2
583#define PCIX0_OMMA 0x0c4
584#define PCIX0_OMMUA 0x0c8
585#define PCIX0_OMMDATA 0x0cc
586#define PCIX0_OMMEOI 0x0ce
587#define PCIX0_PMCAPID 0x0d0
588#define PCIX0_PMNIPTR 0x0d1
589#define PCIX0_PMC 0x0d2
590#define PCIX0_PMCSR 0x0d4
591#define PCIX0_PMCSRBSE 0x0d6
592#define PCIX0_PMDATA 0x0d7
593#define PCIX0_PMSCRR 0x0d8
594#define PCIX0_CAPID 0x0dc
595#define PCIX0_NIPTR 0x0dd
596#define PCIX0_CMD 0x0de
597#define PCIX0_STS 0x0e0
598#define PCIX0_IDR 0x0e4
599#define PCIX0_CID 0x0e8
600#define PCIX0_RID 0x0ec
601#define PCIX0_PIM0SAH 0x0f8
602#define PCIX0_PIM2SAH 0x0fc
603#define PCIX0_MSGIL 0x100
604#define PCIX0_MSGIH 0x104
605#define PCIX0_MSGOL 0x108
606#define PCIX0_MSGOH 0x10c
607#define PCIX0_IM 0x1f8
608
609#define IIC_OWN 0x55
610#define IIC_CLOCK 50
611
612#undef NR_UICS
613#ifdef CONFIG_440GX
614#define NR_UICS 3
615#else
616#define NR_UICS 2
617#endif
618
619#include <asm/ibm4xx.h>
620
621#endif /* __ASSEMBLY__ */
622#endif /* __ASM_IBM44x_H__ */
623#endif /* __KERNEL__ */