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Linux kernel mirror (for testing)
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linux
1/*
2 * linux/include/asm/arch-omap/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08
45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Powermanagement bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES 0x00000fff
56#define PERIPHERAL_ENABLE 0x2
57
58#define SELF_REFRESH_MODE 0x0c000001
59#define IDLE_EMIFS_REQUEST 0xc
60#define MODEM_32K_EN 0x1
61#define PER_EN 0x1
62
63#define CPU_SUSPEND_SIZE 200
64#define ULPD_LOW_POWER_EN 0x0001
65
66#define DSP_IDLE_DELAY 10
67#define DSP_IDLE 0x0040
68#define DSP_RST 0x0004
69#define DSP_ENABLE 0x0002
70#define SUFFICIENT_DSP_RESET_TIME 1000
71#define DEFAULT_MPUI_CONFIG 0x05cf
72#define ENABLE_XORCLK 0x2
73#define DSP_CLOCK_ENABLE 0x2000
74#define DSP_IDLE_MODE 0x2
75#define TC_IDLE_REQUEST (0x0000000c)
76
77#define IRQ_LEVEL2 (1<<0)
78#define IRQ_KEYBOARD (1<<1)
79#define IRQ_UART2 (1<<15)
80
81#define PDE_BIT 0x08
82#define PWD_EN_BIT 0x04
83#define EN_PERCK_BIT 0x04
84
85#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
86#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
87#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
88#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
89#define OMAP1510_ULPD_LOW_POWER_REQ 0x0001
90
91#define OMAP1610_DEEP_SLEEP_REQUEST 0x17c7
92#define OMAP1610_BIG_SLEEP_REQUEST TBD
93#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
94#define OMAP1610_IDLE_CLOCK_DOMAINS 0x09c7
95#define OMAP1610_ULPD_LOW_POWER_REQ 0x3
96
97#ifndef OMAP1510_SRAM_IDLE_SUSPEND
98#define OMAP1510_SRAM_IDLE_SUSPEND 0
99#endif
100#ifndef OMAP1610_SRAM_IDLE_SUSPEND
101#define OMAP1610_SRAM_IDLE_SUSPEND 0
102#endif
103#ifndef OMAP5912_SRAM_IDLE_SUSPEND
104#define OMAP5912_SRAM_IDLE_SUSPEND 0
105#endif
106
107#ifndef OMAP1510_SRAM_API_SUSPEND
108#define OMAP1510_SRAM_API_SUSPEND 0
109#endif
110#ifndef OMAP1610_SRAM_API_SUSPEND
111#define OMAP1610_SRAM_API_SUSPEND 0
112#endif
113#ifndef OMAP5912_SRAM_API_SUSPEND
114#define OMAP5912_SRAM_API_SUSPEND 0
115#endif
116
117#if !defined(CONFIG_ARCH_OMAP1510) && \
118 !defined(CONFIG_ARCH_OMAP16XX)
119#error "Power management for this processor not implemented yet"
120#endif
121
122#ifndef __ASSEMBLER__
123extern void omap_pm_idle(void);
124extern void omap_pm_suspend(void);
125extern int omap1510_cpu_suspend(unsigned short, unsigned short);
126extern int omap1610_cpu_suspend(unsigned short, unsigned short);
127extern int omap1510_idle_loop_suspend(void);
128extern int omap1610_idle_loop_suspend(void);
129extern unsigned int omap1510_cpu_suspend_sz;
130extern unsigned int omap1510_idle_loop_suspend_sz;
131extern unsigned int omap1610_cpu_suspend_sz;
132extern unsigned int omap1610_idle_loop_suspend_sz;
133
134#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
135#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
136#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
137
138#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
139#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
140#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
141
142#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
143#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
144#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
145
146#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
147#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
148#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
149
150/*
151 * List of global OMAP registers to preserve.
152 * More ones like CP and general purpose register values are preserved
153 * with the stack pointer in sleep.S.
154 */
155
156enum arm_save_state {
157 ARM_SLEEP_SAVE_START = 0,
158 /*
159 * MPU control registers 32 bits
160 */
161 ARM_SLEEP_SAVE_ARM_CKCTL,
162 ARM_SLEEP_SAVE_ARM_IDLECT1,
163 ARM_SLEEP_SAVE_ARM_IDLECT2,
164 ARM_SLEEP_SAVE_ARM_EWUPCT,
165 ARM_SLEEP_SAVE_ARM_RSTCT1,
166 ARM_SLEEP_SAVE_ARM_RSTCT2,
167 ARM_SLEEP_SAVE_ARM_SYSST,
168 ARM_SLEEP_SAVE_SIZE
169};
170
171enum ulpd_save_state {
172 ULPD_SLEEP_SAVE_START = 0,
173 /*
174 * ULPD registers 16 bits
175 */
176 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
177 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
178 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
179 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
180 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
181 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
182 ULPD_SLEEP_SAVE_SIZE
183};
184
185enum mpui1510_save_state {
186 MPUI1510_SLEEP_SAVE_START = 0,
187 /*
188 * MPUI registers 32 bits
189 */
190 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
191 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
192 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
193 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
194 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
195 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
196 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
197 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
198#if defined(CONFIG_ARCH_OMAP1510)
199 MPUI1510_SLEEP_SAVE_SIZE
200#else
201 MPUI1510_SLEEP_SAVE_SIZE = 0
202#endif
203};
204
205enum mpui1610_save_state {
206 MPUI1610_SLEEP_SAVE_START = 0,
207 /*
208 * MPUI registers 32 bits
209 */
210 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
211 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
212 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
213 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
214 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
215 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
216 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
217 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
218 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
219 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
220 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
221#if defined(CONFIG_ARCH_OMAP16XX)
222 MPUI1610_SLEEP_SAVE_SIZE
223#else
224 MPUI1610_SLEEP_SAVE_SIZE = 0
225#endif
226};
227
228#endif /* ASSEMBLER */
229#endif /* __ASM_ARCH_OMAP_PM_H */